diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-10-27 23:47:05 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-10-29 17:24:30 +0900 |
| commit | 76466bd7be58c0059e5d44b31907cd1066b9697b (patch) | |
| tree | 8e9044cacb1a8d9cd76852ce1a922f3b8b33320d | |
| parent | a8b66ac87cc1d6ffd1b3693514e60edcf61fb678 (diff) | |
ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabled
At the moment, the clk driver is not clever enough to automatically
enable parent clocks like Linux. Enable the STDMAC clock explicitly
if USB is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| -rw-r--r-- | arch/arm/mach-uniphier/clk/clk-ld11.c | 11 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/sc64-regs.h | 2 |
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index 92a07338a8..ca8737d2ff 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -9,6 +9,7 @@ #include <linux/io.h> #include "../init.h" +#include "../sc64-regs.h" #include "../sg-regs.h" void uniphier_ld11_clk_init(void) @@ -25,4 +26,14 @@ void uniphier_ld11_clk_init(void) writel(3, SG_ETPHYPSHUT); writel(7, SG_ETPHYCNT); } + +#ifdef CONFIG_USB_EHCI + { + /* FIXME: the current clk driver can not handle parents */ + u32 tmp; + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC; + writel(tmp, SC_CLKCTRL4); + } +#endif } diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index b0a4281f44..d3aa18530d 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -52,6 +52,8 @@ #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) +#define SC_CLKCTRL4_MIO (1 << 10) +#define SC_CLKCTRL4_STDMAC (1 << 8) #define SC_CLKCTRL4_PERI (1 << 7) #define SC_CLKCTRL4_ETHER (1 << 6) #define SC_CLKCTRL4_NAND (1 << 0) |