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authormichael <trimarchi@gandalf.sssup.it>2011-03-14 21:16:38 +0000
committerScott Wood <scottwood@freescale.com>2011-04-01 14:49:08 -0500
commit67a490d60d70f2b01d55976440ba30154af96965 (patch)
treef81853db25b1830e3ccde5d2fbee8ea7ab8419e2
parent0272c718ba69c60a9d719db6806971d98db98090 (diff)
atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN
If NCE is hooked up to NCS3, we don't need to (and can't) explicitly set the state of the NCE pin. Instead, the controller asserts it automatically as part of a command/data access. Only "CE don't care"-type NAND chips can be used in this manner. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
-rw-r--r--drivers/mtd/nand/atmel_nand.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index ab8bbb3aea1..818d3624a7e 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -249,8 +249,10 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
if (ctrl & NAND_ALE)
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
+#ifdef CONFIG_SYS_NAND_ENABLE_PIN
at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
!(ctrl & NAND_NCE));
+#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
}