diff options
| author | Ye Li <ye.li@nxp.com> | 2018-11-20 23:42:04 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2019-05-29 20:02:04 -0700 |
| commit | 1e5548d6a7f17e7fe67d67325ee1882dd1b6190c (patch) | |
| tree | 690b8f9fbee4166fa3442dd104dff72723da49d4 | |
| parent | ab8b408407f55ce55214312c1f5726382d337bd2 (diff) | |
MLK-21889-9 DTS: imx8mn: Add binding files and imx8mn.dtsi
Add soc DTSi and clock/pinctrl binding files. The pinctrl binding
file is v0.03 generated by tool
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | arch/arm/dts/fsl-imx8mn.dtsi | 867 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx8mn-clock.h | 460 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pins-imx8mn.h | 646 |
3 files changed, 1973 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-imx8mn.dtsi b/arch/arm/dts/fsl-imx8mn.dtsi new file mode 100644 index 0000000000..c1dc4caec3 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mn.dtsi @@ -0,0 +1,867 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8-ca53.dtsi" +#include <dt-bindings/clock/imx8mn-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/pins-imx8mn.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "fsl,imx8mn"; + interrupt-parent = <&gpc>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + spi0 = &flexspi0; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + cpus { + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x80000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc_32k: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock@2 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock@3 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock@4 { + compatible = "fixed-clock"; + reg = <5>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock@5 { + compatible = "fixed-clock"; + reg = <6>; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + }; + + mipi_pd: gpc_power_domain@0 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <0>; + domain-name = "MIPI_PD"; + }; + + usb_otg1_pd: gpc_power_domain@2 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <2>; + domain-name = "USB_OTG1_PD"; + }; + + usb_otg2_pd: gpc_power_domain@3 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <3>; + domain-name = "USB_OTG2_PD"; + }; + + gpu_2d_pd: gpc_power_domain@4 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <4>; + domain-name = "GPU_2D_PD"; + }; + + gpu_mix_pd: gpc_power_domain@5 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <5>; + domain-name = "GPU_MIX_PD"; + }; + + disp_mix_pd: gpc_power_domain@7 { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-id = <7>; + domain-name = "DISP_MIX_PD"; + }; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30200000 0x0 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30210000 0x0 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30220000 0x0 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30230000 0x0 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30240000 0x0 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x0 0x30260000 0x0 0x10000>; + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + u-boot,dm-pre-reloc; + #thermal-sensor-cells = <0>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x0 0x30340000 0x0 0x10000>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; + reg = <0x0 0x30360000 0x0 0x10000>; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x0 0x30370000 0x0 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x0 0x30380000 0x0 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + src: src@30390000 { + compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; + reg = <0x0 0x30390000 0x0 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc", "syscon"; + reg = <0x0 0x303a0000 0x0 0x10000>; + interrupt-controller; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x0 0x306a0000 0x0 0x10000>, /* system-counter-rd base */ + <0x0 0x306b0000 0x0 0x10000>, /* system-counter-cmp base */ + <0x0 0x306c0000 0x0 0x10000>; /* system-counter-ctrl base */ + clock-frequency = <8000000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30860000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + clocks = <&clk IMX8MN_CLK_UART1_ROOT>, + <&clk IMX8MN_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30880000 0x0 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + clocks = <&clk IMX8MN_CLK_UART3_ROOT>, + <&clk IMX8MN_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30890000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + clocks = <&clk IMX8MN_CLK_UART2_ROOT>, + <&clk IMX8MN_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a20000 0x0 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a30000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a40000 0x0 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a50000 0x0 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + usbotg1: usb@32e40000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x32e40000 0x0 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS_SRC>, + <&clk IMX8MN_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MN_CLK_USB_PHY_REF_SRC>; + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc1: usbmisc@32e40200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x32e40200 0x0 0x200>; + }; + + usbotg2: usb@32e50000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x32e50000 0x0 0x200>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS_SRC>, + <&clk IMX8MN_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MN_CLK_USB_PHY_REF_SRC>; + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc2: usbmisc@32e50200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x32e50200 0x0 0x200>; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b40000 0x0 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MN_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MN_CLK_USDHC1_DIV>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b50000 0x0 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MN_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b60000 0x0 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MN_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + sai1: sai@30010000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30010000 0x0 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI1_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI1_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0xff 0xff>; + status = "disabled"; + }; + + sai2: sai@30020000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30020000 0x0 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI2_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI2_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x0 0x30030000 0x0 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x0 0x30050000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 24 0>, <&sdma2 9 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30060000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 24 0>, <&sdma2 11 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + micfil: micfil@30080000 { + compatible = "fsl,imx9mq-micfil"; + reg = <0x0 0x30080000 0x0 0x10000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_PDM_IPG>, + <&clk IMX8MN_CLK_PDM_ROOT>; + clock-names = "ipg_clk", "ipg_clk_app"; + dmas = <&sdma2 24 24 0>; + dma-names = "rx"; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx8mm-spdif", "fsl,imx8mq-spdif", "fsl,imx35-spdif"; + reg = <0x0 0x30090000 0x0 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, /* core */ + <&clk IMX8MN_CLK_24M>, /* rxtx0 */ + <&clk IMX8MN_CLK_SPDIF1_DIV>, /* rxtx1 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, /* rxtx5 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MN_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x30bd0000 0x0 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, + <&clk IMX8MN_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + status = "okay"; + }; + + sdma2: dma-controller@302c0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302c0000 0x0 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, + <&clk IMX8MN_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "okay"; + }; + + sdma3: dma-controller@302b0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302b0000 0x0 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, + <&clk IMX8MN_CLK_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "okay"; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30280000 0 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30290000 0 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x302a0000 0 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x0 0x30be0000 0x0 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, + <&clk IMX8MN_CLK_ENET1_ROOT>, + <&clk IMX8MN_CLK_ENET_TIMER_DIV>, + <&clk IMX8MN_CLK_ENET_REF_DIV>, + <&clk IMX8MN_CLK_ENET_PHY_REF_DIV>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI_SRC>, + <&clk IMX8MN_CLK_ENET_TIMER_SRC>, + <&clk IMX8MN_CLK_ENET_REF_SRC>, + <&clk IMX8MN_CLK_ENET_TIMER_DIV>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + stop-mode = <&gpr 0x10 3>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + flexspi0: flexspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-flexspi"; + reg = <0x0 0x30bb0000 0x0 0x10000>, + <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, + <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + lcdif: lcdif@32E00000 { + compatible = "fsl,imx8mm-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x32e00000 0x0 0x10000>; + clocks = <&clk IMX8MN_CLK_LCDIF_PIXEL_DIV>; + clock-names = "pix"; + assigned-clocks = <&clk IMX8MN_CLK_LCDIF_PIXEL_SRC>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rate = <594000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + max-res = <1920>, <1080>; + status = "disabled"; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; + }; + + mipi_dsi_phy: dsi_phy@32e10300 { + compatible = "mixel,imx8mm-mipi-dsi-phy", + "mixel,imx8mq-mipi-dsi-phy"; + reg = <0x0 0x32e10300 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge: mipi_dsi_bridge@32E10000 { + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x32e10000 0x0 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_DSI_PHY_REF_DIV>, + <&clk IMX8MN_CLK_DSI_ESC_RX_DIV>, + <&clk IMX8MN_CLK_IPG_DSI_ESC_RX_ROOT>; + clock-names = "phy_ref", "rx_esc", "tx_esc"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_ESC_RX_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + assigned-clock-rates = <80000000>; + phys = <&mipi_dsi_phy>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32E10000 { + compatible = "fsl,imx8mm-mipi-dsi_drm", "fsl,imx8mq-mipi-dsi_drm"; + clocks = <&clk IMX8MN_CLK_DSI_CORE_DIV>, + <&clk IMX8MN_CLK_DSI_PHY_REF_DIV>; + clock-names = "core", "phy_ref"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE_SRC>, + <&clk IMX8MN_CLK_DSI_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + src = <&src>; + mux-sel = <&gpr>; + phys = <&mipi_dsi_phy>; + phys-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge_in>; + }; + }; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + }; +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + 1800000 1000000 + 1600000 900000 + 1200000 800000 + >; + clocks = <&clk IMX8MN_CLK_A53_DIV>, <&clk IMX8MN_CLK_A53_SRC>, + <&clk IMX8MM_ARM_PLL>, <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>; + clock-names = "a53", "arm_a53_src", "arm_pll", + "arm_pll_out", "sys1_pll_800m"; + clock-latency = <61036>; + #cooling-cells = <2>; +}; diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h new file mode 100644 index 0000000000..ad8e2d31f5 --- /dev/null +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -0,0 +1,460 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H +#define __DT_BINDINGS_CLOCK_IMX8MM_H + +#define IMX8MN_CLK_DUMMY 0 +#define IMX8MN_CLK_32K 1 +#define IMX8MN_CLK_24M 2 +#define IMX8MM_OSC_HDMI_CLK 3 +#define IMX8MN_CLK_EXT1 4 +#define IMX8MN_CLK_EXT2 5 +#define IMX8MN_CLK_EXT3 6 +#define IMX8MN_CLK_EXT4 7 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_DRAM_PLL_REF_SEL 11 +#define IMX8MM_GPU_PLL_REF_SEL 12 +#define IMX8MM_VPU_PLL_REF_SEL 13 +#define IMX8MM_ARM_PLL_REF_SEL 14 +#define IMX8MM_SYS_PLL1_REF_SEL 15 +#define IMX8MM_SYS_PLL2_REF_SEL 16 +#define IMX8MM_SYS_PLL3_REF_SEL 17 +#define IMX8MM_AUDIO_PLL1 18 +#define IMX8MM_AUDIO_PLL2 19 +#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_DRAM_PLL 21 +#define IMX8MM_GPU_PLL 22 +#define IMX8MM_VPU_PLL 23 +#define IMX8MM_ARM_PLL 24 +#define IMX8MM_SYS_PLL1 25 +#define IMX8MM_SYS_PLL2 26 +#define IMX8MM_SYS_PLL3 27 +#define IMX8MM_AUDIO_PLL1_BYPASS 28 +#define IMX8MM_AUDIO_PLL2_BYPASS 29 +#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_DRAM_PLL_BYPASS 31 +#define IMX8MM_GPU_PLL_BYPASS 32 +#define IMX8MM_VPU_PLL_BYPASS 33 +#define IMX8MM_ARM_PLL_BYPASS 34 +#define IMX8MM_SYS_PLL1_BYPASS 35 +#define IMX8MM_SYS_PLL2_BYPASS 36 +#define IMX8MM_SYS_PLL3_BYPASS 37 +#define IMX8MM_AUDIO_PLL1_OUT 38 +#define IMX8MM_AUDIO_PLL2_OUT 39 +#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_DRAM_PLL_OUT 41 +#define IMX8MM_GPU_PLL_OUT 42 +#define IMX8MM_VPU_PLL_OUT 43 +#define IMX8MM_ARM_PLL_OUT 44 +#define IMX8MM_SYS_PLL1_OUT 45 +#define IMX8MM_SYS_PLL2_OUT 46 +#define IMX8MM_SYS_PLL3_OUT 47 +#define IMX8MM_SYS_PLL1_40M 48 +#define IMX8MM_SYS_PLL1_80M 49 +#define IMX8MM_SYS_PLL1_100M 50 +#define IMX8MM_SYS_PLL1_133M 51 +#define IMX8MM_SYS_PLL1_160M 52 +#define IMX8MM_SYS_PLL1_200M 53 +#define IMX8MM_SYS_PLL1_266M 54 +#define IMX8MM_SYS_PLL1_400M 55 +#define IMX8MM_SYS_PLL1_800M 56 +#define IMX8MM_SYS_PLL2_50M 57 +#define IMX8MM_SYS_PLL2_100M 58 +#define IMX8MM_SYS_PLL2_125M 59 +#define IMX8MM_SYS_PLL2_166M 60 +#define IMX8MM_SYS_PLL2_200M 61 +#define IMX8MM_SYS_PLL2_250M 62 +#define IMX8MM_SYS_PLL2_333M 63 +#define IMX8MM_SYS_PLL2_500M 64 +#define IMX8MM_SYS_PLL2_1000M 65 +#define IMX8MN_CLK_A53_SRC 66 +#define IMX8MN_CLK_M4_SRC 67 +#define IMX8MN_CLK_VPU_SRC 68 +#define IMX8MN_CLK_GPU3D_SRC 69 +#define IMX8MN_CLK_GPU2D_SRC 70 +#define IMX8MN_CLK_A53_CG 71 +#define IMX8MN_CLK_M4_CG 72 +#define IMX8MN_CLK_VPU_CG 73 +#define IMX8MN_CLK_GPU3D_CG 74 +#define IMX8MN_CLK_GPU2D_CG 75 +#define IMX8MN_CLK_A53_DIV 76 +#define IMX8MN_CLK_M4_DIV 77 +#define IMX8MN_CLK_VPU_DIV 78 +#define IMX8MN_CLK_GPU3D_DIV 79 +#define IMX8MN_CLK_GPU2D_DIV 80 +#define IMX8MN_CLK_MAIN_AXI_SRC 81 +#define IMX8MN_CLK_ENET_AXI_SRC 82 +#define IMX8MN_CLK_NAND_USDHC_BUS_SRC 83 +#define IMX8MN_CLK_VPU_BUS_SRC 84 +#define IMX8MN_CLK_DISP_AXI_SRC 85 +#define IMX8MN_CLK_DISP_APB_SRC 86 +#define IMX8MN_CLK_DISP_RTRM_SRC 87 +#define IMX8MN_CLK_USB_BUS_SRC 88 +#define IMX8MN_CLK_GPU_AXI_SRC 89 +#define IMX8MN_CLK_GPU_AHB_SRC 90 +#define IMX8MN_CLK_NOC_SRC 91 +#define IMX8MN_CLK_NOC_APB_SRC 92 +#define IMX8MN_CLK_MAIN_AXI_CG 93 +#define IMX8MN_CLK_ENET_AXI_CG 94 +#define IMX8MN_CLK_NAND_USDHC_BUS_CG 95 +#define IMX8MN_CLK_VPU_BUS_CG 96 +#define IMX8MN_CLK_DISP_AXI_CG 97 +#define IMX8MN_CLK_DISP_APB_CG 98 +#define IMX8MN_CLK_DISP_RTRM_CG 99 +#define IMX8MN_CLK_USB_BUS_CG 100 +#define IMX8MN_CLK_GPU_AXI_CG 101 +#define IMX8MN_CLK_GPU_AHB_CG 102 +#define IMX8MN_CLK_NOC_CG 103 +#define IMX8MN_CLK_NOC_APB_CG 104 +#define IMX8MN_CLK_MAIN_AXI_PRE_DIV 105 +#define IMX8MN_CLK_ENET_AXI_PRE_DIV 106 +#define IMX8MN_CLK_NAND_USDHC_BUS_PRE_DIV 107 +#define IMX8MN_CLK_VPU_BUS_PRE_DIV 108 +#define IMX8MN_CLK_DISP_AXI_PRE_DIV 109 +#define IMX8MN_CLK_DISP_APB_PRE_DIV 110 +#define IMX8MN_CLK_DISP_RTRM_PRE_DIV 111 +#define IMX8MN_CLK_USB_BUS_PRE_DIV 112 +#define IMX8MN_CLK_GPU_AXI_PRE_DIV 113 +#define IMX8MN_CLK_GPU_AHB_PRE_DIV 114 +#define IMX8MN_CLK_NOC_PRE_DIV 115 +#define IMX8MN_CLK_NOC_APB_PRE_DIV 116 +#define IMX8MN_CLK_MAIN_AXI_DIV 117 +#define IMX8MN_CLK_ENET_AXI_DIV 118 +#define IMX8MN_CLK_NAND_USDHC_BUS_DIV 119 +#define IMX8MN_CLK_VPU_BUS_DIV 120 +#define IMX8MN_CLK_DISP_AXI_DIV 121 +#define IMX8MN_CLK_DISP_APB_DIV 122 +#define IMX8MN_CLK_DISP_RTRM_DIV 123 +#define IMX8MN_CLK_USB_BUS_DIV 124 +#define IMX8MN_CLK_GPU_AXI_DIV 125 +#define IMX8MN_CLK_GPU_AHB_DIV 126 +#define IMX8MN_CLK_NOC_DIV 127 +#define IMX8MN_CLK_NOC_APB_DIV 128 +#define IMX8MN_CLK_AHB_SRC 129 +#define IMX8MN_CLK_AUDIO_AHB_SRC 130 +#define IMX8MN_CLK_DSI_ESC_RX_SRC 131 +#define IMX8MN_CLK_AHB_CG 132 +#define IMX8MN_CLK_AUDIO_AHB_CG 133 +#define IMX8MN_CLK_DSI_ESC_RX_CG 134 +#define IMX8MN_CLK_AHB_PRE_DIV 135 +#define IMX8MN_CLK_AUDIO_AHB_PRE_DIV 136 +#define IMX8MN_CLK_DSI_ESC_RX_PRE_DIV 137 +#define IMX8MN_CLK_AHB_DIV 138 +#define IMX8MN_CLK_AUDIO_AHB_DIV 139 +#define IMX8MN_CLK_DSI_ESC_RX_DIV 140 +#define IMX8MN_CLK_IPG_ROOT 141 +#define IMX8MN_CLK_IPG_AUDIO_ROOT 142 +#define IMX8MN_CLK_IPG_DSI_ESC_RX_ROOT 143 +#define IMX8MN_CLK_DRAM_ALT_SRC 144 +#define IMX8MN_CLK_DRAM_APB_SRC 145 +#define IMX8MN_CLK_VPU_G1_SRC 146 +#define IMX8MN_CLK_VPU_G2_SRC 147 +#define IMX8MN_CLK_DISP_DTRC_SRC 148 +#define IMX8MN_CLK_DISP_DC8000_SRC 149 +#define IMX8MN_CLK_PCIE1_CTRL_SRC 150 +#define IMX8MN_CLK_PCIE1_PHY_SRC 151 +#define IMX8MN_CLK_PCIE1_AUX_SRC 152 +#define IMX8MN_CLK_DC_PIXEL_SRC 153 +#define IMX8MN_CLK_LCDIF_PIXEL_SRC 154 +#define IMX8MN_CLK_SAI1_SRC 155 +#define IMX8MN_CLK_SAI2_SRC 156 +#define IMX8MN_CLK_SAI3_SRC 157 +#define IMX8MN_CLK_SAI4_SRC 158 +#define IMX8MN_CLK_SAI5_SRC 159 +#define IMX8MN_CLK_SAI6_SRC 160 +#define IMX8MN_CLK_SPDIF1_SRC 161 +#define IMX8MN_CLK_SPDIF2_SRC 162 +#define IMX8MN_CLK_ENET_REF_SRC 163 +#define IMX8MN_CLK_ENET_TIMER_SRC 164 +#define IMX8MN_CLK_ENET_PHY_REF_SRC 165 +#define IMX8MN_CLK_NAND_SRC 166 +#define IMX8MN_CLK_QSPI_SRC 167 +#define IMX8MN_CLK_USDHC1_SRC 168 +#define IMX8MN_CLK_USDHC2_SRC 169 +#define IMX8MN_CLK_I2C1_SRC 170 +#define IMX8MN_CLK_I2C2_SRC 171 +#define IMX8MN_CLK_I2C3_SRC 172 +#define IMX8MN_CLK_I2C4_SRC 173 +#define IMX8MN_CLK_UART1_SRC 174 +#define IMX8MN_CLK_UART2_SRC 175 +#define IMX8MN_CLK_UART3_SRC 176 +#define IMX8MN_CLK_UART4_SRC 177 +#define IMX8MN_CLK_USB_CORE_REF_SRC 178 +#define IMX8MN_CLK_USB_PHY_REF_SRC 179 +#define IMX8MN_CLK_ECSPI1_SRC 180 +#define IMX8MN_CLK_ECSPI2_SRC 181 +#define IMX8MN_CLK_PWM1_SRC 182 +#define IMX8MN_CLK_PWM2_SRC 183 +#define IMX8MN_CLK_PWM3_SRC 184 +#define IMX8MN_CLK_PWM4_SRC 185 +#define IMX8MN_CLK_GPT1_SRC 186 +#define IMX8MN_CLK_WDOG_SRC 187 +#define IMX8MN_CLK_WRCLK_SRC 188 +#define IMX8MN_CLK_DSI_CORE_SRC 189 +#define IMX8MN_CLK_DSI_PHY_REF_SRC 190 +#define IMX8MN_CLK_DSI_DBI_SRC 191 +#define IMX8MN_CLK_USDHC3_SRC 192 +#define IMX8MN_CLK_CSI1_CORE_SRC 193 +#define IMX8MN_CLK_CSI1_PHY_REF_SRC 194 +#define IMX8MN_CLK_CSI1_ESC_SRC 195 +#define IMX8MN_CLK_CSI2_CORE_SRC 196 +#define IMX8MN_CLK_CSI2_PHY_REF_SRC 197 +#define IMX8MN_CLK_CSI2_ESC_SRC 198 +#define IMX8MN_CLK_PCIE2_CTRL_SRC 199 +#define IMX8MN_CLK_PCIE2_PHY_SRC 200 +#define IMX8MN_CLK_PCIE2_AUX_SRC 201 +#define IMX8MN_CLK_ECSPI3_SRC 202 +#define IMX8MN_CLK_PDM_SRC 203 +#define IMX8MN_CLK_VPU_H1_SRC 204 +#define IMX8MN_CLK_DRAM_ALT_CG 205 +#define IMX8MN_CLK_DRAM_APB_CG 206 +#define IMX8MN_CLK_VPU_G1_CG 207 +#define IMX8MN_CLK_VPU_G2_CG 208 +#define IMX8MN_CLK_DISP_DTRC_CG 209 +#define IMX8MN_CLK_DISP_DC8000_CG 210 +#define IMX8MN_CLK_PCIE1_CTRL_CG 211 +#define IMX8MN_CLK_PCIE1_PHY_CG 212 +#define IMX8MN_CLK_PCIE1_AUX_CG 213 +#define IMX8MN_CLK_DC_PIXEL_CG 214 +#define IMX8MN_CLK_LCDIF_PIXEL_CG 215 +#define IMX8MN_CLK_SAI1_CG 216 +#define IMX8MN_CLK_SAI2_CG 217 +#define IMX8MN_CLK_SAI3_CG 218 +#define IMX8MN_CLK_SAI4_CG 219 +#define IMX8MN_CLK_SAI5_CG 220 +#define IMX8MN_CLK_SAI6_CG 221 +#define IMX8MN_CLK_SPDIF1_CG 222 +#define IMX8MN_CLK_SPDIF2_CG 223 +#define IMX8MN_CLK_ENET_REF_CG 224 +#define IMX8MN_CLK_ENET_TIMER_CG 225 +#define IMX8MN_CLK_ENET_PHY_REF_CG 226 +#define IMX8MN_CLK_NAND_CG 227 +#define IMX8MN_CLK_QSPI_CG 228 +#define IMX8MN_CLK_USDHC1_CG 229 +#define IMX8MN_CLK_USDHC2_CG 230 +#define IMX8MN_CLK_I2C1_CG 231 +#define IMX8MN_CLK_I2C2_CG 232 +#define IMX8MN_CLK_I2C3_CG 233 +#define IMX8MN_CLK_I2C4_CG 234 +#define IMX8MN_CLK_UART1_CG 235 +#define IMX8MN_CLK_UART2_CG 236 +#define IMX8MN_CLK_UART3_CG 237 +#define IMX8MN_CLK_UART4_CG 238 +#define IMX8MN_CLK_USB_CORE_REF_CG 239 +#define IMX8MN_CLK_USB_PHY_REF_CG 240 +#define IMX8MN_CLK_ECSPI1_CG 241 +#define IMX8MN_CLK_ECSPI2_CG 242 +#define IMX8MN_CLK_PWM1_CG 243 +#define IMX8MN_CLK_PWM2_CG 244 +#define IMX8MN_CLK_PWM3_CG 245 +#define IMX8MN_CLK_PWM4_CG 246 +#define IMX8MN_CLK_GPT1_CG 247 +#define IMX8MN_CLK_WDOG_CG 248 +#define IMX8MN_CLK_WRCLK_CG 249 +#define IMX8MN_CLK_DSI_CORE_CG 250 +#define IMX8MN_CLK_DSI_PHY_REF_CG 251 +#define IMX8MN_CLK_DSI_DBI_CG 252 +#define IMX8MN_CLK_USDHC3_CG 253 +#define IMX8MN_CLK_CSI1_CORE_CG 254 +#define IMX8MN_CLK_CSI1_PHY_REF_CG 255 +#define IMX8MN_CLK_CSI1_ESC_CG 256 +#define IMX8MN_CLK_CSI2_CORE_CG 257 +#define IMX8MN_CLK_CSI2_PHY_REF_CG 258 +#define IMX8MN_CLK_CSI2_ESC_CG 259 +#define IMX8MN_CLK_PCIE2_CTRL_CG 260 +#define IMX8MN_CLK_PCIE2_PHY_CG 261 +#define IMX8MN_CLK_PCIE2_AUX_CG 262 +#define IMX8MN_CLK_ECSPI3_CG 263 +#define IMX8MN_CLK_PDM_CG 264 +#define IMX8MN_CLK_VPU_H1_CG 265 +#define IMX8MN_CLK_DRAM_ALT_PRE_DIV 266 +#define IMX8MN_CLK_DRAM_APB_PRE_DIV 267 +#define IMX8MN_CLK_VPU_G1_PRE_DIV 268 +#define IMX8MN_CLK_VPU_G2_PRE_DIV 269 +#define IMX8MN_CLK_DISP_DTRC_PRE_DIV 270 +#define IMX8MN_CLK_DISP_DC8000_PRE_DIV 271 +#define IMX8MN_CLK_PCIE1_CTRL_PRE_DIV 272 +#define IMX8MN_CLK_PCIE1_PHY_PRE_DIV 273 +#define IMX8MN_CLK_PCIE1_AUX_PRE_DIV 274 +#define IMX8MN_CLK_DC_PIXEL_PRE_DIV 275 +#define IMX8MN_CLK_LCDIF_PIXEL_PRE_DIV 276 +#define IMX8MN_CLK_SAI1_PRE_DIV 277 +#define IMX8MN_CLK_SAI2_PRE_DIV 278 +#define IMX8MN_CLK_SAI3_PRE_DIV 279 +#define IMX8MN_CLK_SAI4_PRE_DIV 280 +#define IMX8MN_CLK_SAI5_PRE_DIV 281 +#define IMX8MN_CLK_SAI6_PRE_DIV 282 +#define IMX8MN_CLK_SPDIF1_PRE_DIV 283 +#define IMX8MN_CLK_SPDIF2_PRE_DIV 284 +#define IMX8MN_CLK_ENET_REF_PRE_DIV 285 +#define IMX8MN_CLK_ENET_TIMER_PRE_DIV 286 +#define IMX8MN_CLK_ENET_PHY_REF_PRE_DIV 287 +#define IMX8MN_CLK_NAND_PRE_DIV 288 +#define IMX8MN_CLK_QSPI_PRE_DIV 289 +#define IMX8MN_CLK_USDHC1_PRE_DIV 290 +#define IMX8MN_CLK_USDHC2_PRE_DIV 291 +#define IMX8MN_CLK_I2C1_PRE_DIV 292 +#define IMX8MN_CLK_I2C2_PRE_DIV 293 +#define IMX8MN_CLK_I2C3_PRE_DIV 294 +#define IMX8MN_CLK_I2C4_PRE_DIV 295 +#define IMX8MN_CLK_UART1_PRE_DIV 296 +#define IMX8MN_CLK_UART2_PRE_DIV 297 +#define IMX8MN_CLK_UART3_PRE_DIV 298 +#define IMX8MN_CLK_UART4_PRE_DIV 299 +#define IMX8MN_CLK_USB_CORE_REF_PRE_DIV 300 +#define IMX8MN_CLK_USB_PHY_REF_PRE_DIV 301 +#define IMX8MN_CLK_ECSPI1_PRE_DIV 302 +#define IMX8MN_CLK_ECSPI2_PRE_DIV 303 +#define IMX8MN_CLK_PWM1_PRE_DIV 304 +#define IMX8MN_CLK_PWM2_PRE_DIV 305 +#define IMX8MN_CLK_PWM3_PRE_DIV 306 +#define IMX8MN_CLK_PWM4_PRE_DIV 307 +#define IMX8MN_CLK_GPT1_PRE_DIV 308 +#define IMX8MN_CLK_WDOG_PRE_DIV 309 +#define IMX8MN_CLK_WRCLK_PRE_DIV 310 +#define IMX8MN_CLK_DSI_CORE_PRE_DIV 311 +#define IMX8MN_CLK_DSI_PHY_REF_PRE_DIV 312 +#define IMX8MN_CLK_DSI_DBI_PRE_DIV 313 +#define IMX8MN_CLK_USDHC3_PRE_DIV 314 +#define IMX8MN_CLK_CSI1_CORE_PRE_DIV 315 +#define IMX8MN_CLK_CSI1_PHY_REF_PRE_DIV 316 +#define IMX8MN_CLK_CSI1_ESC_PRE_DIV 317 +#define IMX8MN_CLK_CSI2_CORE_PRE_DIV 318 +#define IMX8MN_CLK_CSI2_PHY_REF_PRE_DIV 319 +#define IMX8MN_CLK_CSI2_ESC_PRE_DIV 320 +#define IMX8MN_CLK_PCIE2_CTRL_PRE_DIV 321 +#define IMX8MN_CLK_PCIE2_PHY_PRE_DIV 322 +#define IMX8MN_CLK_PCIE2_AUX_PRE_DIV 323 +#define IMX8MN_CLK_ECSPI3_PRE_DIV 324 +#define IMX8MN_CLK_PDM_PRE_DIV 325 +#define IMX8MN_CLK_VPU_H1_PRE_DIV 326 +#define IMX8MN_CLK_DRAM_ALT_DIV 327 +#define IMX8MN_CLK_DRAM_APB_DIV 328 +#define IMX8MN_CLK_VPU_G1_DIV 329 +#define IMX8MN_CLK_VPU_G2_DIV 330 +#define IMX8MN_CLK_DISP_DTRC_DIV 331 +#define IMX8MN_CLK_DISP_DC8000_DIV 332 +#define IMX8MN_CLK_PCIE1_CTRL_DIV 333 +#define IMX8MN_CLK_PCIE1_PHY_DIV 334 +#define IMX8MN_CLK_PCIE1_AUX_DIV 335 +#define IMX8MN_CLK_DC_PIXEL_DIV 336 +#define IMX8MN_CLK_LCDIF_PIXEL_DIV 337 +#define IMX8MN_CLK_SAI1_DIV 338 +#define IMX8MN_CLK_SAI2_DIV 339 +#define IMX8MN_CLK_SAI3_DIV 340 +#define IMX8MN_CLK_SAI4_DIV 341 +#define IMX8MN_CLK_SAI5_DIV 342 +#define IMX8MN_CLK_SAI6_DIV 343 +#define IMX8MN_CLK_SPDIF1_DIV 344 +#define IMX8MN_CLK_SPDIF2_DIV 345 +#define IMX8MN_CLK_ENET_REF_DIV 346 +#define IMX8MN_CLK_ENET_TIMER_DIV 347 +#define IMX8MN_CLK_ENET_PHY_REF_DIV 348 +#define IMX8MN_CLK_NAND_DIV 349 +#define IMX8MN_CLK_QSPI_DIV 350 +#define IMX8MN_CLK_USDHC1_DIV 351 +#define IMX8MN_CLK_USDHC2_DIV 352 +#define IMX8MN_CLK_I2C1_DIV 353 +#define IMX8MN_CLK_I2C2_DIV 354 +#define IMX8MN_CLK_I2C3_DIV 355 +#define IMX8MN_CLK_I2C4_DIV 356 +#define IMX8MN_CLK_UART1_DIV 357 +#define IMX8MN_CLK_UART2_DIV 358 +#define IMX8MN_CLK_UART3_DIV 359 +#define IMX8MN_CLK_UART4_DIV 360 +#define IMX8MN_CLK_USB_CORE_REF_DIV 361 +#define IMX8MN_CLK_USB_PHY_REF_DIV 362 +#define IMX8MN_CLK_ECSPI1_DIV 363 +#define IMX8MN_CLK_ECSPI2_DIV 364 +#define IMX8MN_CLK_PWM1_DIV 365 +#define IMX8MN_CLK_PWM2_DIV 366 +#define IMX8MN_CLK_PWM3_DIV 367 +#define IMX8MN_CLK_PWM4_DIV 368 +#define IMX8MN_CLK_GPT1_DIV 369 +#define IMX8MN_CLK_WDOG_DIV 370 +#define IMX8MN_CLK_WRCLK_DIV 371 +#define IMX8MN_CLK_DSI_CORE_DIV 372 +#define IMX8MN_CLK_DSI_PHY_REF_DIV 373 +#define IMX8MN_CLK_DSI_DBI_DIV 374 +#define IMX8MN_CLK_USDHC3_DIV 375 +#define IMX8MN_CLK_CSI1_CORE_DIV 376 +#define IMX8MN_CLK_CSI1_PHY_REF_DIV 377 +#define IMX8MN_CLK_CSI1_ESC_DIV 378 +#define IMX8MN_CLK_CSI2_CORE_DIV 379 +#define IMX8MN_CLK_CSI2_PHY_REF_DIV 380 +#define IMX8MN_CLK_CSI2_ESC_DIV 381 +#define IMX8MN_CLK_PCIE2_CTRL_DIV 382 +#define IMX8MN_CLK_PCIE2_PHY_DIV 383 +#define IMX8MN_CLK_PCIE2_AUX_DIV 384 +#define IMX8MN_CLK_ECSPI3_DIV 385 +#define IMX8MN_CLK_PDM_DIV 386 +#define IMX8MN_CLK_VPU_H1_DIV 387 +#define IMX8MN_CLK_ECSPI1_ROOT 388 +#define IMX8MN_CLK_ECSPI2_ROOT 389 +#define IMX8MN_CLK_ECSPI3_ROOT 390 +#define IMX8MN_CLK_ENET1_ROOT 391 +#define IMX8MN_CLK_GPT1_ROOT 392 +#define IMX8MN_CLK_I2C1_ROOT 393 +#define IMX8MN_CLK_I2C2_ROOT 394 +#define IMX8MN_CLK_I2C3_ROOT 395 +#define IMX8MN_CLK_I2C4_ROOT 396 +#define IMX8MN_CLK_OCOTP_ROOT 397 +#define IMX8MN_CLK_PCIE1_ROOT 398 +#define IMX8MN_CLK_PWM1_ROOT 399 +#define IMX8MN_CLK_PWM2_ROOT 400 +#define IMX8MN_CLK_PWM3_ROOT 401 +#define IMX8MN_CLK_PWM4_ROOT 402 +#define IMX8MN_CLK_QSPI_ROOT 403 +#define IMX8MN_CLK_NAND_ROOT 404 +#define IMX8MN_CLK_SAI1_ROOT 405 +#define IMX8MN_CLK_SAI1_IPG 406 +#define IMX8MN_CLK_SAI2_ROOT 407 +#define IMX8MN_CLK_SAI2_IPG 408 +#define IMX8MN_CLK_SAI3_ROOT 409 +#define IMX8MN_CLK_SAI3_IPG 410 +#define IMX8MN_CLK_SAI4_ROOT 411 +#define IMX8MN_CLK_SAI4_IPG 412 +#define IMX8MN_CLK_SAI5_ROOT 413 +#define IMX8MN_CLK_SAI5_IPG 414 +#define IMX8MN_CLK_SAI6_ROOT 415 +#define IMX8MN_CLK_SAI6_IPG 416 +#define IMX8MN_CLK_UART1_ROOT 417 +#define IMX8MN_CLK_UART2_ROOT 418 +#define IMX8MN_CLK_UART3_ROOT 419 +#define IMX8MN_CLK_UART4_ROOT 420 +#define IMX8MN_CLK_USB1_CTRL_ROOT 421 +#define IMX8MN_CLK_GPU3D_ROOT 422 +#define IMX8MN_CLK_USDHC1_ROOT 423 +#define IMX8MN_CLK_USDHC2_ROOT 424 +#define IMX8MN_CLK_WDOG1_ROOT 425 +#define IMX8MN_CLK_WDOG2_ROOT 426 +#define IMX8MN_CLK_WDOG3_ROOT 427 +#define IMX8MN_CLK_VPU_G1_ROOT 428 +#define IMX8MN_CLK_GPU_ROOT 429 +#define IMX8MN_CLK_VPU_H1_ROOT 430 +#define IMX8MN_CLK_VPU_G2_ROOT 431 +#define IMX8MN_CLK_PDM_ROOT 432 +#define IMX8MN_CLK_DISP_ROOT 433 +#define IMX8MN_CLK_DISP_AXI_ROOT 434 +#define IMX8MN_CLK_DISP_APB_ROOT 435 +#define IMX8MN_CLK_DISP_RTRM_ROOT 436 +#define IMX8MN_CLK_USDHC3_ROOT 437 +#define IMX8MN_CLK_TMU_ROOT 438 +#define IMX8MN_CLK_VPU_DEC_ROOT 439 +#define IMX8MN_CLK_SDMA1_ROOT 440 +#define IMX8MN_CLK_SDMA2_ROOT 441 +#define IMX8MN_CLK_SDMA3_ROOT 442 +#define IMX8MN_CLK_GPT_3M 443 +#define IMX8MN_CLK_ARM 444 +#define IMX8MN_CLK_PDM_IPG 445 + +#define IMX8MN_CLK_END 446 +#endif diff --git a/include/dt-bindings/pinctrl/pins-imx8mn.h b/include/dt-bindings/pinctrl/pins-imx8mn.h new file mode 100644 index 0000000000..126d7f8acb --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imx8mn.h @@ -0,0 +1,646 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DTS_IMX8MN_PINFUNC_H +#define __DTS_IMX8MN_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX8MN_IOMUXC_BOOT_MODE2__CCMSRCGPCMIX_BOOT_MODE2 0x0020 0x025C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_BOOT_MODE2__I2C1_SCL 0x0020 0x025C 0x055C 0x1 0x3 +#define MX8MN_IOMUXC_BOOT_MODE3__CCMSRCGPCMIX_BOOT_MODE3 0x0024 0x0260 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_BOOT_MODE3__I2C1_SDA 0x0024 0x0260 0x056C 0x1 0x3 +#define MX8MN_IOMUXC_GPIO1_IO00__GPIO1_IO0 0x0028 0x0290 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x0028 0x0290 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x0028 0x0290 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 0x0028 0x0290 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01__GPIO1_IO1 0x002C 0x0294 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01__PWM1_OUT 0x002C 0x0294 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x002C 0x0294 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 0x002C 0x0294 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02__GPIO1_IO2 0x0030 0x0298 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x0030 0x0298 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x0030 0x0298 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03__GPIO1_IO3 0x0034 0x029C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x0034 0x029C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT0 0x0034 0x029C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK 0x0034 0x029C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04__GPIO1_IO4 0x0038 0x02A0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0038 0x02A0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT1 0x0038 0x02A0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV 0x0038 0x02A0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05__GPIO1_IO5 0x003C 0x02A4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05__M4_NMI 0x003C 0x02A4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY 0x003C 0x02A4 0x04BC 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT 0x003C 0x02A4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06__GPIO1_IO6 0x0040 0x02A8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06__ENET1_MDC 0x0040 0x02A8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x0040 0x02A8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 0x0040 0x02A8 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07__GPIO1_IO7 0x0044 0x02AC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07__ENET1_MDIO 0x0044 0x02AC 0x04C0 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07__USDHC1_WP 0x0044 0x02AC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 0x0044 0x02AC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08__GPIO1_IO8 0x0048 0x02B0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08__ENET1_1588_EVENT0_IN 0x0048 0x02B0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08__PWM1_OUT 0x0048 0x02B0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x0048 0x02B0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT 0x0048 0x02B0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09__GPIO1_IO9 0x004C 0x02B4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09__ENET1_1588_EVENT0_OUT 0x004C 0x02B4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09__PWM2_OUT 0x004C 0x02B4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x004C 0x02B4 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT0 0x004C 0x02B4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP 0x004C 0x02B4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x0050 0x02B8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0050 0x02B8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10__PWM3_OUT 0x0050 0x02B8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x0054 0x02BC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11__PWM2_OUT 0x0054 0x02BC 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x0054 0x02BC 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY 0x0054 0x02BC 0x04BC 0x5 0x1 +#define MX8MN_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0 0x0054 0x02BC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x0058 0x02C0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x0058 0x02C0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT1 0x0058 0x02C0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1 0x0058 0x02C0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x005C 0x02C4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x005C 0x02C4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13__PWM2_OUT 0x005C 0x02C4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2 0x005C 0x02C4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x0060 0x02C8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x0060 0x02C8 0x0598 0x4 0x2 +#define MX8MN_IOMUXC_GPIO1_IO14__PWM3_OUT 0x0060 0x02C8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 0x0060 0x02C8 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x0064 0x02CC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15__USDHC3_WP 0x0064 0x02CC 0x05B8 0x4 0x2 +#define MX8MN_IOMUXC_GPIO1_IO15__PWM4_OUT 0x0064 0x02CC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x0064 0x02CC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_ENET_MDC__ENET1_MDC 0x0068 0x02D0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_MDC__SAI6_TX_DATA0 0x0068 0x02D0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_MDC__PDM_BIT_STREAM3 0x0068 0x02D0 0x0540 0x3 0x1 +#define MX8MN_IOMUXC_ENET_MDC__SPDIF1_OUT 0x0068 0x02D0 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_ENET_MDC__GPIO1_IO16 0x0068 0x02D0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_MDC__USDHC3_STROBE 0x0068 0x02D0 0x059C 0x6 0x1 +#define MX8MN_IOMUXC_ENET_MDIO__ENET1_MDIO 0x006C 0x02D4 0x04C0 0x0 0x1 +#define MX8MN_IOMUXC_ENET_MDIO__SAI6_TX_SYNC 0x006C 0x02D4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_MDIO__PDM_BIT_STREAM2 0x006C 0x02D4 0x053C 0x3 0x1 +#define MX8MN_IOMUXC_ENET_MDIO__SPDIF1_IN 0x006C 0x02D4 0x05CC 0x4 0x1 +#define MX8MN_IOMUXC_ENET_MDIO__GPIO1_IO17 0x006C 0x02D4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x006C 0x02D4 0x0550 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD3__ENET1_RGMII_TD3 0x0070 0x02D8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD3__SAI6_TX_BCLK 0x0070 0x02D8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD3__PDM_BIT_STREAM1 0x0070 0x02D8 0x0538 0x3 0x1 +#define MX8MN_IOMUXC_ENET_TD3__SPDIF1_EXT_CLK 0x0070 0x02D8 0x0568 0x4 0x1 +#define MX8MN_IOMUXC_ENET_TD3__GPIO1_IO18 0x0070 0x02D8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD3__USDHC3_DATA6 0x0070 0x02D8 0x0584 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD2__ENET1_RGMII_TD2 0x0074 0x02DC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD2__ENET1_TX_CLK 0x0074 0x02DC 0x05A4 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TD2__CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0074 0x02DC 0x05A4 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TD2__SAI6_RX_DATA0 0x0074 0x02DC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD2__PDM_BIT_STREAM3 0x0074 0x02DC 0x0540 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD2__GPIO1_IO19 0x0074 0x02DC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD2__USDHC3_DATA7 0x0074 0x02DC 0x054C 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD1__ENET1_RGMII_TD1 0x0078 0x02E0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD1__SAI6_RX_SYNC 0x0078 0x02E0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD1__PDM_BIT_STREAM2 0x0078 0x02E0 0x053C 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD1__GPIO1_IO20 0x0078 0x02E0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD1__USDHC3_CD_B 0x0078 0x02E0 0x0598 0x6 0x3 +#define MX8MN_IOMUXC_ENET_TD0__ENET1_RGMII_TD0 0x007C 0x02E4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD0__SAI6_RX_BCLK 0x007C 0x02E4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD0__PDM_BIT_STREAM1 0x007C 0x02E4 0x0538 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD0__GPIO1_IO21 0x007C 0x02E4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD0__USDHC3_WP 0x007C 0x02E4 0x05B8 0x6 0x3 +#define MX8MN_IOMUXC_ENET_TX_CTL__ENET1_RGMII_TX_CTL 0x0080 0x02E8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL__SAI6_MCLK 0x0080 0x02E8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x0080 0x02E8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x0080 0x02E8 0x05B4 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TXC__ENET1_RGMII_TXC 0x0084 0x02EC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TXC__ENET1_TX_ER 0x0084 0x02EC 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TXC__SAI7_TX_DATA0 0x0084 0x02EC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TXC__GPIO1_IO23 0x0084 0x02EC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TXC__USDHC3_DATA1 0x0084 0x02EC 0x05B0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RX_CTL__ENET1_RGMII_RX_CTL 0x0088 0x02F0 0x0574 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL__SAI7_TX_SYNC 0x0088 0x02F0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL__PDM_BIT_STREAM3 0x0088 0x02F0 0x0540 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x0088 0x02F0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x0088 0x02F0 0x05E4 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RXC__ENET1_RGMII_RXC 0x008C 0x02F4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RXC__ENET1_RX_ER 0x008C 0x02F4 0x05C8 0x1 0x0 +#define MX8MN_IOMUXC_ENET_RXC__SAI7_TX_BCLK 0x008C 0x02F4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RXC__PDM_BIT_STREAM2 0x008C 0x02F4 0x053C 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RXC__GPIO1_IO25 0x008C 0x02F4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RXC__USDHC3_DATA3 0x008C 0x02F4 0x05E0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD0__ENET1_RGMII_RD0 0x0090 0x02F8 0x057C 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD0__SAI7_RX_DATA0 0x0090 0x02F8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD0__PDM_BIT_STREAM1 0x0090 0x02F8 0x0538 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RD0__GPIO1_IO26 0x0090 0x02F8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD0__USDHC3_DATA4 0x0090 0x02F8 0x0558 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD1__ENET1_RGMII_RD1 0x0094 0x02FC 0x0554 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD1__SAI7_RX_SYNC 0x0094 0x02FC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD1__PDM_BIT_STREAM0 0x0094 0x02FC 0x0534 0x3 0x1 +#define MX8MN_IOMUXC_ENET_RD1__GPIO1_IO27 0x0094 0x02FC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x0094 0x02FC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_ENET_RD2__ENET1_RGMII_RD2 0x0098 0x0300 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD2__SAI7_RX_BCLK 0x0098 0x0300 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD2__PDM_CLK 0x0098 0x0300 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_ENET_RD2__GPIO1_IO28 0x0098 0x0300 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD2__USDHC3_CLK 0x0098 0x0300 0x05A0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD3__ENET1_RGMII_RD3 0x009C 0x0304 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD3__SAI7_MCLK 0x009C 0x0304 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD3__SPDIF1_IN 0x009C 0x0304 0x05CC 0x3 0x5 +#define MX8MN_IOMUXC_ENET_RD3__GPIO1_IO29 0x009C 0x0304 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD3__USDHC3_CMD 0x009C 0x0304 0x05DC 0x6 0x1 +#define MX8MN_IOMUXC_SD1_CLK__USDHC1_CLK 0x00A0 0x0308 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_CLK__ENET1_MDC 0x00A0 0x0308 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_CLK__UART1_DCE_TX 0x00A0 0x0308 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_CLK__UART1_DTE_RX 0x00A0 0x0308 0x04F4 0x4 0x4 +#define MX8MN_IOMUXC_SD1_CLK__GPIO2_IO0 0x00A0 0x0308 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_CMD__USDHC1_CMD 0x00A4 0x030C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_CMD__ENET1_MDIO 0x00A4 0x030C 0x04C0 0x1 0x3 +#define MX8MN_IOMUXC_SD1_CMD__UART1_DCE_RX 0x00A4 0x030C 0x04F4 0x4 0x5 +#define MX8MN_IOMUXC_SD1_CMD__UART1_DTE_TX 0x00A4 0x030C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_CMD__GPIO2_IO1 0x00A4 0x030C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x00A8 0x0310 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x00A8 0x0310 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA0__UART1_DCE_RTS_B 0x00A8 0x0310 0x04F0 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA0__UART1_DTE_CTS_B 0x00A8 0x0310 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA0__GPIO2_IO2 0x00A8 0x0310 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x00AC 0x0314 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x00AC 0x0314 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA1__UART1_DCE_CTS_B 0x00AC 0x0314 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA1__UART1_DTE_RTS_B 0x00AC 0x0314 0x04F0 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA1__GPIO2_IO3 0x00AC 0x0314 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x00B0 0x0318 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x00B0 0x0318 0x057C 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x00B0 0x0318 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x00B0 0x0318 0x04FC 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA2__GPIO2_IO4 0x00B0 0x0318 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x00B4 0x031C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x00B4 0x031C 0x0554 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x00B4 0x031C 0x04FC 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x00B4 0x031C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA3__GPIO2_IO5 0x00B4 0x031C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x00B8 0x0320 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x00B8 0x0320 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA4__I2C1_SCL 0x00B8 0x0320 0x055C 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA4__UART2_DCE_RTS_B 0x00B8 0x0320 0x04F8 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA4__UART2_DTE_CTS_B 0x00B8 0x0320 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA4__GPIO2_IO6 0x00B8 0x0320 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x00BC 0x0324 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x00BC 0x0324 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA5__I2C1_SDA 0x00BC 0x0324 0x056C 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA5__UART2_DCE_CTS_B 0x00BC 0x0324 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA5__UART2_DTE_RTS_B 0x00BC 0x0324 0x04F8 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA5__GPIO2_IO7 0x00BC 0x0324 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x00C0 0x0328 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x00C0 0x0328 0x0574 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA6__I2C2_SCL 0x00C0 0x0328 0x05D0 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x00C0 0x0328 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x00C0 0x0328 0x0504 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA6__GPIO2_IO8 0x00C0 0x0328 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x00C4 0x032C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x00C4 0x032C 0x05C8 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA7__I2C2_SDA 0x00C4 0x032C 0x0560 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x00C4 0x032C 0x0504 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x00C4 0x032C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA7__GPIO2_IO9 0x00C4 0x032C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x00C8 0x0330 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x00C8 0x0330 0x05A4 0x1 0x1 +#define MX8MN_IOMUXC_SD1_RESET_B__CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x00C8 0x0330 0x05A4 0x1 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B__I2C3_SCL 0x00C8 0x0330 0x0588 0x3 0x1 +#define MX8MN_IOMUXC_SD1_RESET_B__UART3_DCE_RTS_B 0x00C8 0x0330 0x0500 0x4 0x2 +#define MX8MN_IOMUXC_SD1_RESET_B__UART3_DTE_CTS_B 0x00C8 0x0330 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x00C8 0x0330 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x00CC 0x0334 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_STROBE__I2C3_SDA 0x00CC 0x0334 0x05BC 0x3 0x1 +#define MX8MN_IOMUXC_SD1_STROBE__UART3_DCE_CTS_B 0x00CC 0x0334 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_STROBE__UART3_DTE_RTS_B 0x00CC 0x0334 0x0500 0x4 0x3 +#define MX8MN_IOMUXC_SD1_STROBE__GPIO2_IO11 0x00CC 0x0334 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x00D0 0x0338 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CD_B__GPIO2_IO12 0x00D0 0x0338 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x00D0 0x0338 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK 0x00D4 0x033C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CLK__SAI5_RX_SYNC 0x00D4 0x033C 0x04E4 0x1 0x1 +#define MX8MN_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x00D4 0x033C 0x0580 0x2 0x1 +#define MX8MN_IOMUXC_SD2_CLK__UART4_DCE_RX 0x00D4 0x033C 0x050C 0x3 0x4 +#define MX8MN_IOMUXC_SD2_CLK__UART4_DTE_TX 0x00D4 0x033C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_CLK__SAI5_MCLK 0x00D4 0x033C 0x0594 0x4 0x1 +#define MX8MN_IOMUXC_SD2_CLK__GPIO2_IO13 0x00D4 0x033C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x00D4 0x033C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD 0x00D8 0x0340 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CMD__SAI5_RX_BCLK 0x00D8 0x0340 0x04D0 0x1 0x1 +#define MX8MN_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x00D8 0x0340 0x0590 0x2 0x1 +#define MX8MN_IOMUXC_SD2_CMD__UART4_DCE_TX 0x00D8 0x0340 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_CMD__UART4_DTE_RX 0x00D8 0x0340 0x050C 0x3 0x5 +#define MX8MN_IOMUXC_SD2_CMD__PDM_CLK 0x00D8 0x0340 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD2_CMD__GPIO2_IO14 0x00D8 0x0340 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x00D8 0x0340 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x00DC 0x0344 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA0__SAI5_RX_DATA0 0x00DC 0x0344 0x04D4 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA0__I2C4_SDA 0x00DC 0x0344 0x058C 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x00DC 0x0344 0x04FC 0x3 0x6 +#define MX8MN_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x00DC 0x0344 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA0__PDM_BIT_STREAM0 0x00DC 0x0344 0x0534 0x4 0x2 +#define MX8MN_IOMUXC_SD2_DATA0__GPIO2_IO15 0x00DC 0x0344 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x00DC 0x0344 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x00E0 0x0348 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA1__SAI5_TX_SYNC 0x00E0 0x0348 0x04EC 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA1__I2C4_SCL 0x00E0 0x0348 0x05D4 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x00E0 0x0348 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x00E0 0x0348 0x04FC 0x3 0x7 +#define MX8MN_IOMUXC_SD2_DATA1__PDM_BIT_STREAM1 0x00E0 0x0348 0x0538 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA1__GPIO2_IO16 0x00E0 0x0348 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x00E0 0x0348 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x00E4 0x034C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA2__SAI5_TX_BCLK 0x00E4 0x034C 0x04E8 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x00E4 0x034C 0x0570 0x2 0x2 +#define MX8MN_IOMUXC_SD2_DATA2__SPDIF1_OUT 0x00E4 0x034C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA2__PDM_BIT_STREAM2 0x00E4 0x034C 0x053C 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA2__GPIO2_IO17 0x00E4 0x034C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP 0x00E4 0x034C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x00E8 0x0350 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA3__SAI5_TX_DATA0 0x00E8 0x0350 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x00E8 0x0350 0x0578 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA3__SPDIF1_IN 0x00E8 0x0350 0x05CC 0x3 0x2 +#define MX8MN_IOMUXC_SD2_DATA3__PDM_BIT_STREAM3 0x00E8 0x0350 0x0540 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA3__GPIO2_IO18 0x00E8 0x0350 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x00E8 0x0350 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x00EC 0x0354 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x00EC 0x0354 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x00EC 0x0354 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_WP__USDHC2_WP 0x00F0 0x0358 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_WP__GPIO2_IO20 0x00F0 0x0358 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x00F0 0x0358 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_ALE__RAWNAND_ALE 0x00F4 0x035C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_ALE__QSPI_A_SCLK 0x00F4 0x035C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_ALE__PDM_BIT_STREAM0 0x00F4 0x035C 0x0534 0x3 0x3 +#define MX8MN_IOMUXC_NAND_ALE__UART3_DCE_RX 0x00F4 0x035C 0x0504 0x4 0x6 +#define MX8MN_IOMUXC_NAND_ALE__UART3_DTE_TX 0x00F4 0x035C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_ALE__GPIO3_IO0 0x00F4 0x035C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x00F4 0x035C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B 0x00F8 0x0360 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B__QSPI_A_SS0_B 0x00F8 0x0360 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B__PDM_BIT_STREAM1 0x00F8 0x0360 0x0538 0x3 0x5 +#define MX8MN_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x00F8 0x0360 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x00F8 0x0360 0x0504 0x4 0x7 +#define MX8MN_IOMUXC_NAND_CE0_B__GPIO3_IO1 0x00F8 0x0360 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x00F8 0x0360 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B 0x00FC 0x0364 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B__QSPI_A_SS1_B 0x00FC 0x0364 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x00FC 0x0364 0x059C 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B__PDM_BIT_STREAM0 0x00FC 0x0364 0x0534 0x3 0x4 +#define MX8MN_IOMUXC_NAND_CE1_B__I2C4_SCL 0x00FC 0x0364 0x05D4 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE1_B__GPIO3_IO2 0x00FC 0x0364 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE0 0x00FC 0x0364 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B 0x0100 0x0368 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B__QSPI_B_SS0_B 0x0100 0x0368 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0100 0x0368 0x0550 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B__PDM_BIT_STREAM1 0x0100 0x0368 0x0538 0x3 0x6 +#define MX8MN_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0100 0x0368 0x058C 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE2_B__GPIO3_IO3 0x0100 0x0368 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE1 0x0100 0x0368 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B 0x0104 0x036C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B__QSPI_B_SS1_B 0x0104 0x036C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0104 0x036C 0x0584 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B__PDM_BIT_STREAM2 0x0104 0x036C 0x053C 0x3 0x5 +#define MX8MN_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0104 0x036C 0x05BC 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE3_B__GPIO3_IO4 0x0104 0x036C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE2 0x0104 0x036C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CLE__RAWNAND_CLE 0x0108 0x0370 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CLE__QSPI_B_SCLK 0x0108 0x0370 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0108 0x0370 0x054C 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CLE__GPIO3_IO5 0x0108 0x0370 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CLE__CORESIGHT_TRACE3 0x0108 0x0370 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA00__RAWNAND_DATA00 0x010C 0x0374 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA00__QSPI_A_DATA0 0x010C 0x0374 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA00__PDM_BIT_STREAM2 0x010C 0x0374 0x053C 0x3 0x6 +#define MX8MN_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x010C 0x0374 0x050C 0x4 0x6 +#define MX8MN_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x010C 0x0374 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_DATA00__GPIO3_IO6 0x010C 0x0374 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA00__CORESIGHT_TRACE4 0x010C 0x0374 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA01__RAWNAND_DATA01 0x0110 0x0378 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA01__QSPI_A_DATA1 0x0110 0x0378 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA01__PDM_BIT_STREAM3 0x0110 0x0378 0x0540 0x3 0x5 +#define MX8MN_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0110 0x0378 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0110 0x0378 0x050C 0x4 0x7 +#define MX8MN_IOMUXC_NAND_DATA01__GPIO3_IO7 0x0110 0x0378 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA01__CORESIGHT_TRACE5 0x0110 0x0378 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA02__RAWNAND_DATA02 0x0114 0x037C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA02__QSPI_A_DATA2 0x0114 0x037C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x0114 0x037C 0x0598 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA02__I2C4_SDA 0x0114 0x037C 0x058C 0x4 0x3 +#define MX8MN_IOMUXC_NAND_DATA02__GPIO3_IO8 0x0114 0x037C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA02__CORESIGHT_TRACE6 0x0114 0x037C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA03__RAWNAND_DATA03 0x0118 0x0380 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA03__QSPI_A_DATA3 0x0118 0x0380 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA03__USDHC3_WP 0x0118 0x0380 0x05B8 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA03__GPIO3_IO9 0x0118 0x0380 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA03__CORESIGHT_TRACE7 0x0118 0x0380 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA04__RAWNAND_DATA04 0x011C 0x0384 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA04__QSPI_B_DATA0 0x011C 0x0384 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x011C 0x0384 0x05B4 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA04__GPIO3_IO10 0x011C 0x0384 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA04__CORESIGHT_TRACE8 0x011C 0x0384 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA05__RAWNAND_DATA05 0x0120 0x0388 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA05__QSPI_B_DATA1 0x0120 0x0388 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x0120 0x0388 0x05B0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA05__GPIO3_IO11 0x0120 0x0388 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA05__CORESIGHT_TRACE9 0x0120 0x0388 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA06__RAWNAND_DATA06 0x0124 0x038C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA06__QSPI_B_DATA2 0x0124 0x038C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x0124 0x038C 0x05E4 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA06__GPIO3_IO12 0x0124 0x038C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x0124 0x038C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA07__RAWNAND_DATA07 0x0128 0x0390 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA07__QSPI_B_DATA3 0x0128 0x0390 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x0128 0x0390 0x05E0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA07__GPIO3_IO13 0x0128 0x0390 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x0128 0x0390 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DQS__RAWNAND_DQS 0x012C 0x0394 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DQS__QSPI_A_DQS 0x012C 0x0394 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DQS__PDM_CLK 0x012C 0x0394 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_NAND_DQS__I2C3_SCL 0x012C 0x0394 0x0588 0x4 0x2 +#define MX8MN_IOMUXC_NAND_DQS__GPIO3_IO14 0x012C 0x0394 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x012C 0x0394 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_RE_B__RAWNAND_RE_B 0x0130 0x0398 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_RE_B__QSPI_B_DQS 0x0130 0x0398 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x0130 0x0398 0x0558 0x2 0x0 +#define MX8MN_IOMUXC_NAND_RE_B__PDM_BIT_STREAM1 0x0130 0x0398 0x0538 0x3 0x7 +#define MX8MN_IOMUXC_NAND_RE_B__GPIO3_IO15 0x0130 0x0398 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x0130 0x0398 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_READY_B__RAWNAND_READY_B 0x0134 0x039C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x0134 0x039C 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_NAND_READY_B__PDM_BIT_STREAM3 0x0134 0x039C 0x0540 0x3 0x6 +#define MX8MN_IOMUXC_NAND_READY_B__I2C3_SCL 0x0134 0x039C 0x0588 0x4 0x3 +#define MX8MN_IOMUXC_NAND_READY_B__GPIO3_IO16 0x0134 0x039C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x0134 0x039C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_WE_B__RAWNAND_WE_B 0x0138 0x03A0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK 0x0138 0x03A0 0x05A0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_WE_B__I2C3_SDA 0x0138 0x03A0 0x05BC 0x4 0x3 +#define MX8MN_IOMUXC_NAND_WE_B__GPIO3_IO17 0x0138 0x03A0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x0138 0x03A0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_WP_B__RAWNAND_WP_B 0x013C 0x03A4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD 0x013C 0x03A4 0x05DC 0x2 0x0 +#define MX8MN_IOMUXC_NAND_WP_B__I2C4_SDA 0x013C 0x03A4 0x058C 0x4 0x4 +#define MX8MN_IOMUXC_NAND_WP_B__GPIO3_IO18 0x013C 0x03A4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x013C 0x03A4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SAI5_RXFS__SAI5_RX_SYNC 0x0140 0x03A8 0x04E4 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x0140 0x03A8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXC__SAI5_RX_BCLK 0x0144 0x03AC 0x04D0 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXC__PDM_CLK 0x0144 0x03AC 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXC__GPIO3_IO20 0x0144 0x03AC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0__SAI5_RX_DATA0 0x0148 0x03B0 0x04D4 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0__PDM_BIT_STREAM0 0x0148 0x03B0 0x0534 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0148 0x03B0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1__SAI5_RX_DATA1 0x014C 0x03B4 0x04D8 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1__SAI5_TX_SYNC 0x014C 0x03B4 0x04EC 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1__PDM_BIT_STREAM1 0x014C 0x03B4 0x0538 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x014C 0x03B4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2__SAI5_RX_DATA2 0x0150 0x03B8 0x04DC 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2__SAI5_TX_BCLK 0x0150 0x03B8 0x04E8 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2__PDM_BIT_STREAM2 0x0150 0x03B8 0x053C 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x0150 0x03B8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3__SAI5_RX_DATA3 0x0154 0x03BC 0x04E0 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3__SAI5_TX_DATA0 0x0154 0x03BC 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3__PDM_BIT_STREAM3 0x0154 0x03BC 0x0540 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x0154 0x03BC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_MCLK__SAI5_MCLK 0x0158 0x03C0 0x0594 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x0158 0x03C0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS__SAI2_RX_SYNC 0x01B0 0x0418 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS__SAI5_TX_SYNC 0x01B0 0x0418 0x04EC 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_RXFS__SAI5_TX_DATA1 0x01B0 0x0418 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS__SAI2_RX_DATA1 0x01B0 0x0418 0x05AC 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x01B0 0x0418 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x01B0 0x0418 0x04F4 0x4 0x2 +#define MX8MN_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x01B0 0x0418 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS__PDM_BIT_STREAM2 0x01B0 0x0418 0x053C 0x6 0x7 +#define MX8MN_IOMUXC_SAI2_RXC__SAI2_RX_BCLK 0x01B4 0x041C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXC__SAI5_TX_BCLK 0x01B4 0x041C 0x04E8 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x01B4 0x041C 0x04F4 0x4 0x3 +#define MX8MN_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x01B4 0x041C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXC__GPIO4_IO22 0x01B4 0x041C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXC__PDM_BIT_STREAM1 0x01B4 0x041C 0x0538 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_RXD0__SAI2_RX_DATA0 0x01B8 0x0420 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0__SAI5_TX_DATA0 0x01B8 0x0420 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0__SAI2_TX_DATA1 0x01B8 0x0420 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0__UART1_DCE_RTS_B 0x01B8 0x0420 0x04F0 0x4 0x2 +#define MX8MN_IOMUXC_SAI2_RXD0__UART1_DTE_CTS_B 0x01B8 0x0420 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x01B8 0x0420 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0__PDM_BIT_STREAM3 0x01B8 0x0420 0x0540 0x6 0x7 +#define MX8MN_IOMUXC_SAI2_TXFS__SAI2_TX_SYNC 0x01BC 0x0424 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS__SAI5_TX_DATA1 0x01BC 0x0424 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS__SAI2_TX_DATA1 0x01BC 0x0424 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS__UART1_DCE_CTS_B 0x01BC 0x0424 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS__UART1_DTE_RTS_B 0x01BC 0x0424 0x04F0 0x4 0x3 +#define MX8MN_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x01BC 0x0424 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS__PDM_BIT_STREAM2 0x01BC 0x0424 0x053C 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_TXC__SAI2_TX_BCLK 0x01C0 0x0428 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXC__SAI5_TX_DATA2 0x01C0 0x0428 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXC__GPIO4_IO25 0x01C0 0x0428 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXC__PDM_BIT_STREAM1 0x01C0 0x0428 0x0538 0x6 0x9 +#define MX8MN_IOMUXC_SAI2_TXD0__SAI2_TX_DATA0 0x01C4 0x042C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0__SAI5_TX_DATA3 0x01C4 0x042C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x01C4 0x042C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE4 0x01C4 0x042C 0x0540 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_MCLK__SAI2_MCLK 0x01C8 0x0430 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_MCLK__SAI5_MCLK 0x01C8 0x0430 0x0594 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x01C8 0x0430 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_MCLK__SAI3_MCLK 0x01C8 0x0430 0x05C0 0x6 0x1 +#define MX8MN_IOMUXC_SAI3_RXFS__SAI3_RX_SYNC 0x01CC 0x0434 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS__GPT1_CAPTURE1 0x01CC 0x0434 0x05F0 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS__SAI5_RX_SYNC 0x01CC 0x0434 0x04E4 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXFS__SAI3_RX_DATA1 0x01CC 0x0434 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS__SPDIF1_IN 0x01CC 0x0434 0x05CC 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x01CC 0x0434 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS__PDM_BIT_STREAM0 0x01CC 0x0434 0x0534 0x6 0x5 +#define MX8MN_IOMUXC_SAI3_RXC__SAI3_RX_BCLK 0x01D0 0x0438 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXC__GPT1_CLK 0x01D0 0x0438 0x05E8 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXC__SAI5_RX_BCLK 0x01D0 0x0438 0x04D0 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXC__SAI2_RX_DATA1 0x01D0 0x0438 0x05AC 0x3 0x2 +#define MX8MN_IOMUXC_SAI3_RXC__UART2_DCE_CTS_B 0x01D0 0x0438 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_RXC__UART2_DTE_RTS_B 0x01D0 0x0438 0x04F8 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_RXC__GPIO4_IO29 0x01D0 0x0438 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXC__PDM_CLK 0x01D0 0x0438 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SAI3_RXD__SAI3_RX_DATA0 0x01D4 0x043C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXD__GPT1_COMPARE1 0x01D4 0x043C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXD__SAI5_RX_DATA0 0x01D4 0x043C 0x04D4 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXD__SAI3_TX_DATA1 0x01D4 0x043C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_RXD__UART2_DCE_RTS_B 0x01D4 0x043C 0x04F8 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_RXD__UART2_DTE_CTS_B 0x01D4 0x043C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_RXD__GPIO4_IO30 0x01D4 0x043C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXD__PDM_BIT_STREAM1 0x01D4 0x043C 0x0538 0x6 0x10 +#define MX8MN_IOMUXC_SAI3_TXFS__SAI3_TX_SYNC 0x01D8 0x0440 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS__GPT1_CAPTURE2 0x01D8 0x0440 0x05EC 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS__SAI5_RX_DATA1 0x01D8 0x0440 0x04D8 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXFS__SAI3_TX_DATA1 0x01D8 0x0440 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x01D8 0x0440 0x04FC 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x01D8 0x0440 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x01D8 0x0440 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS__PDM_BIT_STREAM3 0x01D8 0x0440 0x0540 0x6 0x9 +#define MX8MN_IOMUXC_SAI3_TXC__SAI3_TX_BCLK 0x01DC 0x0444 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXC__GPT1_COMPARE2 0x01DC 0x0444 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXC__SAI5_RX_DATA2 0x01DC 0x0444 0x04DC 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXC__SAI2_TX_DATA1 0x01DC 0x0444 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x01DC 0x0444 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x01DC 0x0444 0x04FC 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_TXC__GPIO5_IO0 0x01DC 0x0444 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXC__PDM_BIT_STREAM2 0x01DC 0x0444 0x053C 0x6 0x9 +#define MX8MN_IOMUXC_SAI3_TXD__SAI3_TX_DATA0 0x01E0 0x0448 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXD__GPT1_COMPARE3 0x01E0 0x0448 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXD__SAI5_RX_DATA3 0x01E0 0x0448 0x04E0 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXD__SPDIF1_EXT_CLK 0x01E0 0x0448 0x0568 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_TXD__GPIO5_IO1 0x01E0 0x0448 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE5 0x01E0 0x0448 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK__SAI3_MCLK 0x01E4 0x044C 0x05C0 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK__PWM4_OUT 0x01E4 0x044C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK__SAI5_MCLK 0x01E4 0x044C 0x0594 0x2 0x3 +#define MX8MN_IOMUXC_SAI3_MCLK__SPDIF1_OUT 0x01E4 0x044C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK__GPIO5_IO2 0x01E4 0x044C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK__SPDIF1_IN 0x01E4 0x044C 0x05CC 0x6 0x4 +#define MX8MN_IOMUXC_SPDIF_TX__SPDIF1_OUT 0x01E8 0x0450 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_TX__PWM3_OUT 0x01E8 0x0450 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_TX__GPIO5_IO3 0x01E8 0x0450 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SPDIF_RX__SPDIF1_IN 0x01EC 0x0454 0x05CC 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_RX__PWM2_OUT 0x01EC 0x0454 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_RX__GPIO5_IO4 0x01EC 0x0454 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK__SPDIF1_EXT_CLK 0x01F0 0x0458 0x0568 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x01F0 0x0458 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO5 0x01F0 0x0458 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x01F4 0x045C 0x05D8 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x01F4 0x045C 0x0504 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x01F4 0x045C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x01F4 0x045C 0x055C 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_SCLK__SAI5_RX_SYNC 0x01F4 0x045C 0x04DC 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI1_SCLK__GPIO5_IO6 0x01F4 0x045C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x01F8 0x0460 0x05A8 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x01F8 0x0460 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x01F8 0x0460 0x0504 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x01F8 0x0460 0x056C 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_MOSI__SAI5_RX_BCLK 0x01F8 0x0460 0x04D0 0x3 0x3 +#define MX8MN_IOMUXC_ECSPI1_MOSI__GPIO5_IO7 0x01F8 0x0460 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x01FC 0x0464 0x05C4 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS_B 0x01FC 0x0464 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS_B 0x01FC 0x0464 0x0500 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x01FC 0x0464 0x05D0 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_MISO__SAI5_RX_DATA0 0x01FC 0x0464 0x04D4 0x3 0x3 +#define MX8MN_IOMUXC_ECSPI1_MISO__GPIO5_IO8 0x01FC 0x0464 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x0200 0x0468 0x0564 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS_B 0x0200 0x0468 0x0500 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS_B 0x0200 0x0468 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x0200 0x0468 0x0560 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_SS0__SAI5_RX_DATA1 0x0200 0x0468 0x04D8 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI1_SS0__SAI5_TX_SYNC 0x0200 0x0468 0x04EC 0x4 0x3 +#define MX8MN_IOMUXC_ECSPI1_SS0__GPIO5_IO9 0x0200 0x0468 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x0204 0x046C 0x0580 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x0204 0x046C 0x050C 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x0204 0x046C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x0204 0x046C 0x0588 0x2 0x4 +#define MX8MN_IOMUXC_ECSPI2_SCLK__SAI5_RX_DATA2 0x0204 0x046C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK__SAI5_TX_BCLK 0x0204 0x046C 0x04E8 0x4 0x3 +#define MX8MN_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x0204 0x046C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x0208 0x0470 0x0590 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x0208 0x0470 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x0208 0x0470 0x050C 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x0208 0x0470 0x05BC 0x2 0x4 +#define MX8MN_IOMUXC_ECSPI2_MOSI__SAI5_RX_DATA3 0x0208 0x0470 0x04E0 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI2_MOSI__SAI5_TX_DATA0 0x0208 0x0470 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x0208 0x0470 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x020C 0x0474 0x0578 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS_B 0x020C 0x0474 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS_B 0x020C 0x0474 0x0508 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x020C 0x0474 0x05D4 0x2 0x3 +#define MX8MN_IOMUXC_ECSPI2_MISO__SAI5_MCLK 0x020C 0x0474 0x0594 0x3 0x4 +#define MX8MN_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x020C 0x0474 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x0210 0x0478 0x0570 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS_B 0x0210 0x0478 0x0508 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS_B 0x0210 0x0478 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x0210 0x0478 0x058C 0x2 0x5 +#define MX8MN_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x0210 0x0478 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C1_SCL__I2C1_SCL 0x0214 0x047C 0x055C 0x0 0x0 +#define MX8MN_IOMUXC_I2C1_SCL__ENET1_MDC 0x0214 0x047C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x0214 0x047C 0x05D8 0x3 0x1 +#define MX8MN_IOMUXC_I2C1_SCL__GPIO5_IO14 0x0214 0x047C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C1_SDA__I2C1_SDA 0x0218 0x0480 0x056C 0x0 0x0 +#define MX8MN_IOMUXC_I2C1_SDA__ENET1_MDIO 0x0218 0x0480 0x04C0 0x1 0x2 +#define MX8MN_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x0218 0x0480 0x05A8 0x3 0x1 +#define MX8MN_IOMUXC_I2C1_SDA__GPIO5_IO15 0x0218 0x0480 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C2_SCL__I2C2_SCL 0x021C 0x0484 0x05D0 0x0 0x0 +#define MX8MN_IOMUXC_I2C2_SCL__ENET1_1588_EVENT1_IN 0x021C 0x0484 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x021C 0x0484 0x0598 0x2 0x1 +#define MX8MN_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x021C 0x0484 0x05C4 0x3 0x1 +#define MX8MN_IOMUXC_I2C2_SCL__GPIO5_IO16 0x021C 0x0484 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C2_SDA__I2C2_SDA 0x0220 0x0488 0x0560 0x0 0x0 +#define MX8MN_IOMUXC_I2C2_SDA__ENET1_1588_EVENT1_OUT 0x0220 0x0488 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C2_SDA__USDHC3_WP 0x0220 0x0488 0x05B8 0x2 0x1 +#define MX8MN_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x0220 0x0488 0x0564 0x3 0x1 +#define MX8MN_IOMUXC_I2C2_SDA__GPIO5_IO17 0x0220 0x0488 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C3_SCL__I2C3_SCL 0x0224 0x048C 0x0588 0x0 0x0 +#define MX8MN_IOMUXC_I2C3_SCL__PWM4_OUT 0x0224 0x048C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C3_SCL__GPT2_CLK 0x0224 0x048C 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x0224 0x048C 0x0580 0x3 0x2 +#define MX8MN_IOMUXC_I2C3_SCL__GPIO5_IO18 0x0224 0x048C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C3_SDA__I2C3_SDA 0x0228 0x0490 0x05BC 0x0 0x0 +#define MX8MN_IOMUXC_I2C3_SDA__PWM3_OUT 0x0228 0x0490 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C3_SDA__GPT3_CLK 0x0228 0x0490 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x0228 0x0490 0x0590 0x3 0x2 +#define MX8MN_IOMUXC_I2C3_SDA__GPIO5_IO19 0x0228 0x0490 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C4_SCL__I2C4_SCL 0x022C 0x0494 0x05D4 0x0 0x0 +#define MX8MN_IOMUXC_I2C4_SCL__PWM2_OUT 0x022C 0x0494 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x022C 0x0494 0x0578 0x3 0x2 +#define MX8MN_IOMUXC_I2C4_SCL__GPIO5_IO20 0x022C 0x0494 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C4_SDA__I2C4_SDA 0x0230 0x0498 0x058C 0x0 0x0 +#define MX8MN_IOMUXC_I2C4_SDA__PWM1_OUT 0x0230 0x0498 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x0230 0x0498 0x0570 0x3 0x1 +#define MX8MN_IOMUXC_I2C4_SDA__GPIO5_IO21 0x0230 0x0498 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART1_RXD__UART1_DCE_RX 0x0234 0x049C 0x04F4 0x0 0x0 +#define MX8MN_IOMUXC_UART1_RXD__UART1_DTE_TX 0x0234 0x049C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x0234 0x049C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART1_RXD__GPIO5_IO22 0x0234 0x049C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART1_TXD__UART1_DCE_TX 0x0238 0x04A0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART1_TXD__UART1_DTE_RX 0x0238 0x04A0 0x04F4 0x0 0x1 +#define MX8MN_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x0238 0x04A0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART1_TXD__GPIO5_IO23 0x0238 0x04A0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART2_RXD__UART2_DCE_RX 0x023C 0x04A4 0x04FC 0x0 0x0 +#define MX8MN_IOMUXC_UART2_RXD__UART2_DTE_TX 0x023C 0x04A4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART2_RXD__ECSPI3_MISO 0x023C 0x04A4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x023C 0x04A4 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_UART2_RXD__GPIO5_IO24 0x023C 0x04A4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART2_TXD__UART2_DCE_TX 0x0240 0x04A8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART2_TXD__UART2_DTE_RX 0x0240 0x04A8 0x04FC 0x0 0x1 +#define MX8MN_IOMUXC_UART2_TXD__ECSPI3_SS0 0x0240 0x04A8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x0240 0x04A8 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_UART2_TXD__GPIO5_IO25 0x0240 0x04A8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART3_RXD__UART3_DCE_RX 0x0244 0x04AC 0x0504 0x0 0x2 +#define MX8MN_IOMUXC_UART3_RXD__UART3_DTE_TX 0x0244 0x04AC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART3_RXD__UART1_DCE_CTS_B 0x0244 0x04AC 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART3_RXD__UART1_DTE_RTS_B 0x0244 0x04AC 0x04F0 0x1 0x0 +#define MX8MN_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x0244 0x04AC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x0244 0x04AC 0x05EC 0x3 0x1 +#define MX8MN_IOMUXC_UART3_RXD__GPIO5_IO26 0x0244 0x04AC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART3_TXD__UART3_DCE_TX 0x0248 0x04B0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART3_TXD__UART3_DTE_RX 0x0248 0x04B0 0x0504 0x0 0x3 +#define MX8MN_IOMUXC_UART3_TXD__UART1_DCE_RTS_B 0x0248 0x04B0 0x04F0 0x1 0x1 +#define MX8MN_IOMUXC_UART3_TXD__UART1_DTE_CTS_B 0x0248 0x04B0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x0248 0x04B0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_UART3_TXD__GPT1_CLK 0x0248 0x04B0 0x05E8 0x3 0x1 +#define MX8MN_IOMUXC_UART3_TXD__GPIO5_IO27 0x0248 0x04B0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART4_RXD__UART4_DCE_RX 0x024C 0x04B4 0x050C 0x0 0x2 +#define MX8MN_IOMUXC_UART4_RXD__UART4_DTE_TX 0x024C 0x04B4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART4_RXD__UART2_DCE_CTS_B 0x024C 0x04B4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART4_RXD__UART2_DTE_RTS_B 0x024C 0x04B4 0x04F8 0x1 0x0 +#define MX8MN_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x024C 0x04B4 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_UART4_RXD__GPIO5_IO28 0x024C 0x04B4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART4_TXD__UART4_DCE_TX 0x0250 0x04B8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART4_TXD__UART4_DTE_RX 0x0250 0x04B8 0x050C 0x0 0x3 +#define MX8MN_IOMUXC_UART4_TXD__UART2_DCE_RTS_B 0x0250 0x04B8 0x04F8 0x1 0x1 +#define MX8MN_IOMUXC_UART4_TXD__UART2_DTE_CTS_B 0x0250 0x04B8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x0250 0x04B8 0x05F0 0x3 0x1 +#define MX8MN_IOMUXC_UART4_TXD__GPIO5_IO29 0x0250 0x04B8 0x0000 0x5 0x0 + +#endif /* __DTS_IMX8MN_PINFUNC_H */ |