Merge branch 'master' of git://git.denx.de/u-boot-x86

10 files changed, 78 insertions, 29 deletions

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index e522ff3b7f..269043dedc 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -24,6 +24,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <syscon.h>
 #include <asm/control_regs.h>
 #include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
@@ -751,6 +752,10 @@ int cpu_init_r(void)
 	uclass_first_device(UCLASS_PCH, &dev);
 	uclass_first_device(UCLASS_LPC, &dev);
 
+	/* Set up pin control if available */
+	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+	debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
+
 	return 0;
 }
 
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4a50d8665e..c8907ce44b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,6 +65,26 @@
 		};
 	};
 
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
+
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
+	};
+
 	pci {
 		compatible = "pci-x86";
 		#address-cells = <3>;
@@ -213,7 +233,7 @@
 		fsp,mrc-init-mmio-size = <0x800>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
-		fsp,emmc-boot-mode = <2>;
+		fsp,emmc-boot-mode = <1>;
 		fsp,enable-sdio;
 		fsp,enable-sdcard;
 		fsp,enable-hsuart1;
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 1a4ecaad0e..fba089d666 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -30,6 +30,22 @@
 
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
+
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
 	};
 
 	chosen {
@@ -217,7 +233,7 @@
 		fsp,mrc-init-mmio-size = <0x800>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
-		fsp,emmc-boot-mode = <2>;
+		fsp,emmc-boot-mode = <1>;
 		fsp,enable-sdio;
 		fsp,enable-sdcard;
 		fsp,enable-hsuart1;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 936455b5e5..1a8a8cc7f1 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -29,6 +29,7 @@
 
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
 
 		/* GPIO E0 */
 		soc_gpio_s5_0@0 {
@@ -72,6 +73,21 @@
 			output-value = <1>;
 			direction = <PIN_OUTPUT>;
 		};
+
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
 	};
 
 	chosen {
@@ -246,7 +262,7 @@
 		fsp,mrc-init-mmio-size = <0x800>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
-		fsp,emmc-boot-mode = <2>;
+		fsp,emmc-boot-mode = <1>;
 		fsp,enable-sdio;
 		fsp,enable-sdcard;
 		fsp,enable-hsuart1;
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index ffb4678e51..bb71286dba 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -183,20 +183,20 @@ static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
 int acpi_create_madt_lapics(u32 current)
 {
 	struct udevice *dev;
-	int length = 0;
+	int total_length = 0;
 
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
 		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
-		length += acpi_create_madt_lapic(
-			(struct acpi_madt_lapic *)current,
-			plat->cpu_id, plat->cpu_id);
+		int length = acpi_create_madt_lapic(
+				(struct acpi_madt_lapic *)current,
+				plat->cpu_id, plat->cpu_id);
 		current += length;
+		total_length += length;
 	}
 
-	return length;
+	return total_length;
 }
 
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 2fa11fd442..b18d80dea6 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -24,6 +24,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 45bb3ec0e9..a03cff8e3f 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -28,6 +28,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index 22d3becb25..8c3a84caf8 100644
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -9,7 +9,7 @@ The PINCTRL master node requires the following properties:
 Pin nodes must be children of the pinctrl master node and can
 contain the following properties:
 - pad-offset	- (required) offset in the IOBASE for the pin to configure
-- gpio-offset	- (required) 2 cells
+- gpio-offset	- (required only when 'mode-gpio' is set) 2 cells
 			- offset in the GPIOBASE for the pin to configure
 			- the bit shift in this register (4 = bit 4)
 - mode-gpio	- (optional) standalone property to force the pin into GPIO mode
@@ -18,16 +18,16 @@ contain the following properties:
 in case of 'mode-gpio' property set:
 - output-value	- (optional) this set the default output value of the GPIO
 - direction	- (optional) this set the direction of the gpio
-- pull-str	- (optional) this set the pull strength of the pin
+- pull-strength	- (optional) this set the pull strength of the pin
 - pull-assign	- (optional) this set the pull assignement (up/down) of the pin
-- invert            - (optional) this input pin is inverted
+- invert	- (optional) this input pin is inverted
 
 Example:
 
 pin_usb_host_en0@0 {
-    gpio-offset = <0x80 8>;
-    pad-offset = <0x260>;
-    mode-gpio;
-    output-value = <1>;
-    direction = <PIN_OUTPUT>;
+	gpio-offset = <0x80 8>;
+	pad-offset = <0x260>;
+	mode-gpio;
+	output-value = <1>;
+	direction = <PIN_OUTPUT>;
 };
diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
index 81ce446e1a..8b50900f9f 100644
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -9,7 +9,6 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
-#include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -119,12 +118,6 @@ static int broadwell_gpio_probe(struct udevice *dev)
 	struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct broadwell_bank_priv *priv = dev_get_priv(dev);
-	struct udevice *pinctrl;
-	int ret;
-
-	/* Set up pin control if available */
-	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
-	debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b7e379ab97..fd6181fa5a 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,7 +32,6 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
-#include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -113,10 +112,6 @@ static int ich6_gpio_probe(struct udevice *dev)
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct ich6_bank_priv *bank = dev_get_priv(dev);
-	struct udevice *pinctrl;
-
-	/* Set up pin control if available */
-	syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
 
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;