diff options
| author | Tom Rini <trini@konsulko.com> | 2019-02-02 10:11:20 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-02-02 10:11:20 -0500 |
| commit | e5fd39c886485e3dec77f4438a6e364c2987cf5f (patch) | |
| tree | 635a4987f759207efd147ff628d683f7389ab1a1 | |
| parent | 544d5e98f3657e4ac1966be8971586aa42dad8c4 (diff) | |
| parent | 73ced87e9af70cba35c4374055dca56e5f9c460d (diff) | |
Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip
u-boot-rockchip changes for 2019.04-rc1:
* support for Chromebook Bob
* full pinctrl driver using DTS properties
* documentation improvements
* I2S support for some Rockchip SoCs
109 files changed, 7516 insertions, 6775 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d4eae02d89..876c032d11 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ + rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ rk3399-ficus.dtb \ diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index be026b0e07..4a8be5dabb 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -206,7 +206,7 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; + pinctrl-0 = <&uart21_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -748,7 +748,7 @@ uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; }; @@ -760,6 +760,13 @@ rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; }; }; + + uart2-1 { + uart21_xfer: uart21-xfer { + rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, + <1 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; }; dmc: dmc@11200000 { diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index 42f52d4d99..c251d9d594 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -52,6 +52,18 @@ vin-supply = <&vcc33_sys>; startup-delay-us = <15000>; }; + + sound { + compatible = "rockchip,audio-max98090-jerry"; + + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&max98090 0>; + }; + }; }; &dmc { diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi new file mode 100644 index 0000000000..22ba3490f2 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2015 Google, Inc + */ + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts new file mode 100644 index 0000000000..58c1fe96ee --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy.dts @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Speedy Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" +#include "rk3288-veyron-speedy-u-boot.dtsi" + +/ { + model = "Google Speedy"; + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", + "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + startup-delay-us = <100000>; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&backlight { + power-supply = <&backlight_regulator>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + +&panel { + power-supply = <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 92b68878fd..49ba3f3f14 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -484,6 +484,7 @@ max98090: max98090@10 { compatible = "maxim,max98090"; reg = <0x10>; + #sound-dai-cells = <0>; interrupt-parent = <&gpio6>; interrupts = <7 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 273d38c84f..487d22c9b0 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -649,6 +649,7 @@ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + #sound-dai-cells = <1>; dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; dma-names = "tx", "rx"; clock-names = "i2s_hclk", "i2s_clk"; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index be350866a7..f90e7e88db 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -15,7 +15,7 @@ chosen { stdout-path = &uart2; - u-boot,spl-boot-order = &sdhci, &sdmmc; + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; backlight: backlight { diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts new file mode 100644 index 0000000000..0e3d91fc28 --- /dev/null +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Bob Rev 4+ board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; +#include "rk3399-gru-chromebook.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" + +/ { + model = "Google Bob"; + compatible = "google,bob-rev13", "google,bob-rev12", + "google,bob-rev11", "google,bob-rev10", + "google,bob-rev9", "google,bob-rev8", + "google,bob-rev7", "google,bob-rev6", + "google,bob-rev5", "google,bob-rev4", + "google,bob", "google,gru", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "boe,nv101wxmn51", "simple-panel"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&ap_i2c_ts { + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l &touch_reset_l>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; +}; + +&ap_i2c_tp { + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + wakeup-source; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&spi0 { + status = "okay"; +}; + +&pinctrl { + tpm { + h1_int_od_l: h1-int-od-l { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi new file mode 100644 index 0000000000..c6495adcca --- /dev/null +++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Chromebook shared properties + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/ { + pp900_ap: pp900-ap { + compatible = "regulator-fixed"; + regulator-name = "pp900_ap"; + + /* EC turns on w/ pp900_ap_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + /* EC turns on w/ pp900_usb_en */ + pp900_usb: pp900-ap { + }; + + /* EC turns on w/ pp900_pcie_en */ + pp900_pcie: pp900-ap { + }; + + pp3000: pp3000 { + compatible = "regulator-fixed"; + regulator-name = "pp3000"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3000_en>; + + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_centerlogic_pwm"; + + pwms = <&pwm3 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + }; + + ppvar_centerlogic: ppvar-centerlogic { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_centerlogic"; + + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + + ctrl-supply = <&ppvar_centerlogic_pwm>; + ctrl-voltage-range = <799434 1049925>; + + regulator-settling-time-up-us = <378>; + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; + }; + + /* Schematics call this PPVAR even though it's fixed */ + ppvar_logic: ppvar-logic { + compatible = "regulator-fixed"; + regulator-name = "ppvar_logic"; + + /* EC turns on w/ ppvar_logic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800_audio: pp1800-audio { + compatible = "regulator-fixed"; + regulator-name = "pp1800_audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_audio_en>; + + enable-active-high; + gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp1800>; + }; + + /* gpio is shared with pp3300_wifi_bt */ + pp1800_pcie: pp1800-pcie { + compatible = "regulator-fixed"; + regulator-name = "pp1800_pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_pd_l>; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Need to wait 1ms + ramp-up time before we can power on WiFi. + * This has been approximated as 8ms total. + */ + regulator-enable-ramp-delay = <8000>; + + vin-supply = <&pp1800>; + }; + + /* Always on; plain and simple */ + pp3000_ap: pp3000_emmc: pp3000 { + }; + + pp1500_ap_io: pp1500-ap-io { + compatible = "regulator-fixed"; + regulator-name = "pp1500_ap_io"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1500_en>; + + enable-active-high; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&pp1800>; + }; + + pp3300_disp: pp3300-disp { + compatible = "regulator-fixed"; + regulator-name = "pp3300_disp"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_disp_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <2000>; + vin-supply = <&pp3300>; + }; + + /* EC turns on w/ pp3300_usb_en_l */ + pp3300_usb: pp3300 { + }; + + /* gpio is shared with pp1800_pcie and pinctrl is set there */ + pp3300_wifi_bt: pp3300-wifi-bt { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wifi_bt"; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3300>; + }; + + /* + * This is a bit of a hack. The WiFi module should be reset at least + * 1ms after its regulators have ramped up (max rampup time is ~7ms). + * With some stretching of the imagination, we can call the 1.8V + * regulator a supply. + */ + wlan_pd_n: wlan-pd-n { + compatible = "regulator-fixed"; + regulator-name = "wlan_pd_n"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_reset_l>; + + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp1800_pcie>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 + 45 46 47 48 49 50 51 52 53 54 55 56 57 58 + 59 60 61 62 63 64 65 66 67 68 69 70 71 72 + 73 74 75 76 77 78 79 80 81 82 83 84 85 86 + 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; + default-brightness-level = <51>; + enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + power-supply = <&pp3300_disp>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwm-delay-us = <10000>; + }; +}; + +&ppvar_bigcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_litcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_gpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>, <&usbc_extcon1>; +}; + +&edp { + status = "okay"; + + rockchip,panel = <&edp_panel>; + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +ap_i2c_mic: &i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + headsetcodec: rt5514@57 { + compatible = "realtek,rt5514"; + reg = <0x57>; + realtek,dmic-init-delay-ms = <20>; + }; +}; + +ap_i2c_tp: &i2c5 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* + * Note strange pullup enable. Apparently this avoids leakage but + * still allows us to get nice 4.7K pullups for high speed i2c + * transfers. Basically we want the pullup on whenever the ap is + * alive, so the "en" pin just gets set to output high. + */ + pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; +}; + +&cros_ec { + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + usbc_extcon1: extcon@1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + + #extcon-cells = <0>; + }; +}; + +&sound { + rockchip,codec = <&max98357a &headsetcodec + &codec &wacky_spi_audio &cdn_dp>; +}; + +&spi2 { + wacky_spi_audio: spi2@0 { + compatible = "realtek,rt5514"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mic_int>; + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + wakeup-source; + }; +}; + +&pci_rootport { + mvl_wifi: wifi@0,0 { + compatible = "pci1b4b,2b42"; + reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 + 0x83010000 0x0 0x00100000 0x0 0x00100000>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_host_wake_l>; + wakeup-source; + }; +}; + +&tcphy1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&u2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&pinctrl { + discrete-regulators { + pp1500_en: pp1500-en { + rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp1800_audio_en: pp1800-audio-en { + rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + + pp3000_en: pp3000-en { + rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp3300_disp_en: pp3300-disp-en { + rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + wlan_module_pd_l: wlan-module-pd-l { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + }; +}; + +&wifi { + wifi_perst_l: wifi-perst-l { + rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; +}; diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts new file mode 100644 index 0000000000..2cc7c47d6a --- /dev/null +++ b/arch/arm/dts/rk3399-gru-kevin.dts @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Kevin Rev 6+ board device tree source + * + * Copyright 2016-2017 Google, Inc + */ + +/dts-v1/; +#include "rk3399-gru-chromebook.dtsi" +#include <dt-bindings/input/linux-event-codes.h> + +/* + * Kevin-specific things + * + * Things in this section should use names from Kevin schematic since no + * equivalent exists in Gru schematic. If referring to signals that exist + * in Gru we use the Gru names, though. Confusing enough for you? + */ +/ { + model = "Google Kevin"; + compatible = "google,kevin-rev15", "google,kevin-rev14", + "google,kevin-rev13", "google,kevin-rev12", + "google,kevin-rev11", "google,kevin-rev10", + "google,kevin-rev9", "google,kevin-rev8", + "google,kevin-rev7", "google,kevin-rev6", + "google,kevin", "google,gru", "rockchip,rk3399"; + + /* Power tree */ + + p3_3v_dig: p3-3v-dig { + compatible = "regulator-fixed"; + regulator-name = "p3.3v_dig"; + pinctrl-names = "default"; + pinctrl-0 = <&cpu3_pen_pwr_en>; + + enable-active-high; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300>; + }; + + edp_panel: edp-panel { + compatible = "sharp,lq123p1jx31", "simple-panel"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <25500>; + pulldown-ohm = <0>; + io-channels = <&saradc 2>; + #thermal-sensor-cells = <0>; + }; + + thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <25500>; + pulldown-ohm = <0>; + io-channels = <&saradc 3>; + #thermal-sensor-cells = <0>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 1>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; + + pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + linux,code = <SW_PEN_INSERTED>; + linux,input-type = <EV_SW>; + wakeup-source; + }; +}; + +&thermal_zones { + bigcpu_reg_thermal: bigcpu-reg-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermistor_ppvar_bigcpu 0>; + sustainable-power = <4000>; + + ppvar_bigcpu_trips: trips { + ppvar_bigcpu_on: ppvar-bigcpu-on { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_bigcpu_alert: ppvar-bigcpu-alert { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_bigcpu_crit: ppvar-bigcpu-crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&ppvar_bigcpu_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&ppvar_bigcpu_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + litcpu_reg_thermal: litcpu-reg-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermistor_ppvar_litcpu 0>; + sustainable-power = <4000>; + + ppvar_litcpu_trips: trips { + ppvar_litcpu_on: ppvar-litcpu-on { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_litcpu_alert: ppvar-litcpu-alert { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_litcpu_crit: ppvar-litcpu-crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; +}; + +ap_i2c_tpm: &i2c0 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +ap_i2c_dig: &i2c2 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + digitizer: digitizer@9 { + /* wacom,w9013 */ + compatible = "hid-over-i2c"; + reg = <0x9>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>; + + vdd-supply = <&p3_3v_dig>; + post-power-on-delay-ms = <100>; + + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x1>; + }; +}; + +/* Adjustments to things in the gru baseboard */ + +&ap_i2c_tp { + trackpad@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + linux,gpio-keymap = <KEY_RESERVED + KEY_RESERVED + KEY_RESERVED + BTN_LEFT>; + wakeup-source; + }; +}; + +&ap_i2c_ts { + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ppvar_bigcpu_pwm { + regulator-min-microvolt = <798674>; + regulator-max-microvolt = <1302172>; +}; + +&ppvar_bigcpu { + regulator-min-microvolt = <798674>; + regulator-max-microvolt = <1302172>; + ctrl-voltage-range = <798674 1302172>; +}; + +&ppvar_litcpu_pwm { + regulator-min-microvolt = <799065>; + regulator-max-microvolt = <1303738>; +}; + +&ppvar_litcpu { + regulator-min-microvolt = <799065>; + regulator-max-microvolt = <1303738>; + ctrl-voltage-range = <799065 1303738>; +}; + +&ppvar_gpu_pwm { + regulator-min-microvolt = <785782>; + regulator-max-microvolt = <1217729>; +}; + +&ppvar_gpu { + regulator-min-microvolt = <785782>; + regulator-max-microvolt = <1217729>; + ctrl-voltage-range = <785782 1217729>; +}; + +&ppvar_centerlogic_pwm { + regulator-min-microvolt = <800069>; + regulator-max-microvolt = <1049692>; +}; + +&ppvar_centerlogic { + regulator-min-microvolt = <800069>; + regulator-max-microvolt = <1049692>; + ctrl-voltage-range = <800069 1049692>; +}; + +&saradc { + status = "okay"; + vref-supply = <&pp1800_ap_io>; +}; + +&mvl_wifi { + marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */ +}; + +&pinctrl { + digitizer { + /* Has external pullup */ + cpu1_dig_irq_l: cpu1-dig-irq-l { + rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* Has external pullup */ + cpu1_dig_pdct_l: cpu1-dig-pdct-l { + rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + discrete-regulators { + cpu3_pen_pwr_en: cpu3-pen-pwr-en { + rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + cpu1_pen_eject: cpu1-pen-eject { + rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi new file mode 100644 index 0000000000..df19263acc --- /dev/null +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -0,0 +1,844 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru (and derivatives) board device tree source + * + * Copyright 2016-2017 Google, Inc + */ + +#include <dt-bindings/input/input.h> +#include "rk3399.dtsi" +#include "rk3399-op1-opp.dtsi" + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = "serial2:115200n8"; + u-boot,spl-boot-order = &spi_flash; + }; + + config { + u-boot,spl-payload-offset = <0x40000>; + }; + + /* + * Power Tree + * + * In general an attempt is made to include all rails called out by + * the schematic as long as those rails interact in some way with + * the AP. AKA: + * - Rails that only connect to the EC (or devices that the EC talks to) + * are not included. + * - Rails _are_ included if the rails go to the AP even if the AP + * doesn't currently care about them / they are always on. The idea + * here is that it makes it easier to map to the schematic or extend + * later. + * + * If two rails are substantially the same from the AP's point of + * view, though, we won't create a full fixed regulator. We'll just + * put the child rail as an alias of the parent rail. Sometimes rails + * look the same to the AP because one of these is true: + * - The EC controls the enable and the EC always enables a rail as + * long as the AP is running. + * - The rails are actually connected to each other by a jumper and + * the distinction is just there to add clarity/flexibility to the + * schematic. + */ + + ppvar_sys: ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + pp1200_lpddr: pp1200-lpddr { + compatible = "regulator-fixed"; + regulator-name = "pp1200_lpddr"; + + /* EC turns on w/ lpddr_pwr_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800: pp1800 { + compatible = "regulator-fixed"; + regulator-name = "pp1800"; + + /* Always on when ppvar_sys shows power good */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300: pp3300 { + compatible = "regulator-fixed"; + regulator-name = "pp3300"; + + /* Always on; plain and simple */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&ppvar_sys>; + }; + + pp5000: pp5000 { + compatible = "regulator-fixed"; + regulator-name = "pp5000"; + + /* EC turns on w/ pp5000_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_bigcpu_pwm"; + + pwms = <&pwm1 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800107>; + regulator-max-microvolt = <1302232>; + }; + + ppvar_bigcpu: ppvar-bigcpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_bigcpu"; + + regulator-min-microvolt = <800107>; + regulator-max-microvolt = <1302232>; + + ctrl-supply = <&ppvar_bigcpu_pwm>; + ctrl-voltage-range = <800107 1302232>; + + regulator-settling-time-up-us = <322>; + }; + + ppvar_litcpu_pwm: ppvar-litcpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_litcpu_pwm"; + + pwms = <&pwm2 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <797743>; + regulator-max-microvolt = <1307837>; + }; + + ppvar_litcpu: ppvar-litcpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_litcpu"; + + regulator-min-microvolt = <797743>; + regulator-max-microvolt = <1307837>; + + ctrl-supply = <&ppvar_litcpu_pwm>; + ctrl-voltage-range = <797743 1307837>; + + regulator-settling-time-up-us = <384>; + }; + + ppvar_gpu_pwm: ppvar-gpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_gpu_pwm"; + + pwms = <&pwm0 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <786384>; + regulator-max-microvolt = <1217747>; + }; + + ppvar_gpu: ppvar-gpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_gpu"; + + regulator-min-microvolt = <786384>; + regulator-max-microvolt = <1217747>; + + ctrl-supply = <&ppvar_gpu_pwm>; + ctrl-voltage-range = <786384 1217747>; + + regulator-settling-time-up-us = <390>; + }; + + /* EC turns on w/ pp900_ddrpll_en */ + pp900_ddrpll: pp900-ap { + }; + + /* EC turns on w/ pp900_pll_en */ + pp900_pll: pp900-ap { + }; + + /* EC turns on w/ pp900_pmu_en */ + pp900_pmu: pp900-ap { + }; + + /* EC turns on w/ pp1800_s0_en_l */ + pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { + }; + + /* EC turns on w/ pp1800_avdd_en_l */ + pp1800_avdd: pp1800 { + }; + + /* EC turns on w/ pp1800_lid_en_l */ + pp1800_lid: pp1800_mic: pp1800 { + }; + + /* EC turns on w/ lpddr_pwr_en */ + pp1800_lpddr: pp1800 { + }; + + /* EC turns on w/ pp1800_pmu_en_l */ + pp1800_pmu: pp1800 { + }; + + /* EC turns on w/ pp1800_usb_en_l */ + pp1800_usb: pp1800 { + }; + + pp3000_sd_slot: pp3000-sd-slot { + compatible = "regulator-fixed"; + regulator-name = "pp3000_sd_slot"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_slot_pwr_en>; + + enable-active-high; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3000>; + }; + + /* + * Technically, this is a small abuse of 'regulator-gpio'; this + * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are + * always on though, so it is sufficient to simply control the mux + * here. + */ + ppvar_sd_card_io: ppvar-sd-card-io { + compatible = "regulator-gpio"; + regulator-name = "ppvar_sd_card_io"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; + + enable-active-high; + enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3000000 0x0>; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + /* EC turns on w/ pp3300_trackpad_en_l */ + pp3300_trackpad: pp3300-trackpad { + }; + + /* EC turns on w/ usb_a_en */ + pp5000_usb_a_vbus: pp5000 { + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + + wake_on_bt: wake-on-bt { + label = "Wake-on-Bluetooth"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + max98357a: max98357a { + compatible = "maxim,max98357a"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmode_en>; + sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sdmode-delay = <2>; + #sound-dai-cells = <0>; + status = "okay"; + }; + + sound: sound { + compatible = "rockchip,rk3399-gru-sound"; + rockchip,cpu = <&i2s0 &i2s2>; + }; +}; + +&cdn_dp { + status = "okay"; +}; + +/* + * Set some suspend operating points to avoid OVP in suspend + * + * When we go into S3 ARM Trusted Firmware will transition our PWM regulators + * from wherever they're at back to the "default" operating point (whatever + * voltage we get when we set the PWM pins to "input"). + * + * This quick transition under light load has the possibility to trigger the + * regulator "over voltage protection" (OVP). + * + * To make extra certain that we don't hit this OVP at suspend time, we'll + * transition to a voltage that's much closer to the default (~1.0 V) so that + * there will not be a big jump. Technically we only need to get within 200 mV + * of the default voltage, but the speed here should be fast enough and we need + * suspend/resume to be rock solid. + */ + +&cluster0_opp { + opp05 { + opp-suspend; + }; +}; + +&cluster1_opp { + opp06 { + opp-suspend; + }; +}; + +&cpu_l0 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l1 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l2 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l3 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_b0 { + cpu-supply = <&ppvar_bigcpu>; +}; + +&cpu_b1 { + cpu-supply = <&ppvar_bigcpu>; +}; + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; + assigned-clock-rates = + <600000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, <800000000>, + <100000000>, <50000000>, + <400000000>, <400000000>, + <200000000>, + <200000000>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&ppvar_gpu>; + status = "okay"; +}; + +ap_i2c_ts: &i2c3 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; +}; + +ap_i2c_audio: &i2c8 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + codec: da7219@1a { + compatible = "dlg,da7219"; + reg = <0x1a>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + dlg,micbias-lvl = <2600>; + dlg,mic-amp-in-sel = "diff"; + pinctrl-names = "default"; + pinctrl-0 = <&headset_int_l>; + VDD-supply = <&pp1800>; + VDDMIC-supply = <&pp3300>; + VDDIO-supply = <&pp1800>; + + da7219_aad { + dlg,adc-1bit-rpt = <1>; + dlg,btn-avg = <4>; + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; + dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-rem-deb = <1>; + + dlg,a-d-btn-thr = <0xa>; + dlg,d-b-btn-thr = <0x16>; + dlg,b-c-btn-thr = <0x21>; + dlg,c-mic-btn-thr = <0x3E>; + }; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ + bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ + gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ + sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ +}; + +&pcie0 { + status = "okay"; + + ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; + vpcie3v3-supply = <&pp3300_wifi_bt>; + vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ + vpcie0v9-supply = <&pp900_pcie>; + + pci_rootport: pcie@0,0 { + reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + /* + * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the + * same (or nearly the same) performance for all eMMC that are intended + * to be used. + */ + assigned-clock-rates = <150000000>; + + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + status = "okay"; + + /* + * Note: configure "sdmmc_cd" as card detect even though it's actually + * hooked to ground. Because we specified "cd-gpios" below dw_mmc + * should be ignoring card detect anyway. Specifying the pin as + * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) + * turned on that the system will still make sure the port is + * configured as SDMMC and not JTAG. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio + &sdmmc_bus4>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&pp3000_sd_slot>; + vqmmc-supply = <&ppvar_sd_card_io>; +}; + +&spi1 { + status = "okay"; + u-boot,dm-pre-reloc; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&spi1_sleep>; + + spi_flash: spiflash@0 { + u-boot,dm-pre-reloc; + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0>; + + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + }; +}; + +&spi2 { + status = "okay"; +}; + +&spi5 { + status = "okay"; + spi-activate-delay = <100>; + spi-max-frequency = <3000000>; + spi-deactivate-delay = <200>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_ap_int_l>; + spi-max-frequency = <3000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbc_extcon0: extcon@0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + + #extcon-cells = <0>; + }; + }; +}; + +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +}; + +&tcphy0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +#include <cros-ec-keyboard.dtsi> +#include <cros-ec-sbs.dtsi> + +&pinctrl { + /* + * pinctrl settings for pins that have no real owners. + * + * At the moment settings are identical for S0 and S3, but if we later + * need to configure things differently for S3 we'll adjust here. + */ + pinctrl-names = "default"; + pinctrl-0 = < + &ap_pwroff /* AP will auto-assert this when in S3 */ + &clk_32k /* This pin is always 32k on gru boards */ + >; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + backlight-enable { + bl_en: bl-en { + rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cros-ec { + ec_ap_int_l: ec-ap-int-l { + rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + discrete-regulators { + sd_io_pwr_en: sd-io-pwr-en { + rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + sd_pwr_1800_sel: sd-pwr-1800-sel { + rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + sd_slot_pwr_en: sd-slot-pwr-en { + rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + }; + + codec { + /* Has external pullup */ + headset_int_l: headset-int-l { + rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mic_int: mic-int { + rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + max98357a { + sdmode_en: sdmode-en { + rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_clkreqn_cpm: pci-clkreqn-cpm { + /* + * Since our pcie doesn't support ClockPM(CPM), we want + * to hack this as gpio, so the EP could be able to + * de-assert it along and make ClockPM(CPM) work. + */ + rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * We run sdmmc at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, + <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, + <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, + <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + /* + * In our case the official card detect is hooked to ground + * to avoid getting access to JTAG just by sticking something + * in the SD card slot (see the force_jtag bit in the TRM). + * + * We still configure it as card detect because it doesn't + * hurt and dw_mmc will ignore it. We make sure to disable + * the pull though so we don't burn needless power. + */ + sdmmc_cd: sdmmc-cd { + rockchip,pins = + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + + /* This is where we actually hook up CD; has external pull */ + sdmmc_cd_gpio: sdmmc-cd-gpio { + rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + spi1 { + spi1_sleep: spi1-sleep { + /* + * Pull down SPI1 CLK/CS/RX/TX during suspend, to + * prevent leakage. + */ + rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, + <1 10 RK_FUNC_GPIO &pcfg_pull_down>, + <1 7 RK_FUNC_GPIO &pcfg_pull_down>, + <1 8 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + touchscreen { + touch_int_l: touch-int-l { + rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch_reset_l: touch-reset-l { + rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + trackpad { + ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { + rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; + }; + + trackpad_int_l: trackpad-int-l { + rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi: wifi { + wlan_module_reset_l: wlan-module-reset-l { + rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + /* Kevin has an external pull up, but Gru does not */ + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + write-protect { + ap_fw_wp: ap-fw-wp { + rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi new file mode 100644 index 0000000000..69cc9b05ba --- /dev/null +++ b/arch/arm/dts/rk3399-op1-opp.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <975000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1100000>; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1150000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <900000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <975000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1050000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1150000>; + }; + opp08 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1250000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <850000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <925000>; + }; + opp05 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1075000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi new file mode 100644 index 0000000000..2a627e1be5 --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi @@ -0,0 +1,1542 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +&dmc { + rockchip,sdram-params = < + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + + 0x801d181e + 0x17050a08 + 0x00000002 + 0x00006426 + 0x0000004c + 0x00000000 + + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + + 0x801d181e + 0x17050a08 + 0x00000002 + 0x00006426 + 0x0000004c + 0x00000000 + + 933 + 6 /* LPDDR3 */ + 2 + 13 + 1 + + 0x00000700 /* DENALI_CTL_00_DATA */ + 0x00000000 /* DENALI_CTL_01_DATA */ + 0x00000000 /* DENALI_CTL_02_DATA */ + 0x00000000 /* DENALI_CTL_03_DATA */ + 0x00000000 /* DENALI_CTL_04_DATA */ + 0x0000005e /* DENALI_CTL_05_DATA */ + 0x0002d976 /* DENALI_CTL_06_DATA */ + 0x000003a6 /* DENALI_CTL_07_DATA */ + 0x0000247a /* DENALI_CTL_08_DATA */ + 0x0000005e /* DENALI_CTL_09_DATA */ + 0x0002d976 /* DENALI_CTL_10_DATA */ + 0x000003a6 /* DENALI_CTL_11_DATA */ + 0x0000247a /* DENALI_CTL_12_DATA */ + 0x0000005e /* DENALI_CTL_13_DATA */ + 0x0002d976 /* DENALI_CTL_14_DATA */ + 0x000003a6 /* DENALI_CTL_15_DATA */ + 0x0100247a /* DENALI_CTL_16_DATA */ + 0x00000000 /* DENALI_CTL_17_DATA */ + 0x00000101 /* DENALI_CTL_18_DATA */ + 0x00020100 /* DENALI_CTL_19_DATA */ + 0x000000bb /* DENALI_CTL_20_DATA */ + 0x000001d3 /* DENALI_CTL_21_DATA */ + 0x00000000 /* DENALI_CTL_22_DATA */ + 0x081c0000 /* DENALI_CTL_23_DATA */ + 0x00081c00 /* DENALI_CTL_24_DATA */ + 0x0400081c /* DENALI_CTL_25_DATA */ + 0x3b0a0004 /* DENALI_CTL_26_DATA */ + 0x2f110828 /* DENALI_CTL_27_DATA */ + 0x283b0a00 /* DENALI_CTL_28_DATA */ + 0x002f1108 /* DENALI_CTL_29_DATA */ + 0x08283b0a /* DENALI_CTL_30_DATA */ + 0x08002f11 /* DENALI_CTL_31_DATA */ + 0x00000a0a /* DENALI_CTL_32_DATA */ + 0x0800ff4f /* DENALI_CTL_33_DATA */ + 0x0a0a080f /* DENALI_CTL_34_DATA */ + 0x0800ff4f /* DENALI_CTL_35_DATA */ + 0x0a0a080f /* DENALI_CTL_36_DATA */ + 0x0800ff4f /* DENALI_CTL_37_DATA */ + 0x0203000f /* DENALI_CTL_38_DATA */ + 0x110f1100 /* DENALI_CTL_39_DATA */ + 0x040f110f /* DENALI_CTL_40_DATA */ + 0x14000a0a /* DENALI_CTL_41_DATA */ + 0x03030a0a /* DENALI_CTL_42_DATA */ + 0x00010003 /* DENALI_CTL_43_DATA */ + 0x03212121 /* DENALI_CTL_44_DATA */ + 0x00141414 /* DENALI_CTL_45_DATA */ + 0x00000000 /* DENALI_CTL_46_DATA */ + 0x03010000 /* DENALI_CTL_47_DATA */ + 0x0e3100c5 /* DENALI_CTL_48_DATA */ + 0x0e3100c5 /* DENALI_CTL_49_DATA */ + 0x0e3100c5 /* DENALI_CTL_50_DATA */ + 0x00000000 /* DENALI_CTL_51_DATA */ + 0x00080008 /* DENALI_CTL_52_DATA */ + 0x00170008 /* DENALI_CTL_53_DATA */ + 0x00170017 /* DENALI_CTL_54_DATA */ + 0x00111111 /* DENALI_CTL_55_DATA */ + 0x00000000 /* DENALI_CTL_56_DATA */ + 0x00000000 /* DENALI_CTL_57_DATA */ + 0x00000000 /* DENALI_CTL_58_DATA */ + 0x00ce0000 /* DENALI_CTL_59_DATA */ + 0x00ce00ce /* DENALI_CTL_60_DATA */ + 0x00ce00ce /* DENALI_CTL_61_DATA */ + 0x000000ce /* DENALI_CTL_62_DATA */ + 0x00000000 /* DENALI_CTL_63_DATA */ + 0x00000000 /* DENALI_CTL_64_DATA */ + 0x00000000 /* DENALI_CTL_65_DATA */ + 0x00000000 /* DENALI_CTL_66_DATA */ + 0x00000000 /* DENALI_CTL_67_DATA */ + 0x00000000 /* DENALI_CTL_68_DATA */ + 0x00000301 /* DENALI_CTL_69_DATA */ + 0x00000001 /* DENALI_CTL_70_DATA */ + 0x00000000 /* DENALI_CTL_71_DATA */ + 0x00000000 /* DENALI_CTL_72_DATA */ + 0x01000000 /* DENALI_CTL_73_DATA */ + 0x80104002 /* DENALI_CTL_74_DATA */ + 0x00040003 /* DENALI_CTL_75_DATA */ + 0x00040005 /* DENALI_CTL_76_DATA */ + 0x00030000 /* DENALI_CTL_77_DATA */ + 0x00050004 /* DENALI_CTL_78_DATA */ + 0x00000004 /* DENALI_CTL_79_DATA */ + 0x00040003 /* DENALI_CTL_80_DATA */ + 0x00040005 /* DENALI_CTL_81_DATA */ + 0x38c40000 /* DENALI_CTL_82_DATA */ + 0x00001c62 /* DENALI_CTL_83_DATA */ + 0x1c6238c4 /* DENALI_CTL_84_DATA */ + 0x38c40000 /* DENALI_CTL_85_DATA */ + 0x00001c62 /* DENALI_CTL_86_DATA */ + 0x00000000 /* DENALI_CTL_87_DATA */ + 0x00000000 /* DENALI_CTL_88_DATA */ + 0x00000000 /* DENALI_CTL_89_DATA */ + 0x00000000 /* DENALI_CTL_90_DATA */ + 0x00000000 /* DENALI_CTL_91_DATA */ + 0x02020200 /* DENALI_CTL_92_DATA */ + 0x00020202 /* DENALI_CTL_93_DATA */ + 0x00030200 /* DENALI_CTL_94_DATA */ + 0x00040700 /* DENALI_CTL_95_DATA */ + 0x00000302 /* DENALI_CTL_96_DATA */ + 0x02000407 /* DENALI_CTL_97_DATA */ + 0x00000003 /* DENALI_CTL_98_DATA */ + 0x00030f04 /* DENALI_CTL_99_DATA */ + 0x00070004 /* DENALI_CTL_100_DATA */ + 0x00000000 /* DENALI_CTL_101_DATA */ + 0x00000000 /* DENALI_CTL_102_DATA */ + 0x00000000 /* DENALI_CTL_103_DATA */ + 0x00000000 /* DENALI_CTL_104_DATA */ + 0x00000000 /* DENALI_CTL_105_DATA */ + 0x00000000 /* DENALI_CTL_106_DATA */ + 0x00000000 /* DENALI_CTL_107_DATA */ + 0x00010000 /* DENALI_CTL_108_DATA */ + 0x20040020 /* DENALI_CTL_109_DATA */ + 0x00200400 /* DENALI_CTL_110_DATA */ + 0x01000400 /* DENALI_CTL_111_DATA */ + 0x00000b80 /* DENALI_CTL_112_DATA */ + 0x00000000 /* DENALI_CTL_113_DATA */ + 0x00000001 /* DENALI_CTL_114_DATA */ + 0x00000002 /* DENALI_CTL_115_DATA */ + 0x0000000e /* DENALI_CTL_116_DATA */ + 0x00000000 /* DENALI_CTL_117_DATA */ + 0x00000000 /* DENALI_CTL_118_DATA */ + 0x00000000 /* DENALI_CTL_119_DATA */ + 0x00000000 /* DENALI_CTL_120_DATA */ + 0x00000000 /* DENALI_CTL_121_DATA */ + 0x00bb0000 /* DENALI_CTL_122_DATA */ + 0x00ea005e /* DENALI_CTL_123_DATA */ + 0x00ea0000 /* DENALI_CTL_124_DATA */ + 0x005e00bb /* DENALI_CTL_125_DATA */ + 0x000000ea /* DENALI_CTL_126_DATA */ + 0x00bb00ea /* DENALI_CTL_127_DATA */ + 0x00ea005e /* DENALI_CTL_128_DATA */ + 0x00ea0000 /* DENALI_CTL_129_DATA */ + 0x00000000 /* DENALI_CTL_130_DATA */ + 0x00000000 /* DENALI_CTL_131_DATA */ + 0x00000000 /* DENALI_CTL_132_DATA */ + 0x00c30000 /* DENALI_CTL_133_DATA */ + 0x0000001c /* DENALI_CTL_134_DATA */ + 0x001c00c3 /* DENALI_CTL_135_DATA */ + 0x00c30000 /* DENALI_CTL_136_DATA */ + 0x0000001c /* DENALI_CTL_137_DATA */ + 0x00010001 /* DENALI_CTL_138_DATA */ + 0x06000001 /* DENALI_CTL_139_DATA */ + 0x00000606 /* DENALI_CTL_140_DATA */ + 0x00000000 /* DENALI_CTL_141_DATA */ + 0x00000000 /* DENALI_CTL_142_DATA */ + 0x00000000 /* DENALI_CTL_143_DATA */ + 0x00000000 /* DENALI_CTL_144_DATA */ + 0x00000000 /* DENALI_CTL_145_DATA */ + 0x00000000 /* DENALI_CTL_146_DATA */ + 0x00c30000 /* DENALI_CTL_147_DATA */ + 0x0000001c /* DENALI_CTL_148_DATA */ + 0x001c00c3 /* DENALI_CTL_149_DATA */ + 0x00c30000 /* DENALI_CTL_150_DATA */ + 0x0000001c /* DENALI_CTL_151_DATA */ + 0x00010001 /* DENALI_CTL_152_DATA */ + 0x06000001 /* DENALI_CTL_153_DATA */ + 0x00000606 /* DENALI_CTL_154_DATA */ + 0x00000000 /* DENALI_CTL_155_DATA */ + 0x00000000 /* DENALI_CTL_156_DATA */ + 0x00000000 /* DENALI_CTL_157_DATA */ + 0x00000000 /* DENALI_CTL_158_DATA */ + 0x00000000 /* DENALI_CTL_159_DATA */ + 0x00000000 /* DENALI_CTL_160_DATA */ + 0x01000000 /* DENALI_CTL_161_DATA */ + 0x00000000 /* DENALI_CTL_162_DATA */ + 0x00000000 /* DENALI_CTL_163_DATA */ + 0x18151100 /* DENALI_CTL_164_DATA */ + 0x0000000c /* DENALI_CTL_165_DATA */ + 0x00000000 /* DENALI_CTL_166_DATA */ + 0x00000000 /* DENALI_CTL_167_DATA */ + 0x00000000 /* DENALI_CTL_168_DATA */ + 0x00000000 /* DENALI_CTL_169_DATA */ + 0x00000000 /* DENALI_CTL_170_DATA */ + 0x00000000 /* DENALI_CTL_171_DATA */ + 0x00000000 /* DENALI_CTL_172_DATA */ + 0x00000000 /* DENALI_CTL_173_DATA */ + 0x00000000 /* DENALI_CTL_174_DATA */ + 0x00000000 /* DENALI_CTL_175_DATA */ + 0x00000000 /* DENALI_CTL_176_DATA */ + 0x00000000 /* DENALI_CTL_177_DATA */ + 0x00000000 /* DENALI_CTL_178_DATA */ + 0x0003a603 /* DENALI_CTL_179_DATA */ + 0x00550151 /* DENALI_CTL_180_DATA */ + 0x00000000 /* DENALI_CTL_181_DATA */ + 0x015103a6 /* DENALI_CTL_182_DATA */ + 0x00000055 /* DENALI_CTL_183_DATA */ + 0x0003a600 /* DENALI_CTL_184_DATA */ + 0x00550151 /* DENALI_CTL_185_DATA */ + 0x00000000 /* DENALI_CTL_186_DATA */ + 0x002f0000 /* DENALI_CTL_187_DATA */ + 0x002f002f /* DENALI_CTL_188_DATA */ + 0x01010100 /* DENALI_CTL_189_DATA */ + 0x01000202 /* DENALI_CTL_190_DATA */ + 0x0a000002 /* DENALI_CTL_191_DATA */ + 0x01000f0f /* DENALI_CTL_192_DATA */ + 0x00000000 /* DENALI_CTL_193_DATA */ + 0x00000000 /* DENALI_CTL_194_DATA */ + 0x00010003 /* DENALI_CTL_195_DATA */ + 0x00000c03 /* DENALI_CTL_196_DATA */ + 0x00000100 /* DENALI_CTL_197_DATA */ + 0x00010000 /* DENALI_CTL_198_DATA */ + 0x01000000 /* DENALI_CTL_199_DATA */ + 0x00010000 /* DENALI_CTL_200_DATA */ + 0x00000001 /* DENALI_CTL_201_DATA */ + 0x00000000 /* DENALI_CTL_202_DATA */ + 0x00000000 /* DENALI_CTL_203_DATA */ + 0x00000000 /* DENALI_CTL_204_DATA */ + 0x00000000 /* DENALI_CTL_205_DATA */ + 0x00000000 /* DENALI_CTL_206_DATA */ + 0x00000000 /* DENALI_CTL_207_DATA */ + 0x00000000 /* DENALI_CTL_208_DATA */ + 0x00000000 /* DENALI_CTL_209_DATA */ + 0x00000000 /* DENALI_CTL_210_DATA */ + 0x00010000 /* DENALI_CTL_211_DATA */ + 0x04040401 /* DENALI_CTL_212_DATA */ + 0x01010808 /* DENALI_CTL_213_DATA */ + 0x04040001 /* DENALI_CTL_214_DATA */ + 0x0c0c0c04 /* DENALI_CTL_215_DATA */ + 0x08080808 /* DENALI_CTL_216_DATA */ + 0x08050103 /* DENALI_CTL_217_DATA */ + 0x02050103 /* DENALI_CTL_218_DATA */ + 0x00050103 /* DENALI_CTL_219_DATA */ + 0x00020202 /* DENALI_CTL_220_DATA */ + 0x06030600 /* DENALI_CTL_221_DATA */ + 0x00030603 /* DENALI_CTL_222_DATA */ + 0x00000000 /* DENALI_CTL_223_DATA */ + 0x00000000 /* DENALI_CTL_224_DATA */ + 0x0d000001 /* DENALI_CTL_225_DATA */ + 0x00010028 /* DENALI_CTL_226_DATA */ + 0x00010000 /* DENALI_CTL_227_DATA */ + 0x00000003 /* DENALI_CTL_228_DATA */ + 0x00000000 /* DENALI_CTL_229_DATA */ + 0x00000000 /* DENALI_CTL_230_DATA */ + 0x00000000 /* DENALI_CTL_231_DATA */ + 0x00000000 /* DENALI_CTL_232_DATA */ + 0x00000000 /* DENALI_CTL_233_DATA */ + 0x00000000 /* DENALI_CTL_234_DATA */ + 0x00000000 /* DENALI_CTL_235_DATA */ + 0x00000000 /* DENALI_CTL_236_DATA */ + 0x00010100 /* DENALI_CTL_237_DATA */ + 0x01000000 /* DENALI_CTL_238_DATA */ + 0x00000001 /* DENALI_CTL_239_DATA */ + 0x00000303 /* DENALI_CTL_240_DATA */ + 0x00000000 /* DENALI_CTL_241_DATA */ + 0x00000000 /* DENALI_CTL_242_DATA */ + 0x00000000 /* DENALI_CTL_243_DATA */ + 0x00000000 /* DENALI_CTL_244_DATA */ + 0x00000000 /* DENALI_CTL_245_DATA */ + 0x00000000 /* DENALI_CTL_246_DATA */ + 0x00000000 /* DENALI_CTL_247_DATA */ + 0x00000000 /* DENALI_CTL_248_DATA */ + 0x00000000 /* DENALI_CTL_249_DATA */ + 0x00000000 /* DENALI_CTL_250_DATA */ + 0x00000000 /* DENALI_CTL_251_DATA */ + 0x00000000 /* DENALI_CTL_252_DATA */ + 0x00000000 /* DENALI_CTL_253_DATA */ + 0x00000000 /* DENALI_CTL_254_DATA */ + 0x00000000 /* DENALI_CTL_255_DATA */ + 0x000fffff /* DENALI_CTL_256_DATA */ + 0x00000000 /* DENALI_CTL_257_DATA */ + 0x000556aa /* DENALI_CTL_258_DATA */ + 0x000aaaaa /* DENALI_CTL_259_DATA */ + 0x000b3133 /* DENALI_CTL_260_DATA */ + 0x0004cd33 /* DENALI_CTL_261_DATA */ + 0x0004cecc /* DENALI_CTL_262_DATA */ + 0x000b32cc /* DENALI_CTL_263_DATA */ + 0x00010300 /* DENALI_CTL_264_DATA */ + 0x03000100 /* DENALI_CTL_265_DATA */ + 0x00000000 /* DENALI_CTL_266_DATA */ + 0x00000000 /* DENALI_CTL_267_DATA */ + 0x00000000 /* DENALI_CTL_268_DATA */ + 0x00000000 /* DENALI_CTL_269_DATA */ + 0x00000000 /* DENALI_CTL_270_DATA */ + 0x00000000 /* DENALI_CTL_271_DATA */ + 0x00000000 /* DENALI_CTL_272_DATA */ + 0x00000000 /* DENALI_CTL_273_DATA */ + 0x00ffff00 /* DENALI_CTL_274_DATA */ + 0x20200000 /* DENALI_CTL_275_DATA */ + 0x08000020 /* DENALI_CTL_276_DATA */ + 0x00001c62 /* DENALI_CTL_277_DATA */ + 0x00000200 /* DENALI_CTL_278_DATA */ + 0x00000200 /* DENALI_CTL_279_DATA */ + 0x00000200 /* DENALI_CTL_280_DATA */ + 0x00000200 /* DENALI_CTL_281_DATA */ + 0x00001c62 /* DENALI_CTL_282_DATA */ + 0x00011bd4 /* DENALI_CTL_283_DATA */ + 0x1c62070c /* DENALI_CTL_284_DATA */ + 0x00000200 /* DENALI_CTL_285_DATA */ + 0x00000200 /* DENALI_CTL_286_DATA */ + 0x00000200 /* DENALI_CTL_287_DATA */ + 0x00000200 /* DENALI_CTL_288_DATA */ + 0x00001c62 /* DENALI_CTL_289_DATA */ + 0x00011bd4 /* DENALI_CTL_290_DATA */ + 0x1c62070c /* DENALI_CTL_291_DATA */ + 0x00000200 /* DENALI_CTL_292_DATA */ + 0x00000200 /* DENALI_CTL_293_DATA */ + 0x00000200 /* DENALI_CTL_294_DATA */ + 0x00000200 /* DENALI_CTL_295_DATA */ + 0x00001c62 /* DENALI_CTL_296_DATA */ + 0x00011bd4 /* DENALI_CTL_297_DATA */ + 0x0202070c /* DENALI_CTL_298_DATA */ + 0x03030202 /* DENALI_CTL_299_DATA */ + 0x00000018 /* DENALI_CTL_300_DATA */ + 0x00000000 /* DENALI_CTL_301_DATA */ + 0x00000000 /* DENALI_CTL_302_DATA */ + 0x00001403 /* DENALI_CTL_303_DATA */ + 0x00000000 /* DENALI_CTL_304_DATA */ + 0x00000000 /* DENALI_CTL_305_DATA */ + 0x00000000 /* DENALI_CTL_306_DATA */ + 0x00030000 /* DENALI_CTL_307_DATA */ + 0x000f0021 /* DENALI_CTL_308_DATA */ + 0x000f0021 /* DENALI_CTL_309_DATA */ + 0x000f0021 /* DENALI_CTL_310_DATA */ + 0x00000000 /* DENALI_CTL_311_DATA */ + 0x00000000 /* DENALI_CTL_312_DATA */ + 0x01000000 /* DENALI_CTL_313_DATA */ + 0x02090209 /* DENALI_CTL_314_DATA */ + 0x00050209 /* DENALI_CTL_315_DATA */ + 0x00000000 /* DENALI_CTL_316_DATA */ + 0x00000000 /* DENALI_CTL_317_DATA */ + 0x00000000 /* DENALI_CTL_318_DATA */ + 0x00000000 /* DENALI_CTL_319_DATA */ + 0x00000000 /* DENALI_CTL_320_DATA */ + 0x00000000 /* DENALI_CTL_321_DATA */ + 0x00000000 /* DENALI_CTL_322_DATA */ + 0x00000000 /* DENALI_CTL_323_DATA */ + 0x01000101 /* DENALI_CTL_324_DATA */ + 0x01010101 /* DENALI_CTL_325_DATA */ + 0x01000101 /* DENALI_CTL_326_DATA */ + 0x01000100 /* DENALI_CTL_327_DATA */ + 0x00010001 /* DENALI_CTL_328_DATA */ + 0x00010002 /* DENALI_CTL_329_DATA */ + 0x00020100 /* DENALI_CTL_330_DATA */ + 0x00000002 /* DENALI_CTL_331_DATA */ + + 0x00000700 /* DENALI_PI_00_DATA */ + 0x00000000 /* DENALI_PI_01_DATA */ + 0x000038c4 /* DENALI_PI_02_DATA */ + 0x00001c62 /* DENALI_PI_03_DATA */ + 0x000038c4 /* DENALI_PI_04_DATA */ + 0x00001c62 /* DENALI_PI_05_DATA */ + 0x000038c4 /* DENALI_PI_06_DATA */ + 0x1c621c62 /* DENALI_PI_07_DATA */ + 0x00000200 /* DENALI_PI_08_DATA */ + 0x00000200 /* DENALI_PI_09_DATA */ + 0x00000200 /* DENALI_PI_10_DATA */ + 0x00000200 /* DENALI_PI_11_DATA */ + 0x00001c62 /* DENALI_PI_12_DATA */ + 0x00000200 /* DENALI_PI_13_DATA */ + 0x00000200 /* DENALI_PI_14_DATA */ + 0x00000200 /* DENALI_PI_15_DATA */ + 0x00000200 /* DENALI_PI_16_DATA */ + 0x00001c62 /* DENALI_PI_17_DATA */ + 0x00000200 /* DENALI_PI_18_DATA */ + 0x00000200 /* DENALI_PI_19_DATA */ + 0x00000200 /* DENALI_PI_20_DATA */ + 0x00000200 /* DENALI_PI_21_DATA */ + 0x00010000 /* DENALI_PI_22_DATA */ + 0x00000007 /* DENALI_PI_23_DATA */ + 0x81000001 /* DENALI_PI_24_DATA */ + 0x0f0003f0 /* DENALI_PI_25_DATA */ + 0x3fffffff /* DENALI_PI_26_DATA */ + 0x0f0000a0 /* DENALI_PI_27_DATA */ + 0x377ff000 /* DENALI_PI_28_DATA */ + 0x0f000020 /* DENALI_PI_29_DATA */ + 0x377ff000 /* DENALI_PI_30_DATA */ + 0x0f000030 /* DENALI_PI_31_DATA */ + 0x377ff000 /* DENALI_PI_32_DATA */ + 0x0f0000b0 /* DENALI_PI_33_DATA */ + 0x377ff000 /* DENALI_PI_34_DATA */ + 0x0f000100 /* DENALI_PI_35_DATA */ + 0x377ff000 /* DENALI_PI_36_DATA */ + 0x0f000110 /* DENALI_PI_37_DATA */ + 0x377ff000 /* DENALI_PI_38_DATA */ + 0x0f000010 /* DENALI_PI_39_DATA */ + 0x377ff000 /* DENALI_PI_40_DATA */ + 0x03000101 /* DENALI_PI_41_DATA */ + 0x04323232 /* DENALI_PI_42_DATA */ + 0x081c0008 /* DENALI_PI_43_DATA */ + 0x00081c00 /* DENALI_PI_44_DATA */ + 0x0000001c /* DENALI_PI_45_DATA */ + 0x0e3100c5 /* DENALI_PI_46_DATA */ + 0x0e3100c5 /* DENALI_PI_47_DATA */ + 0x0e3100c5 /* DENALI_PI_48_DATA */ + 0x00000500 /* DENALI_PI_49_DATA */ + 0x00000000 /* DENALI_PI_50_DATA */ + 0x00000000 /* DENALI_PI_51_DATA */ + 0x00000000 /* DENALI_PI_52_DATA */ + 0x00000000 /* DENALI_PI_53_DATA */ + 0x00000000 /* DENALI_PI_54_DATA */ + 0x00000000 /* DENALI_PI_55_DATA */ + 0x00000000 /* DENALI_PI_56_DATA */ + 0x00000000 /* DENALI_PI_57_DATA */ + 0x04040000 /* DENALI_PI_58_DATA */ + 0x0d000004 /* DENALI_PI_59_DATA */ + 0x00000128 /* DENALI_PI_60_DATA */ + 0x00000000 /* DENALI_PI_61_DATA */ + 0x00030003 /* DENALI_PI_62_DATA */ + 0x00000018 /* DENALI_PI_63_DATA */ + 0x00000000 /* DENALI_PI_64_DATA */ + 0x00000000 /* DENALI_PI_65_DATA */ + 0x04060002 /* DENALI_PI_66_DATA */ + 0x04010401 /* DENALI_PI_67_DATA */ + 0x00080801 /* DENALI_PI_68_DATA */ + 0x00020001 /* DENALI_PI_69_DATA */ + 0x00080004 /* DENALI_PI_70_DATA */ + 0x00000000 /* DENALI_PI_71_DATA */ + 0x04040000 /* DENALI_PI_72_DATA */ + 0x0c0c0c04 /* DENALI_PI_73_DATA */ + 0x00000000 /* DENALI_PI_74_DATA */ + 0x00000000 /* DENALI_PI_75_DATA */ + 0x00000000 /* DENALI_PI_76_DATA */ + 0x00030300 /* DENALI_PI_77_DATA */ + 0x00000014 /* DENALI_PI_78_DATA */ + 0x00000000 /* DENALI_PI_79_DATA */ + 0x01010300 /* DENALI_PI_80_DATA */ + 0x00000000 /* DENALI_PI_81_DATA */ + 0x00000000 /* DENALI_PI_82_DATA */ + 0x01000000 /* DENALI_PI_83_DATA */ + 0x00000101 /* DENALI_PI_84_DATA */ + 0x55555a5a /* DENALI_PI_85_DATA */ + 0x55555a5a /* DENALI_PI_86_DATA */ + 0x55555a5a /* DENALI_PI_87_DATA */ + 0x55555a5a /* DENALI_PI_88_DATA */ + 0x0c0c0001 /* DENALI_PI_89_DATA */ + 0x0707000c /* DENALI_PI_90_DATA */ + 0x02020007 /* DENALI_PI_91_DATA */ + 0x00000102 /* DENALI_PI_92_DATA */ + 0x00030000 /* DENALI_PI_93_DATA */ + 0x17030000 /* DENALI_PI_94_DATA */ + 0x000f0021 /* DENALI_PI_95_DATA */ + 0x000f0021 /* DENALI_PI_96_DATA */ + 0x000f0021 /* DENALI_PI_97_DATA */ + 0x00000000 /* DENALI_PI_98_DATA */ + 0x00000000 /* DENALI_PI_99_DATA */ + 0x00000100 /* DENALI_PI_100_DATA */ + 0x140a0000 /* DENALI_PI_101_DATA */ + 0x000a030a /* DENALI_PI_102_DATA */ + 0x03000a03 /* DENALI_PI_103_DATA */ + 0x010a000a /* DENALI_PI_104_DATA */ + 0x00000100 /* DENALI_PI_105_DATA */ + 0x01000000 /* DENALI_PI_106_DATA */ + 0x00000000 /* DENALI_PI_107_DATA */ + 0x00000100 /* DENALI_PI_108_DATA */ + 0x1e1a0000 /* DENALI_PI_109_DATA */ + 0x10010204 /* DENALI_PI_110_DATA */ + 0x07070705 /* DENALI_PI_111_DATA */ + 0x20000202 /* DENALI_PI_112_DATA */ + 0x00201000 /* DENALI_PI_113_DATA */ + 0x00201000 /* DENALI_PI_114_DATA */ + 0x04041000 /* DENALI_PI_115_DATA */ + 0x12120100 /* DENALI_PI_116_DATA */ + 0x00010112 /* DENALI_PI_117_DATA */ + 0x004b004a /* DENALI_PI_118_DATA */ + 0x1a030000 /* DENALI_PI_119_DATA */ + 0x0102041e /* DENALI_PI_120_DATA */ + 0x34000000 /* DENALI_PI_121_DATA */ + 0x00000000 /* DENALI_PI_122_DATA */ + 0x00000000 /* DENALI_PI_123_DATA */ + 0x00000000 /* DENALI_PI_124_DATA */ + 0x0000c300 /* DENALI_PI_125_DATA */ + 0x0001001c /* DENALI_PI_126_DATA */ + 0x004d4d07 /* DENALI_PI_127_DATA */ + 0x001c00c3 /* DENALI_PI_128_DATA */ + 0x4d070001 /* DENALI_PI_129_DATA */ + 0x0000c34d /* DENALI_PI_130_DATA */ + 0x0001001c /* DENALI_PI_131_DATA */ + 0x004d4d07 /* DENALI_PI_132_DATA */ + 0x001c00c3 /* DENALI_PI_133_DATA */ + 0x4d070001 /* DENALI_PI_134_DATA */ + 0x0000c34d /* DENALI_PI_135_DATA */ + 0x0001001c /* DENALI_PI_136_DATA */ + 0x004d4d07 /* DENALI_PI_137_DATA */ + 0x001c00c3 /* DENALI_PI_138_DATA */ + 0x4d070001 /* DENALI_PI_139_DATA */ + 0x00c3004d /* DENALI_PI_140_DATA */ + 0x0001001c /* DENALI_PI_141_DATA */ + 0x004d4d07 /* DENALI_PI_142_DATA */ + 0x001c00c3 /* DENALI_PI_143_DATA */ + 0x4d070001 /* DENALI_PI_144_DATA */ + 0x0000c34d /* DENALI_PI_145_DATA */ + 0x0001001c /* DENALI_PI_146_DATA */ + 0x004d4d07 /* DENALI_PI_147_DATA */ + 0x001c00c3 /* DENALI_PI_148_DATA */ + 0x4d070001 /* DENALI_PI_149_DATA */ + 0x0000c34d /* DENALI_PI_150_DATA */ + 0x0001001c /* DENALI_PI_151_DATA */ + 0x004d4d07 /* DENALI_PI_152_DATA */ + 0x001c00c3 /* DENALI_PI_153_DATA */ + 0x4d070001 /* DENALI_PI_154_DATA */ + 0x0100004d /* DENALI_PI_155_DATA */ + 0x00ea00ea /* DENALI_PI_156_DATA */ + 0x080400ea /* DENALI_PI_157_DATA */ + 0x0f081114 /* DENALI_PI_158_DATA */ + 0x2800fcc1 /* DENALI_PI_159_DATA */ + 0x0a0e2006 /* DENALI_PI_160_DATA */ + 0x1114080a /* DENALI_PI_161_DATA */ + 0x00000f08 /* DENALI_PI_162_DATA */ + 0x2800fcc1 /* DENALI_PI_163_DATA */ + 0x0a0e2006 /* DENALI_PI_164_DATA */ + 0x1114080a /* DENALI_PI_165_DATA */ + 0x00000f08 /* DENALI_PI_166_DATA */ + 0x2800fcc1 /* DENALI_PI_167_DATA */ + 0x0a0e2006 /* DENALI_PI_168_DATA */ + 0x0200020a /* DENALI_PI_169_DATA */ + 0x02000200 /* DENALI_PI_170_DATA */ + 0x02000200 /* DENALI_PI_171_DATA */ + 0x02000200 /* DENALI_PI_172_DATA */ + 0x02000200 /* DENALI_PI_173_DATA */ + 0x00000000 /* DENALI_PI_174_DATA */ + 0x00000000 /* DENALI_PI_175_DATA */ + 0x00000000 /* DENALI_PI_176_DATA */ + 0x00000000 /* DENALI_PI_177_DATA */ + 0x00000000 /* DENALI_PI_178_DATA */ + 0x00000000 /* DENALI_PI_179_DATA */ + 0x00000000 /* DENALI_PI_180_DATA */ + 0x00000000 /* DENALI_PI_181_DATA */ + 0x00000000 /* DENALI_PI_182_DATA */ + 0x00000000 /* DENALI_PI_183_DATA */ + 0x00000000 /* DENALI_PI_184_DATA */ + 0x00000000 /* DENALI_PI_185_DATA */ + 0x01000300 /* DENALI_PI_186_DATA */ + 0x001c6200 /* DENALI_PI_187_DATA */ + 0x00011bd4 /* DENALI_PI_188_DATA */ + 0x00001c62 /* DENALI_PI_189_DATA */ + 0x00011bd4 /* DENALI_PI_190_DATA */ + 0x00001c62 /* DENALI_PI_191_DATA */ + 0x00011bd4 /* DENALI_PI_192_DATA */ + 0x08000000 /* DENALI_PI_193_DATA */ + 0x00000100 /* DENALI_PI_194_DATA */ + 0x00000000 /* DENALI_PI_195_DATA */ + 0x00000000 /* DENALI_PI_196_DATA */ + 0x00000000 /* DENALI_PI_197_DATA */ + 0x00000000 /* DENALI_PI_198_DATA */ + 0x00000002 /* DENALI_PI_199_DATA */ + + 0x76543210 /* DENALI_PHY_00_DATA */ + 0x0004c008 /* DENALI_PHY_01_DATA */ + 0x000001a2 /* DENALI_PHY_02_DATA */ + 0x00000000 /* DENALI_PHY_03_DATA */ + 0x00000000 /* DENALI_PHY_04_DATA */ + 0x00010000 /* DENALI_PHY_05_DATA */ + 0x01665555 /* DENALI_PHY_06_DATA */ + 0x00665555 /* DENALI_PHY_07_DATA */ + 0x00010f00 /* DENALI_PHY_08_DATA */ + 0x06010200 /* DENALI_PHY_09_DATA */ + 0x00000003 /* DENALI_PHY_10_DATA */ + 0x001700c0 /* DENALI_PHY_11_DATA */ + 0x00cc0101 /* DENALI_PHY_12_DATA */ + 0x00030066 /* DENALI_PHY_13_DATA */ + 0x00000000 /* DENALI_PHY_14_DATA */ + 0x00000000 /* DENALI_PHY_15_DATA */ + 0x00000000 /* DENALI_PHY_16_DATA */ + 0x00000000 /* DENALI_PHY_17_DATA */ + 0x00000000 /* DENALI_PHY_18_DATA */ + 0x00000000 /* DENALI_PHY_19_DATA */ + 0x00000000 /* DENALI_PHY_20_DATA */ + 0x00000000 /* DENALI_PHY_21_DATA */ + 0x04080000 /* DENALI_PHY_22_DATA */ + 0x04080400 /* DENALI_PHY_23_DATA */ + 0x08000000 /* DENALI_PHY_24_DATA */ + 0x0c00c007 /* DENALI_PHY_25_DATA */ + 0x00000100 /* DENALI_PHY_26_DATA */ + 0x00000100 /* DENALI_PHY_27_DATA */ + 0x55555555 /* DENALI_PHY_28_DATA */ + 0xaaaaaaaa /* DENALI_PHY_29_DATA */ + 0x55555555 /* DENALI_PHY_30_DATA */ + 0xaaaaaaaa /* DENALI_PHY_31_DATA */ + 0x00005555 /* DENALI_PHY_32_DATA */ + 0x00000000 /* DENALI_PHY_33_DATA */ + 0x00000000 /* DENALI_PHY_34_DATA */ + 0x00000000 /* DENALI_PHY_35_DATA */ + 0x00000000 /* DENALI_PHY_36_DATA */ + 0x00000000 /* DENALI_PHY_37_DATA */ + 0x00000000 /* DENALI_PHY_38_DATA */ + 0x00000000 /* DENALI_PHY_39_DATA */ + 0x00000000 /* DENALI_PHY_40_DATA */ + 0x00000000 /* DENALI_PHY_41_DATA */ + 0x00000000 /* DENALI_PHY_42_DATA */ + 0x00000000 /* DENALI_PHY_43_DATA */ + 0x00000000 /* DENALI_PHY_44_DATA */ + 0x00000000 /* DENALI_PHY_45_DATA */ + 0x00000000 /* DENALI_PHY_46_DATA */ + 0x00000000 /* DENALI_PHY_47_DATA */ + 0x00000000 /* DENALI_PHY_48_DATA */ + 0x00000000 /* DENALI_PHY_49_DATA */ + 0x00000000 /* DENALI_PHY_50_DATA */ + 0x00000000 /* DENALI_PHY_51_DATA */ + 0x00200000 /* DENALI_PHY_52_DATA */ + 0x00000000 /* DENALI_PHY_53_DATA */ + 0x00000000 /* DENALI_PHY_54_DATA */ + 0x00000000 /* DENALI_PHY_55_DATA */ + 0x00000000 /* DENALI_PHY_56_DATA */ + 0x00000000 /* DENALI_PHY_57_DATA */ + 0x00000000 /* DENALI_PHY_58_DATA */ + 0x02700270 /* DENALI_PHY_59_DATA */ + 0x02700270 /* DENALI_PHY_60_DATA */ + 0x02700270 /* DENALI_PHY_61_DATA */ + 0x02700270 /* DENALI_PHY_62_DATA */ + 0x00000270 /* DENALI_PHY_63_DATA */ + 0x00000000 /* DENALI_PHY_64_DATA */ + 0x00000000 /* DENALI_PHY_65_DATA */ + 0x00000000 /* DENALI_PHY_66_DATA */ + 0x00000000 /* DENALI_PHY_67_DATA */ + 0x00800000 /* DENALI_PHY_68_DATA */ + 0x00800080 /* DENALI_PHY_69_DATA */ + 0x00800080 /* DENALI_PHY_70_DATA */ + 0x00800080 /* DENALI_PHY_71_DATA */ + 0x00800080 /* DENALI_PHY_72_DATA */ + 0x00800080 /* DENALI_PHY_73_DATA */ + 0x00800080 /* DENALI_PHY_74_DATA */ + 0x00800080 /* DENALI_PHY_75_DATA */ + 0x00800080 /* DENALI_PHY_76_DATA */ + 0x01a20080 /* DENALI_PHY_77_DATA */ + 0x00000003 /* DENALI_PHY_78_DATA */ + 0x00000000 /* DENALI_PHY_79_DATA */ + 0x00030000 /* DENALI_PHY_80_DATA */ + 0x00000200 /* DENALI_PHY_81_DATA */ + 0x00000000 /* DENALI_PHY_82_DATA */ + 0x51315152 /* DENALI_PHY_83_DATA */ + 0xc0013150 /* DENALI_PHY_84_DATA */ + 0x020000c0 /* DENALI_PHY_85_DATA */ + 0x00100001 /* DENALI_PHY_86_DATA */ + 0x07064208 /* DENALI_PHY_87_DATA */ + 0x000f0c18 /* DENALI_PHY_88_DATA */ + 0x01000140 /* DENALI_PHY_89_DATA */ + 0x00000c20 /* DENALI_PHY_90_DATA */ + 0x00000000 /* DENALI_PHY_91_DATA */ + 0x00000000 /* DENALI_PHY_92_DATA */ + 0x00000000 /* DENALI_PHY_93_DATA */ + 0x00000000 /* DENALI_PHY_94_DATA */ + 0x00000000 /* DENALI_PHY_95_DATA */ + 0x00000000 /* DENALI_PHY_96_DATA */ + 0x00000000 /* DENALI_PHY_97_DATA */ + 0x00000000 /* DENALI_PHY_98_DATA */ + 0x00000000 /* DENALI_PHY_99_DATA */ + 0x00000000 /* DENALI_PHY_100_DATA */ + 0x00000000 /* DENALI_PHY_101_DATA */ + 0x00000000 /* DENALI_PHY_102_DATA */ + 0x00000000 /* DENALI_PHY_103_DATA */ + 0x00000000 /* DENALI_PHY_104_DATA */ + 0x00000000 /* DENALI_PHY_105_DATA */ + 0x00000000 /* DENALI_PHY_106_DATA */ + 0x00000000 /* DENALI_PHY_107_DATA */ + 0x00000000 /* DENALI_PHY_108_DATA */ + 0x00000000 /* DENALI_PHY_109_DATA */ + 0x00000000 /* DENALI_PHY_110_DATA */ + 0x00000000 /* DENALI_PHY_111_DATA */ + 0x00000000 /* DENALI_PHY_112_DATA */ + 0x00000000 /* DENALI_PHY_113_DATA */ + 0x00000000 /* DENALI_PHY_114_DATA */ + 0x00000000 /* DENALI_PHY_115_DATA */ + 0x00000000 /* DENALI_PHY_116_DATA */ + 0x00000000 /* DENALI_PHY_117_DATA */ + 0x00000000 /* DENALI_PHY_118_DATA */ + 0x00000000 /* DENALI_PHY_119_DATA */ + 0x00000000 /* DENALI_PHY_120_DATA */ + 0x00000000 /* DENALI_PHY_121_DATA */ + 0x00000000 /* DENALI_PHY_122_DATA */ + 0x00000000 /* DENALI_PHY_123_DATA */ + 0x00000000 /* DENALI_PHY_124_DATA */ + 0x00000000 /* DENALI_PHY_125_DATA */ + 0x00000000 /* DENALI_PHY_126_DATA */ + 0x00000000 /* DENALI_PHY_127_DATA */ + 0x76543210 /* DENALI_PHY_128_DATA */ + 0x0004c008 /* DENALI_PHY_129_DATA */ + 0x000001a2 /* DENALI_PHY_130_DATA */ + 0x00000000 /* DENALI_PHY_131_DATA */ + 0x00000000 /* DENALI_PHY_132_DATA */ + 0x00010000 /* DENALI_PHY_133_DATA */ + 0x01665555 /* DENALI_PHY_134_DATA */ + 0x00665555 /* DENALI_PHY_135_DATA */ + 0x00010f00 /* DENALI_PHY_136_DATA */ + 0x06010200 /* DENALI_PHY_137_DATA */ + 0x00000003 /* DENALI_PHY_138_DATA */ + 0x001700c0 /* DENALI_PHY_139_DATA */ + 0x00cc0101 /* DENALI_PHY_140_DATA */ + 0x00030066 /* DENALI_PHY_141_DATA */ + 0x00000000 /* DENALI_PHY_142_DATA */ + 0x00000000 /* DENALI_PHY_143_DATA */ + 0x00000000 /* DENALI_PHY_144_DATA */ + 0x00000000 /* DENALI_PHY_145_DATA */ + 0x00000000 /* DENALI_PHY_146_DATA */ + 0x00000000 /* DENALI_PHY_147_DATA */ + 0x00000000 /* DENALI_PHY_148_DATA */ + 0x00000000 /* DENALI_PHY_149_DATA */ + 0x04080000 /* DENALI_PHY_150_DATA */ + 0x04080400 /* DENALI_PHY_151_DATA */ + 0x08000000 /* DENALI_PHY_152_DATA */ + 0x0c00c007 /* DENALI_PHY_153_DATA */ + 0x00000100 /* DENALI_PHY_154_DATA */ + 0x00000100 /* DENALI_PHY_155_DATA */ + 0x55555555 /* DENALI_PHY_156_DATA */ + 0xaaaaaaaa /* DENALI_PHY_157_DATA */ + 0x55555555 /* DENALI_PHY_158_DATA */ + 0xaaaaaaaa /* DENALI_PHY_159_DATA */ + 0x00005555 /* DENALI_PHY_160_DATA */ + 0x00000000 /* DENALI_PHY_161_DATA */ + 0x00000000 /* DENALI_PHY_162_DATA */ + 0x00000000 /* DENALI_PHY_163_DATA */ + 0x00000000 /* DENALI_PHY_164_DATA */ + 0x00000000 /* DENALI_PHY_165_DATA */ + 0x00000000 /* DENALI_PHY_166_DATA */ + 0x00000000 /* DENALI_PHY_167_DATA */ + 0x00000000 /* DENALI_PHY_168_DATA */ + 0x00000000 /* DENALI_PHY_169_DATA */ + 0x00000000 /* DENALI_PHY_170_DATA */ + 0x00000000 /* DENALI_PHY_171_DATA */ + 0x00000000 /* DENALI_PHY_172_DATA */ + 0x00000000 /* DENALI_PHY_173_DATA */ + 0x00000000 /* DENALI_PHY_174_DATA */ + 0x00000000 /* DENALI_PHY_175_DATA */ + 0x00000000 /* DENALI_PHY_176_DATA */ + 0x00000000 /* DENALI_PHY_177_DATA */ + 0x00000000 /* DENALI_PHY_178_DATA */ + 0x00000000 /* DENALI_PHY_179_DATA */ + 0x00200000 /* DENALI_PHY_180_DATA */ + 0x00000000 /* DENALI_PHY_181_DATA */ + 0x00000000 /* DENALI_PHY_182_DATA */ + 0x00000000 /* DENALI_PHY_183_DATA */ + 0x00000000 /* DENALI_PHY_184_DATA */ + 0x00000000 /* DENALI_PHY_185_DATA */ + 0x00000000 /* DENALI_PHY_186_DATA */ + 0x02700270 /* DENALI_PHY_187_DATA */ + 0x02700270 /* DENALI_PHY_188_DATA */ + 0x02700270 /* DENALI_PHY_189_DATA */ + 0x02700270 /* DENALI_PHY_190_DATA */ + 0x00000270 /* DENALI_PHY_191_DATA */ + 0x00000000 /* DENALI_PHY_192_DATA */ + 0x00000000 /* DENALI_PHY_193_DATA */ + 0x00000000 /* DENALI_PHY_194_DATA */ + 0x00000000 /* DENALI_PHY_195_DATA */ + 0x00800000 /* DENALI_PHY_196_DATA */ + 0x00800080 /* DENALI_PHY_197_DATA */ + 0x00800080 /* DENALI_PHY_198_DATA */ + 0x00800080 /* DENALI_PHY_199_DATA */ + 0x00800080 /* DENALI_PHY_200_DATA */ + 0x00800080 /* DENALI_PHY_201_DATA */ + 0x00800080 /* DENALI_PHY_202_DATA */ + 0x00800080 /* DENALI_PHY_203_DATA */ + 0x00800080 /* DENALI_PHY_204_DATA */ + 0x01a20080 /* DENALI_PHY_205_DATA */ + 0x00000003 /* DENALI_PHY_206_DATA */ + 0x00000000 /* DENALI_PHY_207_DATA */ + 0x00030000 /* DENALI_PHY_208_DATA */ + 0x00000200 /* DENALI_PHY_209_DATA */ + 0x00000000 /* DENALI_PHY_210_DATA */ + 0x51315152 /* DENALI_PHY_211_DATA */ + 0xc0013150 /* DENALI_PHY_212_DATA */ + 0x020000c0 /* DENALI_PHY_213_DATA */ + 0x00100001 /* DENALI_PHY_214_DATA */ + 0x07064208 /* DENALI_PHY_215_DATA */ + 0x000f0c18 /* DENALI_PHY_216_DATA */ + 0x01000140 /* DENALI_PHY_217_DATA */ + 0x00000c20 /* DENALI_PHY_218_DATA */ + 0x00000000 /* DENALI_PHY_219_DATA */ + 0x00000000 /* DENALI_PHY_220_DATA */ + 0x00000000 /* DENALI_PHY_221_DATA */ + 0x00000000 /* DENALI_PHY_222_DATA */ + 0x00000000 /* DENALI_PHY_223_DATA */ + 0x00000000 /* DENALI_PHY_224_DATA */ + 0x00000000 /* DENALI_PHY_225_DATA */ + 0x00000000 /* DENALI_PHY_226_DATA */ + 0x00000000 /* DENALI_PHY_227_DATA */ + 0x00000000 /* DENALI_PHY_228_DATA */ + 0x00000000 /* DENALI_PHY_229_DATA */ + 0x00000000 /* DENALI_PHY_230_DATA */ + 0x00000000 /* DENALI_PHY_231_DATA */ + 0x00000000 /* DENALI_PHY_232_DATA */ + 0x00000000 /* DENALI_PHY_233_DATA */ + 0x00000000 /* DENALI_PHY_234_DATA */ + 0x00000000 /* DENALI_PHY_235_DATA */ + 0x00000000 /* DENALI_PHY_236_DATA */ + 0x00000000 /* DENALI_PHY_237_DATA */ + 0x00000000 /* DENALI_PHY_238_DATA */ + 0x00000000 /* DENALI_PHY_239_DATA */ + 0x00000000 /* DENALI_PHY_240_DATA */ + 0x00000000 /* DENALI_PHY_241_DATA */ + 0x00000000 /* DENALI_PHY_242_DATA */ + 0x00000000 /* DENALI_PHY_243_DATA */ + 0x00000000 /* DENALI_PHY_244_DATA */ + 0x00000000 /* DENALI_PHY_245_DATA */ + 0x00000000 /* DENALI_PHY_246_DATA */ + 0x00000000 /* DENALI_PHY_247_DATA */ + 0x00000000 /* DENALI_PHY_248_DATA */ + 0x00000000 /* DENALI_PHY_249_DATA */ + 0x00000000 /* DENALI_PHY_250_DATA */ + 0x00000000 /* DENALI_PHY_251_DATA */ + 0x00000000 /* DENALI_PHY_252_DATA */ + 0x00000000 /* DENALI_PHY_253_DATA */ + 0x00000000 /* DENALI_PHY_254_DATA */ + 0x00000000 /* DENALI_PHY_255_DATA */ + 0x76543210 /* DENALI_PHY_256_DATA */ + 0x0004c008 /* DENALI_PHY_257_DATA */ + 0x000001a2 /* DENALI_PHY_258_DATA */ + 0x00000000 /* DENALI_PHY_259_DATA */ + 0x00000000 /* DENALI_PHY_260_DATA */ + 0x00010000 /* DENALI_PHY_261_DATA */ + 0x01665555 /* DENALI_PHY_262_DATA */ + 0x00665555 /* DENALI_PHY_263_DATA */ + 0x00010f00 /* DENALI_PHY_264_DATA */ + 0x06010200 /* DENALI_PHY_265_DATA */ + 0x00000003 /* DENALI_PHY_266_DATA */ + 0x001700c0 /* DENALI_PHY_267_DATA */ + 0x00cc0101 /* DENALI_PHY_268_DATA */ + 0x00030066 /* DENALI_PHY_269_DATA */ + 0x00000000 /* DENALI_PHY_270_DATA */ + 0x00000000 /* DENALI_PHY_271_DATA */ + 0x00000000 /* DENALI_PHY_272_DATA */ + 0x00000000 /* DENALI_PHY_273_DATA */ + 0x00000000 /* DENALI_PHY_274_DATA */ + 0x00000000 /* DENALI_PHY_275_DATA */ + 0x00000000 /* DENALI_PHY_276_DATA */ + 0x00000000 /* DENALI_PHY_277_DATA */ + 0x04080000 /* DENALI_PHY_278_DATA */ + 0x04080400 /* DENALI_PHY_279_DATA */ + 0x08000000 /* DENALI_PHY_280_DATA */ + 0x0c00c007 /* DENALI_PHY_281_DATA */ + 0x00000100 /* DENALI_PHY_282_DATA */ + 0x00000100 /* DENALI_PHY_283_DATA */ + 0x55555555 /* DENALI_PHY_284_DATA */ + 0xaaaaaaaa /* DENALI_PHY_285_DATA */ + 0x55555555 /* DENALI_PHY_286_DATA */ + 0xaaaaaaaa /* DENALI_PHY_287_DATA */ + 0x00005555 /* DENALI_PHY_288_DATA */ + 0x00000000 /* DENALI_PHY_289_DATA */ + 0x00000000 /* DENALI_PHY_290_DATA */ + 0x00000000 /* DENALI_PHY_291_DATA */ + 0x00000000 /* DENALI_PHY_292_DATA */ + 0x00000000 /* DENALI_PHY_293_DATA */ + 0x00000000 /* DENALI_PHY_294_DATA */ + 0x00000000 /* DENALI_PHY_295_DATA */ + 0x00000000 /* DENALI_PHY_296_DATA */ + 0x00000000 /* DENALI_PHY_297_DATA */ + 0x00000000 /* DENALI_PHY_298_DATA */ + 0x00000000 /* DENALI_PHY_299_DATA */ + 0x00000000 /* DENALI_PHY_300_DATA */ + 0x00000000 /* DENALI_PHY_301_DATA */ + 0x00000000 /* DENALI_PHY_302_DATA */ + 0x00000000 /* DENALI_PHY_303_DATA */ + 0x00000000 /* DENALI_PHY_304_DATA */ + 0x00000000 /* DENALI_PHY_305_DATA */ + 0x00000000 /* DENALI_PHY_306_DATA */ + 0x00000000 /* DENALI_PHY_307_DATA */ + 0x00200000 /* DENALI_PHY_308_DATA */ + 0x00000000 /* DENALI_PHY_309_DATA */ + 0x00000000 /* DENALI_PHY_310_DATA */ + 0x00000000 /* DENALI_PHY_311_DATA */ + 0x00000000 /* DENALI_PHY_312_DATA */ + 0x00000000 /* DENALI_PHY_313_DATA */ + 0x00000000 /* DENALI_PHY_314_DATA */ + 0x02700270 /* DENALI_PHY_315_DATA */ + 0x02700270 /* DENALI_PHY_316_DATA */ + 0x02700270 /* DENALI_PHY_317_DATA */ + 0x02700270 /* DENALI_PHY_318_DATA */ + 0x00000270 /* DENALI_PHY_319_DATA */ + 0x00000000 /* DENALI_PHY_320_DATA */ + 0x00000000 /* DENALI_PHY_321_DATA */ + 0x00000000 /* DENALI_PHY_322_DATA */ + 0x00000000 /* DENALI_PHY_323_DATA */ + 0x00800000 /* DENALI_PHY_324_DATA */ + 0x00800080 /* DENALI_PHY_325_DATA */ + 0x00800080 /* DENALI_PHY_326_DATA */ + 0x00800080 /* DENALI_PHY_327_DATA */ + 0x00800080 /* DENALI_PHY_328_DATA */ + 0x00800080 /* DENALI_PHY_329_DATA */ + 0x00800080 /* DENALI_PHY_330_DATA */ + 0x00800080 /* DENALI_PHY_331_DATA */ + 0x00800080 /* DENALI_PHY_332_DATA */ + 0x01a20080 /* DENALI_PHY_333_DATA */ + 0x00000003 /* DENALI_PHY_334_DATA */ + 0x00000000 /* DENALI_PHY_335_DATA */ + 0x00030000 /* DENALI_PHY_336_DATA */ + 0x00000200 /* DENALI_PHY_337_DATA */ + 0x00000000 /* DENALI_PHY_338_DATA */ + 0x51315152 /* DENALI_PHY_339_DATA */ + 0xc0013150 /* DENALI_PHY_340_DATA */ + 0x020000c0 /* DENALI_PHY_341_DATA */ + 0x00100001 /* DENALI_PHY_342_DATA */ + 0x07064208 /* DENALI_PHY_343_DATA */ + 0x000f0c18 /* DENALI_PHY_344_DATA */ + 0x01000140 /* DENALI_PHY_345_DATA */ + 0x00000c20 /* DENALI_PHY_346_DATA */ + 0x00000000 /* DENALI_PHY_347_DATA */ + 0x00000000 /* DENALI_PHY_348_DATA */ + 0x00000000 /* DENALI_PHY_349_DATA */ + 0x00000000 /* DENALI_PHY_350_DATA */ + 0x00000000 /* DENALI_PHY_351_DATA */ + 0x00000000 /* DENALI_PHY_352_DATA */ + 0x00000000 /* DENALI_PHY_353_DATA */ + 0x00000000 /* DENALI_PHY_354_DATA */ + 0x00000000 /* DENALI_PHY_355_DATA */ + 0x00000000 /* DENALI_PHY_356_DATA */ + 0x00000000 /* DENALI_PHY_357_DATA */ + 0x00000000 /* DENALI_PHY_358_DATA */ + 0x00000000 /* DENALI_PHY_359_DATA */ + 0x00000000 /* DENALI_PHY_360_DATA */ + 0x00000000 /* DENALI_PHY_361_DATA */ + 0x00000000 /* DENALI_PHY_362_DATA */ + 0x00000000 /* DENALI_PHY_363_DATA */ + 0x00000000 /* DENALI_PHY_364_DATA */ + 0x00000000 /* DENALI_PHY_365_DATA */ + 0x00000000 /* DENALI_PHY_366_DATA */ + 0x00000000 /* DENALI_PHY_367_DATA */ + 0x00000000 /* DENALI_PHY_368_DATA */ + 0x00000000 /* DENALI_PHY_369_DATA */ + 0x00000000 /* DENALI_PHY_370_DATA */ + 0x00000000 /* DENALI_PHY_371_DATA */ + 0x00000000 /* DENALI_PHY_372_DATA */ + 0x00000000 /* DENALI_PHY_373_DATA */ + 0x00000000 /* DENALI_PHY_374_DATA */ + 0x00000000 /* DENALI_PHY_375_DATA */ + 0x00000000 /* DENALI_PHY_376_DATA */ + 0x00000000 /* DENALI_PHY_377_DATA */ + 0x00000000 /* DENALI_PHY_378_DATA */ + 0x00000000 /* DENALI_PHY_379_DATA */ + 0x00000000 /* DENALI_PHY_380_DATA */ + 0x00000000 /* DENALI_PHY_381_DATA */ + 0x00000000 /* DENALI_PHY_382_DATA */ + 0x00000000 /* DENALI_PHY_383_DATA */ + 0x76543210 /* DENALI_PHY_384_DATA */ + 0x0004c008 /* DENALI_PHY_385_DATA */ + 0x000001a2 /* DENALI_PHY_386_DATA */ + 0x00000000 /* DENALI_PHY_387_DATA */ + 0x00000000 /* DENALI_PHY_388_DATA */ + 0x00010000 /* DENALI_PHY_389_DATA */ + 0x01665555 /* DENALI_PHY_390_DATA */ + 0x00665555 /* DENALI_PHY_391_DATA */ + 0x00010f00 /* DENALI_PHY_392_DATA */ + 0x06010200 /* DENALI_PHY_393_DATA */ + 0x00000003 /* DENALI_PHY_394_DATA */ + 0x001700c0 /* DENALI_PHY_395_DATA */ + 0x00cc0101 /* DENALI_PHY_396_DATA */ + 0x00030066 /* DENALI_PHY_397_DATA */ + 0x00000000 /* DENALI_PHY_398_DATA */ + 0x00000000 /* DENALI_PHY_399_DATA */ + 0x00000000 /* DENALI_PHY_400_DATA */ + 0x00000000 /* DENALI_PHY_401_DATA */ + 0x00000000 /* DENALI_PHY_402_DATA */ + 0x00000000 /* DENALI_PHY_403_DATA */ + 0x00000000 /* DENALI_PHY_404_DATA */ + 0x00000000 /* DENALI_PHY_405_DATA */ + 0x04080000 /* DENALI_PHY_406_DATA */ + 0x04080400 /* DENALI_PHY_407_DATA */ + 0x08000000 /* DENALI_PHY_408_DATA */ + 0x0c00c007 /* DENALI_PHY_409_DATA */ + 0x00000100 /* DENALI_PHY_410_DATA */ + 0x00000100 /* DENALI_PHY_411_DATA */ + 0x55555555 /* DENALI_PHY_412_DATA */ + 0xaaaaaaaa /* DENALI_PHY_413_DATA */ + 0x55555555 /* DENALI_PHY_414_DATA */ + 0xaaaaaaaa /* DENALI_PHY_415_DATA */ + 0x00005555 /* DENALI_PHY_416_DATA */ + 0x00000000 /* DENALI_PHY_417_DATA */ + 0x00000000 /* DENALI_PHY_418_DATA */ + 0x00000000 /* DENALI_PHY_419_DATA */ + 0x00000000 /* DENALI_PHY_420_DATA */ + 0x00000000 /* DENALI_PHY_421_DATA */ + 0x00000000 /* DENALI_PHY_422_DATA */ + 0x00000000 /* DENALI_PHY_423_DATA */ + 0x00000000 /* DENALI_PHY_424_DATA */ + 0x00000000 /* DENALI_PHY_425_DATA */ + 0x00000000 /* DENALI_PHY_426_DATA */ + 0x00000000 /* DENALI_PHY_427_DATA */ + 0x00000000 /* DENALI_PHY_428_DATA */ + 0x00000000 /* DENALI_PHY_429_DATA */ + 0x00000000 /* DENALI_PHY_430_DATA */ + 0x00000000 /* DENALI_PHY_431_DATA */ + 0x00000000 /* DENALI_PHY_432_DATA */ + 0x00000000 /* DENALI_PHY_433_DATA */ + 0x00000000 /* DENALI_PHY_434_DATA */ + 0x00000000 /* DENALI_PHY_435_DATA */ + 0x00200000 /* DENALI_PHY_436_DATA */ + 0x00000000 /* DENALI_PHY_437_DATA */ + 0x00000000 /* DENALI_PHY_438_DATA */ + 0x00000000 /* DENALI_PHY_439_DATA */ + 0x00000000 /* DENALI_PHY_440_DATA */ + 0x00000000 /* DENALI_PHY_441_DATA */ + 0x00000000 /* DENALI_PHY_442_DATA */ + 0x02700270 /* DENALI_PHY_443_DATA */ + 0x02700270 /* DENALI_PHY_444_DATA */ + 0x02700270 /* DENALI_PHY_445_DATA */ + 0x02700270 /* DENALI_PHY_446_DATA */ + 0x00000270 /* DENALI_PHY_447_DATA */ + 0x00000000 /* DENALI_PHY_448_DATA */ + 0x00000000 /* DENALI_PHY_449_DATA */ + 0x00000000 /* DENALI_PHY_450_DATA */ + 0x00000000 /* DENALI_PHY_451_DATA */ + 0x00800000 /* DENALI_PHY_452_DATA */ + 0x00800080 /* DENALI_PHY_453_DATA */ + 0x00800080 /* DENALI_PHY_454_DATA */ + 0x00800080 /* DENALI_PHY_455_DATA */ + 0x00800080 /* DENALI_PHY_456_DATA */ + 0x00800080 /* DENALI_PHY_457_DATA */ + 0x00800080 /* DENALI_PHY_458_DATA */ + 0x00800080 /* DENALI_PHY_459_DATA */ + 0x00800080 /* DENALI_PHY_460_DATA */ + 0x01a20080 /* DENALI_PHY_461_DATA */ + 0x00000003 /* DENALI_PHY_462_DATA */ + 0x00000000 /* DENALI_PHY_463_DATA */ + 0x00030000 /* DENALI_PHY_464_DATA */ + 0x00000200 /* DENALI_PHY_465_DATA */ + 0x00000000 /* DENALI_PHY_466_DATA */ + 0x51315152 /* DENALI_PHY_467_DATA */ + 0xc0013150 /* DENALI_PHY_468_DATA */ + 0x020000c0 /* DENALI_PHY_469_DATA */ + 0x00100001 /* DENALI_PHY_470_DATA */ + 0x07064208 /* DENALI_PHY_471_DATA */ + 0x000f0c18 /* DENALI_PHY_472_DATA */ + 0x01000140 /* DENALI_PHY_473_DATA */ + 0x00000c20 /* DENALI_PHY_474_DATA */ + 0x00000000 /* DENALI_PHY_475_DATA */ + 0x00000000 /* DENALI_PHY_476_DATA */ + 0x00000000 /* DENALI_PHY_477_DATA */ + 0x00000000 /* DENALI_PHY_478_DATA */ + 0x00000000 /* DENALI_PHY_479_DATA */ + 0x00000000 /* DENALI_PHY_480_DATA */ + 0x00000000 /* DENALI_PHY_481_DATA */ + 0x00000000 /* DENALI_PHY_482_DATA */ + 0x00000000 /* DENALI_PHY_483_DATA */ + 0x00000000 /* DENALI_PHY_484_DATA */ + 0x00000000 /* DENALI_PHY_485_DATA */ + 0x00000000 /* DENALI_PHY_486_DATA */ + 0x00000000 /* DENALI_PHY_487_DATA */ + 0x00000000 /* DENALI_PHY_488_DATA */ + 0x00000000 /* DENALI_PHY_489_DATA */ + 0x00000000 /* DENALI_PHY_490_DATA */ + 0x00000000 /* DENALI_PHY_491_DATA */ + 0x00000000 /* DENALI_PHY_492_DATA */ + 0x00000000 /* DENALI_PHY_493_DATA */ + 0x00000000 /* DENALI_PHY_494_DATA */ + 0x00000000 /* DENALI_PHY_495_DATA */ + 0x00000000 /* DENALI_PHY_496_DATA */ + 0x00000000 /* DENALI_PHY_497_DATA */ + 0x00000000 /* DENALI_PHY_498_DATA */ + 0x00000000 /* DENALI_PHY_499_DATA */ + 0x00000000 /* DENALI_PHY_500_DATA */ + 0x00000000 /* DENALI_PHY_501_DATA */ + 0x00000000 /* DENALI_PHY_502_DATA */ + 0x00000000 /* DENALI_PHY_503_DATA */ + 0x00000000 /* DENALI_PHY_504_DATA */ + 0x00000000 /* DENALI_PHY_505_DATA */ + 0x00000000 /* DENALI_PHY_506_DATA */ + 0x00000000 /* DENALI_PHY_507_DATA */ + 0x00000000 /* DENALI_PHY_508_DATA */ + 0x00000000 /* DENALI_PHY_509_DATA */ + 0x00000000 /* DENALI_PHY_510_DATA */ + 0x00000000 /* DENALI_PHY_511_DATA */ + 0x00000000 /* DENALI_PHY_512_DATA */ + 0x00800000 /* DENALI_PHY_513_DATA */ + 0x00000000 /* DENALI_PHY_514_DATA */ + 0x00000000 /* DENALI_PHY_515_DATA */ + 0x00000000 /* DENALI_PHY_516_DATA */ + 0x00000000 /* DENALI_PHY_517_DATA */ + 0x00000000 /* DENALI_PHY_518_DATA */ + 0x00000001 /* DENALI_PHY_519_DATA */ + 0x00000000 /* DENALI_PHY_520_DATA */ + 0x00000000 /* DENALI_PHY_521_DATA */ + 0x00000000 /* DENALI_PHY_522_DATA */ + 0x00400320 /* DENALI_PHY_523_DATA */ + 0x00000040 /* DENALI_PHY_524_DATA */ + 0x00806420 /* DENALI_PHY_525_DATA */ + 0x00917531 /* DENALI_PHY_526_DATA */ + 0x00806420 /* DENALI_PHY_527_DATA */ + 0x01917531 /* DENALI_PHY_528_DATA */ + 0x02020003 /* DENALI_PHY_529_DATA */ + 0x00000000 /* DENALI_PHY_530_DATA */ + 0x00000000 /* DENALI_PHY_531_DATA */ + 0x00000000 /* DENALI_PHY_532_DATA */ + 0x000fffff /* DENALI_PHY_533_DATA */ + 0x00000000 /* DENALI_PHY_534_DATA */ + 0x000556aa /* DENALI_PHY_535_DATA */ + 0x000aaaaa /* DENALI_PHY_536_DATA */ + 0x000b3133 /* DENALI_PHY_537_DATA */ + 0x0004cd33 /* DENALI_PHY_538_DATA */ + 0x0004cecc /* DENALI_PHY_539_DATA */ + 0x000b32cc /* DENALI_PHY_540_DATA */ + 0x0a418820 /* DENALI_PHY_541_DATA */ + 0x103f0000 /* DENALI_PHY_542_DATA */ + 0x0000003f /* DENALI_PHY_543_DATA */ + 0x00038055 /* DENALI_PHY_544_DATA */ + 0x03800380 /* DENALI_PHY_545_DATA */ + 0x03800380 /* DENALI_PHY_546_DATA */ + 0x00000380 /* DENALI_PHY_547_DATA */ + 0x42080010 /* DENALI_PHY_548_DATA */ + 0x00000003 /* DENALI_PHY_549_DATA */ + 0x00000000 /* DENALI_PHY_550_DATA */ + 0x00000000 /* DENALI_PHY_551_DATA */ + 0x00000000 /* DENALI_PHY_552_DATA */ + 0x00000000 /* DENALI_PHY_553_DATA */ + 0x00000000 /* DENALI_PHY_554_DATA */ + 0x00000000 /* DENALI_PHY_555_DATA */ + 0x00000000 /* DENALI_PHY_556_DATA */ + 0x00000000 /* DENALI_PHY_557_DATA */ + 0x00000000 /* DENALI_PHY_558_DATA */ + 0x00000000 /* DENALI_PHY_559_DATA */ + 0x00000000 /* DENALI_PHY_560_DATA */ + 0x00000000 /* DENALI_PHY_561_DATA */ + 0x00000000 /* DENALI_PHY_562_DATA */ + 0x00000000 /* DENALI_PHY_563_DATA */ + 0x00000000 /* DENALI_PHY_564_DATA */ + 0x00000000 /* DENALI_PHY_565_DATA */ + 0x00000000 /* DENALI_PHY_566_DATA */ + 0x00000000 /* DENALI_PHY_567_DATA */ + 0x00000000 /* DENALI_PHY_568_DATA */ + 0x00000000 /* DENALI_PHY_569_DATA */ + 0x00000000 /* DENALI_PHY_570_DATA */ + 0x00000000 /* DENALI_PHY_571_DATA */ + 0x00000000 /* DENALI_PHY_572_DATA */ + 0x00000000 /* DENALI_PHY_573_DATA */ + 0x00000000 /* DENALI_PHY_574_DATA */ + 0x00000000 /* DENALI_PHY_575_DATA */ + 0x00000000 /* DENALI_PHY_576_DATA */ + 0x00000000 /* DENALI_PHY_577_DATA */ + 0x00000000 /* DENALI_PHY_578_DATA */ + 0x00000000 /* DENALI_PHY_579_DATA */ + 0x00000000 /* DENALI_PHY_580_DATA */ + 0x00000000 /* DENALI_PHY_581_DATA */ + 0x00000000 /* DENALI_PHY_582_DATA */ + 0x00000000 /* DENALI_PHY_583_DATA */ + 0x00000000 /* DENALI_PHY_584_DATA */ + 0x00000000 /* DENALI_PHY_585_DATA */ + 0x00000000 /* DENALI_PHY_586_DATA */ + 0x00000000 /* DENALI_PHY_587_DATA */ + 0x00000000 /* DENALI_PHY_588_DATA */ + 0x00000000 /* DENALI_PHY_589_DATA */ + 0x00000000 /* DENALI_PHY_590_DATA */ + 0x00000000 /* DENALI_PHY_591_DATA */ + 0x00000000 /* DENALI_PHY_592_DATA */ + 0x00000000 /* DENALI_PHY_593_DATA */ + 0x00000000 /* DENALI_PHY_594_DATA */ + 0x00000000 /* DENALI_PHY_595_DATA */ + 0x00000000 /* DENALI_PHY_596_DATA */ + 0x00000000 /* DENALI_PHY_597_DATA */ + 0x00000000 /* DENALI_PHY_598_DATA */ + 0x00000000 /* DENALI_PHY_599_DATA */ + 0x00000000 /* DENALI_PHY_600_DATA */ + 0x00000000 /* DENALI_PHY_601_DATA */ + 0x00000000 /* DENALI_PHY_602_DATA */ + 0x00000000 /* DENALI_PHY_603_DATA */ + 0x00000000 /* DENALI_PHY_604_DATA */ + 0x00000000 /* DENALI_PHY_605_DATA */ + 0x00000000 /* DENALI_PHY_606_DATA */ + 0x00000000 /* DENALI_PHY_607_DATA */ + 0x00000000 /* DENALI_PHY_608_DATA */ + 0x00000000 /* DENALI_PHY_609_DATA */ + 0x00000000 /* DENALI_PHY_610_DATA */ + 0x00000000 /* DENALI_PHY_611_DATA */ + 0x00000000 /* DENALI_PHY_612_DATA */ + 0x00000000 /* DENALI_PHY_613_DATA */ + 0x00000000 /* DENALI_PHY_614_DATA */ + 0x00000000 /* DENALI_PHY_615_DATA */ + 0x00000000 /* DENALI_PHY_616_DATA */ + 0x00000000 /* DENALI_PHY_617_DATA */ + 0x00000000 /* DENALI_PHY_618_DATA */ + 0x00000000 /* DENALI_PHY_619_DATA */ + 0x00000000 /* DENALI_PHY_620_DATA */ + 0x00000000 /* DENALI_PHY_621_DATA */ + 0x00000000 /* DENALI_PHY_622_DATA */ + 0x00000000 /* DENALI_PHY_623_DATA */ + 0x00000000 /* DENALI_PHY_624_DATA */ + 0x00000000 /* DENALI_PHY_625_DATA */ + 0x00000000 /* DENALI_PHY_626_DATA */ + 0x00000000 /* DENALI_PHY_627_DATA */ + 0x00000000 /* DENALI_PHY_628_DATA */ + 0x00000000 /* DENALI_PHY_629_DATA */ + 0x00000000 /* DENALI_PHY_630_DATA */ + 0x00000000 /* DENALI_PHY_631_DATA */ + 0x00000000 /* DENALI_PHY_632_DATA */ + 0x00000000 /* DENALI_PHY_633_DATA */ + 0x00000000 /* DENALI_PHY_634_DATA */ + 0x00000000 /* DENALI_PHY_635_DATA */ + 0x00000000 /* DENALI_PHY_636_DATA */ + 0x00000000 /* DENALI_PHY_637_DATA */ + 0x00000000 /* DENALI_PHY_638_DATA */ + 0x00000000 /* DENALI_PHY_639_DATA */ + 0x00000000 /* DENALI_PHY_640_DATA */ + 0x00800000 /* DENALI_PHY_641_DATA */ + 0x00000000 /* DENALI_PHY_642_DATA */ + 0x00000000 /* DENALI_PHY_643_DATA */ + 0x00000000 /* DENALI_PHY_644_DATA */ + 0x00000000 /* DENALI_PHY_645_DATA */ + 0x00000000 /* DENALI_PHY_646_DATA */ + 0x00000001 /* DENALI_PHY_647_DATA */ + 0x00000000 /* DENALI_PHY_648_DATA */ + 0x00000000 /* DENALI_PHY_649_DATA */ + 0x00000000 /* DENALI_PHY_650_DATA */ + 0x00400320 /* DENALI_PHY_651_DATA */ + 0x00000040 /* DENALI_PHY_652_DATA */ + 0x00008eca /* DENALI_PHY_653_DATA */ + 0x00009fdb /* DENALI_PHY_654_DATA */ + 0x00008eca /* DENALI_PHY_655_DATA */ + 0x01009fdb /* DENALI_PHY_656_DATA */ + 0x02020003 /* DENALI_PHY_657_DATA */ + 0x00000000 /* DENALI_PHY_658_DATA */ + 0x00000000 /* DENALI_PHY_659_DATA */ + 0x00000000 /* DENALI_PHY_660_DATA */ + 0x000fffff /* DENALI_PHY_661_DATA */ + 0x00000000 /* DENALI_PHY_662_DATA */ + 0x000556aa /* DENALI_PHY_663_DATA */ + 0x000aaaaa /* DENALI_PHY_664_DATA */ + 0x000b3133 /* DENALI_PHY_665_DATA */ + 0x0004cd33 /* DENALI_PHY_666_DATA */ + 0x0004cecc /* DENALI_PHY_667_DATA */ + 0x000b32cc /* DENALI_PHY_668_DATA */ + 0x0004a0e6 /* DENALI_PHY_669_DATA */ + 0x080f0000 /* DENALI_PHY_670_DATA */ + 0x0000000f /* DENALI_PHY_671_DATA */ + 0x00038055 /* DENALI_PHY_672_DATA */ + 0x03800380 /* DENALI_PHY_673_DATA */ + 0x03800380 /* DENALI_PHY_674_DATA */ + 0x00000380 /* DENALI_PHY_675_DATA */ + 0x42080010 /* DENALI_PHY_676_DATA */ + 0x00000003 /* DENALI_PHY_677_DATA */ + 0x00000000 /* DENALI_PHY_678_DATA */ + 0x00000000 /* DENALI_PHY_679_DATA */ + 0x00000000 /* DENALI_PHY_680_DATA */ + 0x00000000 /* DENALI_PHY_681_DATA */ + 0x00000000 /* DENALI_PHY_682_DATA */ + 0x00000000 /* DENALI_PHY_683_DATA */ + 0x00000000 /* DENALI_PHY_684_DATA */ + 0x00000000 /* DENALI_PHY_685_DATA */ + 0x00000000 /* DENALI_PHY_686_DATA */ + 0x00000000 /* DENALI_PHY_687_DATA */ + 0x00000000 /* DENALI_PHY_688_DATA */ + 0x00000000 /* DENALI_PHY_689_DATA */ + 0x00000000 /* DENALI_PHY_690_DATA */ + 0x00000000 /* DENALI_PHY_691_DATA */ + 0x00000000 /* DENALI_PHY_692_DATA */ + 0x00000000 /* DENALI_PHY_693_DATA */ + 0x00000000 /* DENALI_PHY_694_DATA */ + 0x00000000 /* DENALI_PHY_695_DATA */ + 0x00000000 /* DENALI_PHY_696_DATA */ + 0x00000000 /* DENALI_PHY_697_DATA */ + 0x00000000 /* DENALI_PHY_698_DATA */ + 0x00000000 /* DENALI_PHY_699_DATA */ + 0x00000000 /* DENALI_PHY_700_DATA */ + 0x00000000 /* DENALI_PHY_701_DATA */ + 0x00000000 /* DENALI_PHY_702_DATA */ + 0x00000000 /* DENALI_PHY_703_DATA */ + 0x00000000 /* DENALI_PHY_704_DATA */ + 0x00000000 /* DENALI_PHY_705_DATA */ + 0x00000000 /* DENALI_PHY_706_DATA */ + 0x00000000 /* DENALI_PHY_707_DATA */ + 0x00000000 /* DENALI_PHY_708_DATA */ + 0x00000000 /* DENALI_PHY_709_DATA */ + 0x00000000 /* DENALI_PHY_710_DATA */ + 0x00000000 /* DENALI_PHY_711_DATA */ + 0x00000000 /* DENALI_PHY_712_DATA */ + 0x00000000 /* DENALI_PHY_713_DATA */ + 0x00000000 /* DENALI_PHY_714_DATA */ + 0x00000000 /* DENALI_PHY_715_DATA */ + 0x00000000 /* DENALI_PHY_716_DATA */ + 0x00000000 /* DENALI_PHY_717_DATA */ + 0x00000000 /* DENALI_PHY_718_DATA */ + 0x00000000 /* DENALI_PHY_719_DATA */ + 0x00000000 /* DENALI_PHY_720_DATA */ + 0x00000000 /* DENALI_PHY_721_DATA */ + 0x00000000 /* DENALI_PHY_722_DATA */ + 0x00000000 /* DENALI_PHY_723_DATA */ + 0x00000000 /* DENALI_PHY_724_DATA */ + 0x00000000 /* DENALI_PHY_725_DATA */ + 0x00000000 /* DENALI_PHY_726_DATA */ + 0x00000000 /* DENALI_PHY_727_DATA */ + 0x00000000 /* DENALI_PHY_728_DATA */ + 0x00000000 /* DENALI_PHY_729_DATA */ + 0x00000000 /* DENALI_PHY_730_DATA */ + 0x00000000 /* DENALI_PHY_731_DATA */ + 0x00000000 /* DENALI_PHY_732_DATA */ + 0x00000000 /* DENALI_PHY_733_DATA */ + 0x00000000 /* DENALI_PHY_734_DATA */ + 0x00000000 /* DENALI_PHY_735_DATA */ + 0x00000000 /* DENALI_PHY_736_DATA */ + 0x00000000 /* DENALI_PHY_737_DATA */ + 0x00000000 /* DENALI_PHY_738_DATA */ + 0x00000000 /* DENALI_PHY_739_DATA */ + 0x00000000 /* DENALI_PHY_740_DATA */ + 0x00000000 /* DENALI_PHY_741_DATA */ + 0x00000000 /* DENALI_PHY_742_DATA */ + 0x00000000 /* DENALI_PHY_743_DATA */ + 0x00000000 /* DENALI_PHY_744_DATA */ + 0x00000000 /* DENALI_PHY_745_DATA */ + 0x00000000 /* DENALI_PHY_746_DATA */ + 0x00000000 /* DENALI_PHY_747_DATA */ + 0x00000000 /* DENALI_PHY_748_DATA */ + 0x00000000 /* DENALI_PHY_749_DATA */ + 0x00000000 /* DENALI_PHY_750_DATA */ + 0x00000000 /* DENALI_PHY_751_DATA */ + 0x00000000 /* DENALI_PHY_752_DATA */ + 0x00000000 /* DENALI_PHY_753_DATA */ + 0x00000000 /* DENALI_PHY_754_DATA */ + 0x00000000 /* DENALI_PHY_755_DATA */ + 0x00000000 /* DENALI_PHY_756_DATA */ + 0x00000000 /* DENALI_PHY_757_DATA */ + 0x00000000 /* DENALI_PHY_758_DATA */ + 0x00000000 /* DENALI_PHY_759_DATA */ + 0x00000000 /* DENALI_PHY_760_DATA */ + 0x00000000 /* DENALI_PHY_761_DATA */ + 0x00000000 /* DENALI_PHY_762_DATA */ + 0x00000000 /* DENALI_PHY_763_DATA */ + 0x00000000 /* DENALI_PHY_764_DATA */ + 0x00000000 /* DENALI_PHY_765_DATA */ + 0x00000000 /* DENALI_PHY_766_DATA */ + 0x00000000 /* DENALI_PHY_767_DATA */ + 0x00000000 /* DENALI_PHY_768_DATA */ + 0x00800000 /* DENALI_PHY_769_DATA */ + 0x00000000 /* DENALI_PHY_770_DATA */ + 0x00000000 /* DENALI_PHY_771_DATA */ + 0x00000000 /* DENALI_PHY_772_DATA */ + 0x00000000 /* DENALI_PHY_773_DATA */ + 0x00000000 /* DENALI_PHY_774_DATA */ + 0x00000001 /* DENALI_PHY_775_DATA */ + 0x00000000 /* DENALI_PHY_776_DATA */ + 0x00000000 /* DENALI_PHY_777_DATA */ + 0x00000000 /* DENALI_PHY_778_DATA */ + 0x00400320 /* DENALI_PHY_779_DATA */ + 0x00000040 /* DENALI_PHY_780_DATA */ + 0x00008eca /* DENALI_PHY_781_DATA */ + 0x00009fdb /* DENALI_PHY_782_DATA */ + 0x00008eca /* DENALI_PHY_783_DATA */ + 0x01009fdb /* DENALI_PHY_784_DATA */ + 0x02020003 /* DENALI_PHY_785_DATA */ + 0x00000000 /* DENALI_PHY_786_DATA */ + 0x00000000 /* DENALI_PHY_787_DATA */ + 0x00000000 /* DENALI_PHY_788_DATA */ + 0x000fffff /* DENALI_PHY_789_DATA */ + 0x00000000 /* DENALI_PHY_790_DATA */ + 0x000556aa /* DENALI_PHY_791_DATA */ + 0x000aaaaa /* DENALI_PHY_792_DATA */ + 0x000b3133 /* DENALI_PHY_793_DATA */ + 0x0004cd33 /* DENALI_PHY_794_DATA */ + 0x0004cecc /* DENALI_PHY_795_DATA */ + 0x000b32cc /* DENALI_PHY_796_DATA */ + 0x1ee6b16a /* DENALI_PHY_797_DATA */ + 0x10000000 /* DENALI_PHY_798_DATA */ + 0x00000000 /* DENALI_PHY_799_DATA */ + 0x00038055 /* DENALI_PHY_800_DATA */ + 0x03800380 /* DENALI_PHY_801_DATA */ + 0x03800380 /* DENALI_PHY_802_DATA */ + 0x00000380 /* DENALI_PHY_803_DATA */ + 0x42080010 /* DENALI_PHY_804_DATA */ + 0x00000003 /* DENALI_PHY_805_DATA */ + 0x00000000 /* DENALI_PHY_806_DATA */ + 0x00000000 /* DENALI_PHY_807_DATA */ + 0x00000000 /* DENALI_PHY_808_DATA */ + 0x00000000 /* DENALI_PHY_809_DATA */ + 0x00000000 /* DENALI_PHY_810_DATA */ + 0x00000000 /* DENALI_PHY_811_DATA */ + 0x00000000 /* DENALI_PHY_812_DATA */ + 0x00000000 /* DENALI_PHY_813_DATA */ + 0x00000000 /* DENALI_PHY_814_DATA */ + 0x00000000 /* DENALI_PHY_815_DATA */ + 0x00000000 /* DENALI_PHY_816_DATA */ + 0x00000000 /* DENALI_PHY_817_DATA */ + 0x00000000 /* DENALI_PHY_818_DATA */ + 0x00000000 /* DENALI_PHY_819_DATA */ + 0x00000000 /* DENALI_PHY_820_DATA */ + 0x00000000 /* DENALI_PHY_821_DATA */ + 0x00000000 /* DENALI_PHY_822_DATA */ + 0x00000000 /* DENALI_PHY_823_DATA */ + 0x00000000 /* DENALI_PHY_824_DATA */ + 0x00000000 /* DENALI_PHY_825_DATA */ + 0x00000000 /* DENALI_PHY_826_DATA */ + 0x00000000 /* DENALI_PHY_827_DATA */ + 0x00000000 /* DENALI_PHY_828_DATA */ + 0x00000000 /* DENALI_PHY_829_DATA */ + 0x00000000 /* DENALI_PHY_830_DATA */ + 0x00000000 /* DENALI_PHY_831_DATA */ + 0x00000000 /* DENALI_PHY_832_DATA */ + 0x00000000 /* DENALI_PHY_833_DATA */ + 0x00000000 /* DENALI_PHY_834_DATA */ + 0x00000000 /* DENALI_PHY_835_DATA */ + 0x00000000 /* DENALI_PHY_836_DATA */ + 0x00000000 /* DENALI_PHY_837_DATA */ + 0x00000000 /* DENALI_PHY_838_DATA */ + 0x00000000 /* DENALI_PHY_839_DATA */ + 0x00000000 /* DENALI_PHY_840_DATA */ + 0x00000000 /* DENALI_PHY_841_DATA */ + 0x00000000 /* DENALI_PHY_842_DATA */ + 0x00000000 /* DENALI_PHY_843_DATA */ + 0x00000000 /* DENALI_PHY_844_DATA */ + 0x00000000 /* DENALI_PHY_845_DATA */ + 0x00000000 /* DENALI_PHY_846_DATA */ + 0x00000000 /* DENALI_PHY_847_DATA */ + 0x00000000 /* DENALI_PHY_848_DATA */ + 0x00000000 /* DENALI_PHY_849_DATA */ + 0x00000000 /* DENALI_PHY_850_DATA */ + 0x00000000 /* DENALI_PHY_851_DATA */ + 0x00000000 /* DENALI_PHY_852_DATA */ + 0x00000000 /* DENALI_PHY_853_DATA */ + 0x00000000 /* DENALI_PHY_854_DATA */ + 0x00000000 /* DENALI_PHY_855_DATA */ + 0x00000000 /* DENALI_PHY_856_DATA */ + 0x00000000 /* DENALI_PHY_857_DATA */ + 0x00000000 /* DENALI_PHY_858_DATA */ + 0x00000000 /* DENALI_PHY_859_DATA */ + 0x00000000 /* DENALI_PHY_860_DATA */ + 0x00000000 /* DENALI_PHY_861_DATA */ + 0x00000000 /* DENALI_PHY_862_DATA */ + 0x00000000 /* DENALI_PHY_863_DATA */ + 0x00000000 /* DENALI_PHY_864_DATA */ + 0x00000000 /* DENALI_PHY_865_DATA */ + 0x00000000 /* DENALI_PHY_866_DATA */ + 0x00000000 /* DENALI_PHY_867_DATA */ + 0x00000000 /* DENALI_PHY_868_DATA */ + 0x00000000 /* DENALI_PHY_869_DATA */ + 0x00000000 /* DENALI_PHY_870_DATA */ + 0x00000000 /* DENALI_PHY_871_DATA */ + 0x00000000 /* DENALI_PHY_872_DATA */ + 0x00000000 /* DENALI_PHY_873_DATA */ + 0x00000000 /* DENALI_PHY_874_DATA */ + 0x00000000 /* DENALI_PHY_875_DATA */ + 0x00000000 /* DENALI_PHY_876_DATA */ + 0x00000000 /* DENALI_PHY_877_DATA */ + 0x00000000 /* DENALI_PHY_878_DATA */ + 0x00000000 /* DENALI_PHY_879_DATA */ + 0x00000000 /* DENALI_PHY_880_DATA */ + 0x00000000 /* DENALI_PHY_881_DATA */ + 0x00000000 /* DENALI_PHY_882_DATA */ + 0x00000000 /* DENALI_PHY_883_DATA */ + 0x00000000 /* DENALI_PHY_884_DATA */ + 0x00000000 /* DENALI_PHY_885_DATA */ + 0x00000000 /* DENALI_PHY_886_DATA */ + 0x00000000 /* DENALI_PHY_887_DATA */ + 0x00000000 /* DENALI_PHY_888_DATA */ + 0x00000000 /* DENALI_PHY_889_DATA */ + 0x00000000 /* DENALI_PHY_890_DATA */ + 0x00000000 /* DENALI_PHY_891_DATA */ + 0x00000000 /* DENALI_PHY_892_DATA */ + 0x00000000 /* DENALI_PHY_893_DATA */ + 0x00000000 /* DENALI_PHY_894_DATA */ + 0x00000000 /* DENALI_PHY_895_DATA */ + 0x00000001 /* DENALI_PHY_896_DATA */ + 0x00000000 /* DENALI_PHY_897_DATA */ + 0x01000005 /* DENALI_PHY_898_DATA */ + 0x04000f00 /* DENALI_PHY_899_DATA */ + 0x00020040 /* DENALI_PHY_900_DATA */ + 0x00020055 /* DENALI_PHY_901_DATA */ + 0x00000000 /* DENALI_PHY_902_DATA */ + 0x00000000 /* DENALI_PHY_903_DATA */ + 0x00000000 /* DENALI_PHY_904_DATA */ + 0x00000050 /* DENALI_PHY_905_DATA */ + 0x00000000 /* DENALI_PHY_906_DATA */ + 0x00010100 /* DENALI_PHY_907_DATA */ + 0x00000601 /* DENALI_PHY_908_DATA */ + 0x00000000 /* DENALI_PHY_909_DATA */ + 0x00006400 /* DENALI_PHY_910_DATA */ + 0x01221102 /* DENALI_PHY_911_DATA */ + 0x00000000 /* DENALI_PHY_912_DATA */ + 0x00051f00 /* DENALI_PHY_913_DATA */ + 0x051f051f /* DENALI_PHY_914_DATA */ + 0x051f051f /* DENALI_PHY_915_DATA */ + 0x00030003 /* DENALI_PHY_916_DATA */ + 0x03000300 /* DENALI_PHY_917_DATA */ + 0x00000300 /* DENALI_PHY_918_DATA */ + 0x01221102 /* DENALI_PHY_919_DATA */ + 0x00000000 /* DENALI_PHY_920_DATA */ + 0x00000000 /* DENALI_PHY_921_DATA */ + 0x04020000 /* DENALI_PHY_922_DATA */ + 0x00000001 /* DENALI_PHY_923_DATA */ + 0x00000011 /* DENALI_PHY_924_DATA */ + 0x00000011 /* DENALI_PHY_925_DATA */ + 0x00000400 /* DENALI_PHY_926_DATA */ + 0x00000000 /* DENALI_PHY_927_DATA */ + 0x00000011 /* DENALI_PHY_928_DATA */ + 0x00000011 /* DENALI_PHY_929_DATA */ + 0x00004410 /* DENALI_PHY_930_DATA */ + 0x00004410 /* DENALI_PHY_931_DATA */ + 0x00004410 /* DENALI_PHY_932_DATA */ + 0x00004410 /* DENALI_PHY_933_DATA */ + 0x00004410 /* DENALI_PHY_934_DATA */ + 0x00000011 /* DENALI_PHY_935_DATA */ + 0x00004410 /* DENALI_PHY_936_DATA */ + 0x00000011 /* DENALI_PHY_937_DATA */ + 0x00004410 /* DENALI_PHY_938_DATA */ + 0x00000011 /* DENALI_PHY_939_DATA */ + 0x00004410 /* DENALI_PHY_940_DATA */ + 0x00000000 /* DENALI_PHY_941_DATA */ + 0x00000000 /* DENALI_PHY_942_DATA */ + 0x00000000 /* DENALI_PHY_943_DATA */ + 0x04000000 /* DENALI_PHY_944_DATA */ + 0x00000000 /* DENALI_PHY_945_DATA */ + 0x00000000 /* DENALI_PHY_946_DATA */ + 0x00000508 /* DENALI_PHY_947_DATA */ + 0x00000000 /* DENALI_PHY_948_DATA */ + 0x00000000 /* DENALI_PHY_949_DATA */ + 0x00000000 /* DENALI_PHY_950_DATA */ + 0x00000000 /* DENALI_PHY_951_DATA */ + 0x00000000 /* DENALI_PHY_952_DATA */ + 0x00000000 /* DENALI_PHY_953_DATA */ + 0xe4000000 /* DENALI_PHY_954_DATA */ + 0x00000000 /* DENALI_PHY_955_DATA */ + 0x00000000 /* DENALI_PHY_956_DATA */ + 0x01010000 /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + >; +}; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 21f156782f..b53e41b4dc 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -349,45 +349,105 @@ status = "disabled"; }; - dwc3_typec0: usb@fe800000 { - compatible = "rockchip,rk3399-xhci"; - reg = <0x0 0xfe800000 0x0 0x100000>; + usbdrd3_0: dwc3_typec0: usb@fe800000 { + compatible = "rockchip,rk3399-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + resets = <&cru SRST_A_USB3_OTG0>; + reset-names = "usb3-otg"; status = "disabled"; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk; + usbdrd_dwc3_0: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; + status = "disabled"; + }; + }; + + dwc3_typec1: usbdrd3_1: usb@fe900000 { + compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; - hub { - compatible = "usb-hub"; - usb,device-class = <USB_CLASS_HUB>; - }; - typec_phy0 { - compatible = "rockchip,rk3399-usb3-phy"; - reg = <0x0 0xff7c0000 0x0 0x40000>; + ranges; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + resets = <&cru SRST_A_USB3_OTG1>; + reset-names = "usb3-otg"; + status = "disabled"; + + usbdrd_dwc3_1: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe900000 0x0 0x100000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; + status = "disabled"; }; }; - dwc3_typec1: usb@fe900000 { - compatible = "rockchip,rk3399-xhci"; - reg = <0x0 0xfe900000 0x0 0x100000>; + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; + assigned-clock-rates = <100000000>, <200000000>; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + power-domains = <&power RK3399_PD_HDCP>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #sound-dai-cells = <1>; status = "disabled"; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk; - #address-cells = <2>; - #size-cells = <2>; - hub { - compatible = "usb-hub"; - usb,device-class = <USB_CLASS_HUB>; - }; - typec_phy1 { - compatible = "rockchip,rk3399-usb3-phy"; - reg = <0x0 0xff800000 0x0 0x40000>; + ports { + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; }; }; @@ -1054,6 +1114,21 @@ status = "disabled"; }; + i2c0: i2c@ff3c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3c0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C0_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c4: i2c@ff3d0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3d0000 0x0 0x1000>; @@ -1217,7 +1292,10 @@ <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; assigned-clock-rates = <594000000>, <800000000>, <1000000000>, @@ -1225,7 +1303,10 @@ <37500000>, <100000000>, <100000000>, <50000000>, <600000000>, - <100000000>, <50000000>; + <100000000>, <50000000>, + <400000000>, <400000000>, + <200000000>, + <200000000>; }; grf: syscon@ff770000 { @@ -1314,6 +1395,56 @@ }; }; + tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD0>; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + status = "disabled"; + + tcphy0_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD1>; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + status = "disabled"; + + tcphy1_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy1_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + watchdog@ff848000 { compatible = "snps,dw-wdt"; reg = <0x0 0xff848000 0x0 0x100>; @@ -1340,6 +1471,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spdif_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1355,6 +1487,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s0_8ch_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1369,6 +1502,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s1_2ch_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1381,21 +1515,7 @@ clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; power-domains = <&power RK3399_PD_SDIOAUDIO>; - status = "disabled"; - }; - - i2c0: i2c@ff3c0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3c0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C0_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1404,69 +1524,177 @@ compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x3efc>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + assigned-clock-rates = <400000000>, <100000000>; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vopl_mmu>; + power-domains = <&power RK3399_PD_VOPL>; resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; reset-names = "axi", "ahb", "dclk"; status = "disabled"; + vopl_out: port { #address-cells = <1>; #size-cells = <0>; + vopl_out_mipi: endpoint@0 { - reg = <3>; + reg = <0>; remote-endpoint = <&mipi_in_vopl>; }; - vopl_out_hdmi: endpoint@1 { + vopl_out_edp: endpoint@1 { reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + + vopl_out_hdmi: endpoint@2 { + reg = <2>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopl>; + }; + + vopl_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopl>; + }; }; }; + vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPL>; + #iommu-cells = <0>; + status = "disabled"; + }; + vopb: vop@ff900000 { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-vop-big"; reg = <0x0 0xff900000 0x0 0x3efc>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + assigned-clock-rates = <400000000>, <100000000>; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - #clock-cells = <0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vopb_mmu>; + power-domains = <&power RK3399_PD_VOPB>; resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; reset-names = "axi", "ahb", "dclk"; status = "disabled"; + vopb_out: port { #address-cells = <1>; #size-cells = <0>; - vopb_out_mipi: endpoint@0 { - reg = <3>; - remote-endpoint = <&mipi_in_vopb>; + + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_in_vopb>; }; - vopb_out_hdmi: endpoint@1 { + vopb_out_mipi: endpoint@1 { reg = <1>; + remote-endpoint = <&mipi_in_vopb>; + }; + + vopb_out_hdmi: endpoint@2 { + reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopb>; + }; + + vopb_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopb>; + }; + }; + }; + + vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPB>; + #iommu-cells = <0>; + status = "disabled"; + }; + + isp0_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "hdmi-sound"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; }; }; hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_HDMI_CTRL>, + <&cru SCLK_HDMI_SFR>, + <&cru PLL_VPLL>, + <&cru PCLK_VIO_GRF>, + <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "vpll", "grf", "cec"; + power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_i2c_xfer>; - power-domains = <&power RK3399_PD_HDCP>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; - clock-names = "iahb", "isfr", "vpll", "grf"; + #sound-dai-cells = <0>; status = "disabled"; ports { hdmi_in: port { #address-cells = <1>; #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; @@ -1507,6 +1735,88 @@ }; }; + mipi_dsi1: mipi@ff968000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff968000 0x0 0x8000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI1>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi1>; + }; + + mipi1_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi1>; + }; + }; + }; + }; + + edp: edp@ff970000 { + compatible = "rockchip,rk3399-edp"; + reg = <0x0 0xff970000 0x0 0x8000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; + clock-names = "dp", "pclk", "grf"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + power-domains = <&power RK3399_PD_EDP>; + resets = <&cru SRST_P_EDP_CTRL>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + gpu: gpu@ff9a0000 { + compatible = "rockchip,rk3399-mali", "arm,mali-t860"; + reg = <0x0 0xff9a0000 0x0 0x10000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "gpu", "job", "mmu"; + clocks = <&cru ACLK_GPU>; + power-domains = <&power RK3399_PD_GPU>; + status = "disabled"; + }; + pinctrl: pinctrl { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl"; @@ -1911,7 +2221,7 @@ <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; }; - sdmmc_cd: sdmcc-cd { + sdmmc_cd: sdmmc-cd { rockchip,pins = <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; }; diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index 0475598b77..e891f20b37 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -75,6 +75,14 @@ enum { MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, }; +/* CRU_CLKSEL8_CON */ +enum { + I2S0_FRAC_DENOM_SHIFT = 0, + I2S0_FRAC_DENOM_MASK = 0xffff << I2S0_FRAC_DENOM_SHIFT, + I2S0_FRAC_NUMER_SHIFT = 16, + I2S0_FRAC_NUMER_MASK = 0xffffu << I2S0_FRAC_NUMER_SHIFT, +}; + /* CRU_CLKSEL12_CON */ enum { EMMC_PLL_SHIFT = 0xe, diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h index e204dcfd1d..1aaec5faec 100644 --- a/arch/arm/include/asm/arch-rockchip/gpio.h +++ b/arch/arm/include/asm/arch-rockchip/gpio.h @@ -24,4 +24,34 @@ struct rockchip_gpio_regs { }; check_member(rockchip_gpio_regs, ls_sync, 0x60); +enum gpio_pu_pd { + GPIO_PULL_NORMAL = 0, + GPIO_PULL_UP, + GPIO_PULL_DOWN, + GPIO_PULL_REPEAT, +}; + +/* These defines are only used by spl_gpio.h */ +enum { + /* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */ + GPIO_BANK_SHIFT = 3, + GPIO_BANK_MASK = 3 << GPIO_BANK_SHIFT, + + GPIO_OFFSET_MASK = 0x1f, +}; + +#define GPIO(bank, offset) ((bank) << GPIO_BANK_SHIFT | (offset)) + +enum gpio_bank_t { + BANK_A = 0, + BANK_B, + BANK_C, + BANK_D, +}; + +enum gpio_dir_t { + GPIO_INPUT = 0, + GPIO_OUTPUT, +}; + #endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index c235607cee..894d3a40b0 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -561,6 +561,49 @@ enum { GPIO5C0_TS0_SYNC, }; +/* GRF_GPIO6A_IOMUX */ +enum { + GPIO6A7_SHIFT = 0xe, + GPIO6A7_MASK = 1, + GPIO6A7_GPIO = 0, + GPIO6A7_I2S_SDO3, + + GPIO6A6_SHIFT = 0xc, + GPIO6A6_MASK = 1, + GPIO6A6_GPIO = 0, + GPIO6A6_I2S_SDO2, + + GPIO6A5_SHIFT = 0xa, + GPIO6A5_MASK = 1, + GPIO6A5_GPIO = 0, + GPIO6A5_I2S_SDO1, + + GPIO6A4_SHIFT = 8, + GPIO6A4_MASK = 1, + GPIO6A4_GPIO = 0, + GPIO6A4_I2S_SDO0, + + GPIO6A3_SHIFT = 6, + GPIO6A3_MASK = 1, + GPIO6A3_GPIO = 0, + GPIO6A3_I2S_SDI, + + GPIO6A2_SHIFT = 4, + GPIO6A2_MASK = 1, + GPIO6A2_GPIO = 0, + GPIO6A2_I2S_LRCKTX, + + GPIO6A1_SHIFT = 2, + GPIO6A1_MASK = 1, + GPIO6A1_GPIO = 0, + GPIO6A1_I2S_LRCKRX, + + GPIO6A0_SHIFT = 0, + GPIO6A0_MASK = 1, + GPIO6A0_GPIO = 0, + GPIO6A0_I2S_SCLK, +}; + /* GRF_GPIO6B_IOMUX */ enum { GPIO6B3_SHIFT = 6, @@ -1042,6 +1085,59 @@ enum GRF_SOC_CON8 { RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, }; +/* GRF_IO_VSEL */ +enum { + GPIO1830_V18SEL_SHIFT = 9, + GPIO1830_V18SEL_MASK = 1, + GPIO1830_V18SEL_3_3V = 0, + GPIO1830_V18SEL_1_8V, + + GPIO30_V18SEL_SHIFT = 8, + GPIO30_V18SEL_MASK = 1, + GPIO30_V18SEL_3_3V = 0, + GPIO30_V18SEL_1_8V, + + SDCARD_V18SEL_SHIFT = 7, + SDCARD_V18SEL_MASK = 1, + SDCARD_V18SEL_3_3V = 0, + SDCARD_V18SEL_1_8V, + + AUDIO_V18SEL_SHIFT = 6, + AUDIO_V18SEL_MASK = 1, + AUDIO_V18SEL_3_3V = 0, + AUDIO_V18SEL_1_8V, + + BB_V18SEL_SHIFT = 5, + BB_V18SEL_MASK = 1, + BB_V18SEL_3_3V = 0, + BB_V18SEL_1_8V, + + WIFI_V18SEL_SHIFT = 4, + WIFI_V18SEL_MASK = 1, + WIFI_V18SEL_3_3V = 0, + WIFI_V18SEL_1_8V, + + FLASH1_V18SEL_SHIFT = 3, + FLASH1_V18SEL_MASK = 1, + FLASH1_V18SEL_3_3V = 0, + FLASH1_V18SEL_1_8V, + + FLASH0_V18SEL_SHIFT = 2, + FLASH0_V18SEL_MASK = 1, + FLASH0_V18SEL_3_3V = 0, + FLASH0_V18SEL_1_8V, + + DVP_V18SEL_SHIFT = 1, + DVP_V18SEL_MASK = 1, + DVP_V18SEL_3_3V = 0, + DVP_V18SEL_1_8V, + + LCDC_V18SEL_SHIFT = 0, + LCDC_V18SEL_MASK = 1, + LCDC_V18SEL_3_3V = 0, + LCDC_V18SEL_1_8V, +}; + /* GPIO Bias settings */ enum GPIO_BIAS { GPIO_BIAS_2MA = 0, @@ -1053,13 +1149,6 @@ enum GPIO_BIAS { #define GPIO_BIAS_MASK 0x3 #define GPIO_BIAS_SHIFT(x) ((x) * 2) -enum GPIO_PU_PD { - GPIO_PULL_NORMAL = 0, - GPIO_PULL_UP, - GPIO_PULL_DOWN, - GPIO_PULL_REPEAT, -}; - #define GPIO_PULL_MASK 0x3 #define GPIO_PULL_SHIFT(x) ((x) * 2) diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index 514baf6a53..2191b7d43a 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -45,6 +45,7 @@ enum periph_id { PERIPH_ID_HDMI, PERIPH_ID_GMAC, PERIPH_ID_SFC, + PERIPH_ID_I2S, PERIPH_ID_COUNT, diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 925fcc888c..928e4f258b 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -29,4 +29,7 @@ static void configure_l2ctlr(void) } #endif /* CONFIG_ROCKCHIP_RK3288 */ +/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 8e9d88c3f9..b9a026abb5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -29,7 +29,6 @@ config ROCKCHIP_RK3188 select SUPPORT_SPL select SPL select SPL_CLK - select SPL_PINCTRL select SPL_REGMAP select SPL_SYSCON select SPL_RAM diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index f32b3c4ce5..d7997d71e3 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -61,7 +61,13 @@ int setup_boot_mode(void) void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG; int boot_mode = readl(reg); - rockchip_dnl_mode_check(); + /* + * This should be handled using a driver-tree property and a suitable + * driver which can read the appropriate settings. As it is, this + * breaks chromebook_minnie.\ + * + * rockchip_dnl_mode_check(); + */ boot_mode = readl(reg); debug("%s: boot mode 0x%08x\n", __func__, boot_mode); diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 95871cdd2e..872bed9606 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -7,13 +7,13 @@ #include <clk.h> #include <dm.h> #include <ram.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/periph.h> #include <asm/arch/grf_rk3036.h> #include <asm/arch/boot_mode.h> #include <asm/arch/sdram_rk3036.h> -#include <asm/gpio.h> #include <dm/pinctrl.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 3c6c3d3c09..5c09b0e4ae 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -12,6 +12,7 @@ #include <malloc.h> #include <ram.h> #include <spl.h> +#include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/bootrom.h> @@ -27,7 +28,6 @@ #include <dm/test.h> #include <dm/util.h> #include <power/regulator.h> -#include <syscon.h> DECLARE_GLOBAL_DATA_PTR; @@ -120,7 +120,7 @@ void board_debug_uart_init(void) void board_init_f(ulong dummy) { - struct udevice *pinctrl, *dev; + struct udevice *dev; int ret; #define EARLY_UART @@ -134,10 +134,7 @@ void board_init_f(ulong dummy) * printascii("string"); */ debug_uart_init(); - printch('s'); - printch('p'); - printch('l'); - printch('\n'); + printascii("U-Boot SPL board init"); #endif #ifdef CONFIG_ROCKCHIP_USB_UART @@ -171,12 +168,6 @@ void board_init_f(ulong dummy) return; } - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("Pinctrl init failed: %d\n", ret); - return; - } - ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); @@ -214,7 +205,6 @@ static int setup_led(void) void spl_board_init(void) { - struct udevice *pinctrl; int ret; ret = setup_led(); @@ -223,36 +213,9 @@ void spl_board_init(void) hang(); } - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - -#ifdef CONFIG_SPL_MMC_SUPPORT - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } -#endif - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - preloader_console_init(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif return; - -err: - printf("spl_board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); } diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 8853e4a58e..3802395bc0 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -8,13 +8,13 @@ #include <dm.h> #include <ram.h> #include <syscon.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/grf_rk3188.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3288.h> #include <asm/arch/boot_mode.h> -#include <asm/gpio.h> #include <dm/pinctrl.h> __weak int rk_board_late_init(void) diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index 7366d45ab6..5659248178 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -8,10 +8,10 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> +#include <asm/arch/boot_mode.h> #include <asm/arch/clock.h> #include <asm/arch/periph.h> #include <asm/arch/grf_rk322x.h> -#include <asm/arch/boot_mode.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index abd62e520f..93c772184d 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -71,51 +71,13 @@ u32 spl_boot_device(void) fallback: #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_MMC1; } -#ifdef CONFIG_SPL_MMC_SUPPORT -static int configure_emmc(struct udevice *pinctrl) -{ -#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) - - struct gpio_desc desc; - int ret; - - pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC); - - /* - * TODO(sjg@chromium.org): Pick this up from device tree or perhaps - * use the EMMC_PWREN setting. - */ - ret = dm_gpio_lookup_name("D9", &desc); - if (ret) { - debug("gpio ret=%d\n", ret); - return ret; - } - ret = dm_gpio_request(&desc, "emmc_pwren"); - if (ret) { - debug("gpio_request ret=%d\n", ret); - return ret; - } - ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); - if (ret) { - debug("gpio dir ret=%d\n", ret); - return ret; - } - ret = dm_gpio_set_value(&desc, 1); - if (ret) { - debug("gpio value ret=%d\n", ret); - return ret; - } -#endif - return 0; -} -#endif - #if !defined(CONFIG_SPL_OF_PLATDATA) static int phycore_init(void) { @@ -144,7 +106,6 @@ static int phycore_init(void) void board_init_f(ulong dummy) { - struct udevice *pinctrl; struct udevice *dev; int ret; @@ -183,12 +144,6 @@ void board_init_f(ulong dummy) return; } - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("Pinctrl init failed: %d\n", ret); - return; - } - #if !defined(CONFIG_SPL_OF_PLATDATA) if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { ret = phycore_init(); @@ -239,52 +194,19 @@ static int setup_led(void) void spl_board_init(void) { - struct udevice *pinctrl; int ret; ret = setup_led(); - if (ret) { debug("LED ret=%d\n", ret); hang(); } - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - -#ifdef CONFIG_SPL_MMC_SUPPORT - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - ret = configure_emmc(pinctrl); - if (ret) { - debug("%s: Failed to set up eMMC\n", __func__); - goto err; - } -#endif - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - preloader_console_init(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif return; -err: - printf("spl_board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); } #ifdef CONFIG_SPL_OS_BOOT diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index b5447e5b65..bce8023881 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of internal MMC. The product name is ASUS Chromebook Flip. +config TARGET_CHROMEBOOK_SPEEDY + bool "Google/Rockchip Veyron-Speedy Chromebook" + select BOARD_LATE_INIT + help + Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports, + micro HDMI, an 11.6 inch display, micro-SD card, + HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS + EC (Cortex-M3) to provide access to the keyboard and battery + functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC. + The product name is Asus Chromebook C201PA. + config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index eae8ef15f3..230850ad6c 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -6,7 +6,6 @@ #include <common.h> #include <debug_uart.h> #include <dm.h> -#include <dm/pinctrl.h> #include <ram.h> #include <spl.h> #include <asm/io.h> @@ -15,6 +14,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/timer.h> +#include <dm/pinctrl.h> void board_debug_uart_init(void) { diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index 3b33ce468a..f90a1fdca7 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -4,18 +4,18 @@ */ #include <common.h> -#include <asm/arch/clock.h> #include <debug_uart.h> #include <dm.h> #include <ram.h> #include <spl.h> +#include <syscon.h> #include <asm/io.h> #include <asm/arch/bootrom.h> +#include <asm/arch/clock.h> #include <asm/arch/cru_rk3368.h> #include <asm/arch/grf_rk3368.h> #include <asm/arch/hardware.h> #include <asm/arch/timer.h> -#include <syscon.h> /* * The SPL (and also the full U-Boot stage on the RK3368) will run in diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 0198c6c65f..ccc136f388 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -5,18 +5,20 @@ */ #include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <spl_gpio.h> +#include <syscon.h> +#include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h> #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> -#include <asm/io.h> -#include <debug_uart.h> -#include <dm.h> +#include <asm/arch/sys_proto.h> #include <dm/pinctrl.h> -#include <ram.h> -#include <spl.h> -#include <syscon.h> void board_return_to_bootrom(void) { @@ -128,7 +130,13 @@ void secure_timer_init(void) void board_debug_uart_init(void) { #define GRF_BASE 0xff770000 +#define GPIO0_BASE 0xff720000 +#define PMUGRF_BASE 0xff320000 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; +#ifdef CONFIG_TARGET_CHROMEBOOK_BOB + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; +#endif #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) /* Enable early UART0 on the RK3399 */ @@ -139,6 +147,20 @@ void board_debug_uart_init(void) GRF_GPIO2C1_SEL_MASK, GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); #else +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running the SPI + * Flash based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, @@ -163,6 +185,22 @@ void board_init_f(ulong dummy) #define EARLY_UART #ifdef EARLY_UART + debug_uart_init(); + +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + int sum, i; + + /* + * Add a delay and ensure that the compiler does not optimise this out. + * This is needed since the power rails tail a while to turn on, and + * we get garbage serial output otherwise. + */ + sum = 0; + for (i = 0; i < 150000; i++) + sum += i; + gru_dummy_function(sum); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + /* * Debug UART can be used from here if required: * @@ -171,7 +209,6 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - debug_uart_init(); printascii("U-Boot SPL board init\n"); #endif diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 8f18e33c76..2408adb420 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -53,6 +53,15 @@ config TARGET_ROCK960_RK3399 * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG +config TARGET_CHROMEBOOK_BOB + bool "Asus Flip C101PA Chromebook (RK3399)" + help + Bob is a small RK3299-based device similar in apperance to Minnie. + It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1", + 1280x800 display. It uses its USB ports for both power and external + display. It includes a Chrome OS EC (Cortex-M3) to provide access to + the keyboard and battery functions. + endchoice config SYS_SOC @@ -64,5 +73,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" +source "board/google/gru/Kconfig" endif diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 81a72cc263..0e485deda2 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -61,6 +61,9 @@ static int spl_node_to_boot_device(int node) default: return -ENOSYS; } + } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, + &parent)) { + return BOOT_DEVICE_SPI; } /* diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig new file mode 100644 index 0000000000..61f7bbca98 --- /dev/null +++ b/board/google/gru/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_BOB + +config SYS_BOARD + default "gru" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "gru" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/gru/MAINTAINERS b/board/google/gru/MAINTAINERS new file mode 100644 index 0000000000..e1cda756b8 --- /dev/null +++ b/board/google/gru/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK BOB BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/gru/ +F: include/configs/gru.h +F: configs/chromebook_bob_defconfig diff --git a/board/google/gru/Makefile b/board/google/gru/Makefile new file mode 100644 index 0000000000..9117534a49 --- /dev/null +++ b/board/google/gru/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += gru.o diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c new file mode 100644 index 0000000000..b116b1a549 --- /dev/null +++ b/board/google/gru/gru.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google + */ + +#include <common.h> + +int board_init(void) +{ + return 0; +} + +/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i) +{ +} diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig index 770e9aad28..7f55d78dac 100644 --- a/board/google/veyron/Kconfig +++ b/board/google/veyron/Kconfig @@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y endif + +if TARGET_CHROMEBOOK_SPEEDY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS index 246a3e3b55..d97978076d 100644 --- a/board/google/veyron/MAINTAINERS +++ b/board/google/veyron/MAINTAINERS @@ -18,3 +18,10 @@ S: Maintained F: board/google/veyron/ F: include/configs/veyron.h F: configs/chromebook_minnie_defconfig + +CHROMEBOOK SPEEDY BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebook_speedy_defconfig diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README index 8321467046..6469821987 100644 --- a/board/rockchip/evb_rk3399/README +++ b/board/rockchip/evb_rk3399/README @@ -35,21 +35,29 @@ Get the Source and prebuild binary > git clone https://github.com/rockchip-linux/rkbin.git > git clone https://github.com/rockchip-linux/rkdeveloptool.git -Compile the ATF -=============== +Get some prerequisites +====================== + +You need the Python elftools.elf.elffile library for make_fit_atf.py to work: + + > sudo apt-get install python-pyelftools + +Compile ATF +=========== > cd arm-trusted-firmware > make realclean > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + Get bl31.elf in this step, copy it to U-Boot root dir: + > cp build/rk3399/release/bl31/bl31.elf ../u-boot/ + Or you can get the bl31.elf directly from Rockchip: - cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf + > cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf - Get bl31.elf in this step, copy it to U-Boot root dir: - > cp bl31.elf ../u-boot/ -Compile the U-Boot -================== +Compile U-Boot +============== > cd ../u-boot > export ARCH=arm64 @@ -62,17 +70,18 @@ Compile the U-Boot Get spl/u-boot-spl.bin and u-boot.itb in this step. -Compile the rkdeveloptool -======================= - Follow instructions in latest README +Compile rkdeveloptool +===================== + +Get rkdeveloptool installed on your Host in this step. + +Follow instructions in latest README, example: > cd ../rkdeveloptool > autoreconf -i > ./configure > make > sudo make install - Get rkdeveloptool in you Host in this step. - Both origin binaries and Tool are ready now, choose either option 1 or option 2 to deploy U-Boot. diff --git a/cmd/gpio.c b/cmd/gpio.c index c60946bc06..4ac1f1e418 100644 --- a/cmd/gpio.c +++ b/cmd/gpio.c @@ -18,10 +18,10 @@ __weak int name_to_gpio(const char *name) } enum gpio_cmd { - GPIO_INPUT, - GPIO_SET, - GPIO_CLEAR, - GPIO_TOGGLE, + GPIOC_INPUT, + GPIOC_SET, + GPIOC_CLEAR, + GPIOC_TOGGLE, }; #if defined(CONFIG_DM_GPIO) && !defined(gpio_status) @@ -158,11 +158,20 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* parse the behavior */ switch (*str_cmd) { - case 'i': sub_cmd = GPIO_INPUT; break; - case 's': sub_cmd = GPIO_SET; break; - case 'c': sub_cmd = GPIO_CLEAR; break; - case 't': sub_cmd = GPIO_TOGGLE; break; - default: goto show_usage; + case 'i': + sub_cmd = GPIOC_INPUT; + break; + case 's': + sub_cmd = GPIOC_SET; + break; + case 'c': + sub_cmd = GPIOC_CLEAR; + break; + case 't': + sub_cmd = GPIOC_TOGGLE; + break; + default: + goto show_usage; } #if defined(CONFIG_DM_GPIO) @@ -192,18 +201,18 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } /* finally, let's do it: set direction and exec command */ - if (sub_cmd == GPIO_INPUT) { + if (sub_cmd == GPIOC_INPUT) { gpio_direction_input(gpio); value = gpio_get_value(gpio); } else { switch (sub_cmd) { - case GPIO_SET: + case GPIOC_SET: value = 1; break; - case GPIO_CLEAR: + case GPIOC_CLEAR: value = 0; break; - case GPIO_TOGGLE: + case GPIOC_TOGGLE: value = gpio_get_value(gpio); if (!IS_ERR_VALUE(value)) value = !value; @@ -218,7 +227,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("unknown (ret=%d)\n", value); else printf("%d\n", value); - if (sub_cmd != GPIO_INPUT && !IS_ERR_VALUE(value)) { + if (sub_cmd != GPIOC_INPUT && !IS_ERR_VALUE(value)) { int nval = gpio_get_value(gpio); if (IS_ERR_VALUE(nval)) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 1c20dcd882..fd4cd806e6 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -38,7 +38,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -62,8 +61,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y @@ -92,4 +89,3 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig new file mode 100644 index 0000000000..56b52bc160 --- /dev/null +++ b/configs/chromebook_bob_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_BOB=y +CONFIG_DEBUG_UART_BASE=0xff1a0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_LOG_DEFAULT_LEVEL=7 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 94a1af01be..88a37c5d82 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -14,6 +14,8 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_SILENT_CONSOLE=y +CONFIG_LOG=y +CONFIG_LOG_DEFAULT_LEVEL=7 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -32,6 +34,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -40,7 +43,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -64,8 +66,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y @@ -76,6 +76,10 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SERIAL=y +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_ROCKCHIP=y +CONFIG_SOUND_MAX98090=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y @@ -96,4 +100,3 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index cb7f52f040..2e17e73ded 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -39,7 +39,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -63,8 +62,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y @@ -94,4 +91,3 @@ CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig new file mode 100644 index 0000000000..f1c5ed7293 --- /dev/null +++ b/configs/chromebook_speedy_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00100000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_SPEEDY=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SILENT_CONSOLE=y +CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x320a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_CONSOLE_TRUETYPE=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +# CONFIG_USE_PRIVATE_LIBGCC is not set +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index c3bda3bf3b..1d428e7ac8 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -22,7 +22,6 @@ CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3368=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index 00bf907ff1..78c5ac6f53 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -31,7 +31,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3128=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 0cc92a3314..14ff54af20 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -44,7 +44,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 980f7f7b3d..671bb8ca3c 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -57,8 +57,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 3ec6b20814..3a0ed1808b 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y @@ -50,7 +49,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3399=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 0ca6930e43..3db453f5f6 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -37,7 +37,6 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 # CONFIG_SPL_SERIAL_PRESENT is not set diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 2795ad82b0..25baf4cbbd 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -56,8 +56,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index f5a8b614f6..8c1f7639fd 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -59,8 +59,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_ACT8846=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index e77bc4463d..3b3be2218f 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -49,7 +49,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3399=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 884c5fe3e1..f40bcd97d8 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -17,7 +17,6 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3368=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index a577605822..57558c6323 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -41,7 +41,6 @@ CONFIG_LED=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3036=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_SYSRESET=y diff --git a/configs/kylin-rk3036_defconfig.rej b/configs/kylin-rk3036_defconfig.rej new file mode 100644 index 0000000000..5478e65f1a --- /dev/null +++ b/configs/kylin-rk3036_defconfig.rej @@ -0,0 +1,10 @@ +--- configs/kylin-rk3036_defconfig ++++ configs/kylin-rk3036_defconfig +@@ -8,6 +8,7 @@ CONFIG_ROCKCHIP_RK3036=y + CONFIG_TARGET_KYLIN_RK3036=y + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" ++CONFIG_DEBUG_UART=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 + # CONFIG_ANDROID_BOOT_IMAGE is not set + # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 2b61922ff5..d6dd0e5106 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -79,7 +79,6 @@ CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3368=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index fcb7163ba1..0d9f6c36b6 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -56,8 +56,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 1e33e542ef..92aa802ade 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -60,8 +60,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 85f4f393e8..5cbcb89722 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -56,8 +56,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index fd492312a1..3fcff2580a 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -74,8 +75,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3399=y -CONFIG_PINCTRL_ROCKCHIP_RK3399_FULL=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y diff --git a/configs/puma-rk3399_defconfig.rej b/configs/puma-rk3399_defconfig.rej new file mode 100644 index 0000000000..78a1819b5f --- /dev/null +++ b/configs/puma-rk3399_defconfig.rej @@ -0,0 +1,10 @@ +--- configs/puma-rk3399_defconfig ++++ configs/puma-rk3399_defconfig +@@ -74,7 +74,6 @@ CONFIG_ETH_DESIGNWARE=y + CONFIG_GMAC_ROCKCHIP=y + CONFIG_PINCTRL=y + CONFIG_SPL_PINCTRL=y +-CONFIG_PINCTRL_ROCKCHIP_RK3399=y + CONFIG_DM_PMIC=y + CONFIG_DM_PMIC_FAN53555=y + CONFIG_PMIC_RK8XX=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 702e8e91cb..a5faa8fb95 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -56,8 +56,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_ACT8846=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 0c41ac9f20..36e35eb65d 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -41,7 +41,6 @@ CONFIG_LED=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3188=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_ACT8846=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 8dfd92f7b2..193e41896c 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -149,8 +149,6 @@ CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y -CONFIG_PINCTRL_ROCKCHIP_RK3036=y -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_PINCTRL_SANDBOX=y CONFIG_POWER_DOMAIN=y CONFIG_SANDBOX_POWER_DOMAIN=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 63e3745522..40eb870c35 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -119,8 +119,6 @@ CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y -CONFIG_PINCTRL_ROCKCHIP_RK3036=y -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_PINCTRL_SANDBOX=y CONFIG_POWER_DOMAIN=y CONFIG_SANDBOX_POWER_DOMAIN=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 1a30e53f6f..79befa6b0a 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -121,8 +121,6 @@ CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y -CONFIG_PINCTRL_ROCKCHIP_RK3036=y -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_PINCTRL_SANDBOX=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 23e653d660..aac2243208 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -20,7 +20,6 @@ CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3368=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index e0fc1875ee..24222e5395 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -59,8 +59,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 989ede35a1..03c8a76cbe 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -54,8 +54,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 51b00a9d85..ec10ebbc26 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -6,13 +6,7 @@ U-Boot on Rockchip ================== -There are several repositories available with versions of U-Boot that support -many Rockchip devices [1] [2]. - -The current mainline support is experimental only and is not useful for -anything. It should provide a base on which to build. - -So far only support for the RK3288 and RK3036 is provided. +A wide range of Rockchip SoCs are supported in mainline U-Boot Prerequisites @@ -34,23 +28,64 @@ You will need: Building ======== -At present nine RK3288 boards are supported: +At present 12 RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - Fennec RK3288 - use fennec-rk3288 configuration - Firefly RK3288 - use firefly-rk3288 configuration - Hisense Chromebook - use chromebook_jerry configuration + - Asus C100P Chromebook - use chromebook_minnie configuration + - Asus Chromebit - use chromebook_mickey configuration - MiQi RK3288 - use miqi-rk3288 configuration - phyCORE-RK3288 RDK - use phycore-rk3288 configuration - PopMetal RK3288 - use popmetal-rk3288 configuration - Radxa Rock 2 - use rock2 configuration - Tinker RK3288 - use tinker-rk3288 configuration + - Vyasa RK3288 - use vyasa-rk3288 configuration -Two RK3036 board are supported: +Two RK3036 boards are supported: - EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration +One RK3328 board is supported: + + - EVB RK3328 + +Size RK3399 boards are supported (aarch64): + + - EBV RK3399 - use evb_rk3399 configuration + - Firefly RK3399 - use the firefly_rk3399 configuration + - Puma - use puma_rk3399 configuration + - Ficus - use ficus-rk3399 configuration + - Rock960 (Vamrs) - use rock960-rk3399 configuration + - Bob - use chromebook_bob configuration + +Four RK3368 boards are supported: + + - Sheep - use sheep-rk3368 configuration + - Lion - use lion-rk3368 configuration + - Geekbox - use geekbox configuration + - EVB PX5 - use evb-px5 configuration + +One RK3128 board is supported: + + - EVB RK3128 - use evb-rk3128 configuration + +One RK3229 board is supported: + + - EVB RK3229 - use evb-rk3229 configuration + +Two RV1108 boards are supported: + + - EVB RV1108 - use evb-rv1108 configuration + - Elgin R1 - use elgin-rv1108 configuration + +One RV3188 baord is supported: + + - Raxda Rock - use rock configuration + + For example: CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all @@ -219,7 +254,8 @@ You should see something like: Booting from SPI ================ -To write an image that boots from SPI flash (e.g. for the Haier Chromebook): +To write an image that boots from SPI flash (e.g. for the Haier Chromebook or +Bob): ./chromebook_jerry/tools/mkimage -n rk3288 -T rkspi \ -d chromebook_jerry/spl/u-boot-spl-dtb.bin spl.bin && \ @@ -228,7 +264,7 @@ To write an image that boots from SPI flash (e.g. for the Haier Chromebook): dd if=out.bin of=out.bin.pad bs=4M conv=sync This converts the SPL image to the required SPI format by adding the Rockchip -header and skipping every 2KB block. Then the U-Boot image is written at +header and skipping every second 2KB block. Then the U-Boot image is written at offset 128KB and the whole image is padded to 4MB which is the SPI flash size. The position of U-Boot is controlled with this setting in U-Boot: @@ -264,7 +300,6 @@ Immediate priorities are: - USB device - Run CPU at full speed (code exists but we only see ~60 DMIPS maximum) - NAND flash -- Support for other Rockchip parts - Boot U-Boot proper over USB OTG (at present only SPL works) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 6d7a514006..844b87cc33 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -228,8 +228,8 @@ static int clk_set_default_rates(struct udevice *dev) ret = clk_set_rate(&clk, rates[index]); if (ret < 0) { - debug("%s: failed to set rate on clock %d for %s\n", - __func__, index, dev_read_name(dev)); + debug("%s: failed to set rate on clock index %d (%ld) for %s\n", + __func__, index, clk.id, dev_read_name(dev)); break; } } diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 4a6e5c7113..930c99f4d9 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -6,6 +6,7 @@ #include <common.h> #include <bitfield.h> #include <clk-uclass.h> +#include <div64.h> #include <dm.h> #include <dt-structs.h> #include <errno.h> @@ -371,6 +372,50 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, return 0; } + +static u32 rockchip_clk_gcd(u32 a, u32 b) +{ + while (b != 0) { + int r = b; + + b = a % b; + a = r; + } + return a; +} + +static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate) +{ + unsigned long long rate; + uint val; + int n, d; + + val = readl(&cru->cru_clksel_con[8]); + n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT; + d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT; + + rate = (unsigned long long)gclk_rate * n; + do_div(rate, d); + + return (ulong)rate; +} + +static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate, + uint freq) +{ + int n, d; + int v; + + /* set frac divider */ + v = rockchip_clk_gcd(gclk_rate, freq); + n = gclk_rate / v; + d = freq / v; + assert(freq == gclk_rate / n * d); + writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT, + &cru->cru_clksel_con[8]); + + return rockchip_i2s_get_clk(cru, gclk_rate); +} #endif /* CONFIG_SPL_BUILD */ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) @@ -769,6 +814,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); break; #ifndef CONFIG_SPL_BUILD + case SCLK_I2S0: + new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate); + break; case SCLK_MAC: new_rate = rockchip_mac_set_clk(priv->cru, rate); break; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 198914b067..cab2bd9943 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -925,7 +925,13 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_SARADC: rate = rk3399_saradc_get_clk(priv->cru); break; + case ACLK_VIO: + case ACLK_HDCP: + case ACLK_GIC_PRE: + case PCLK_DDR: + break; default: + log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; } @@ -993,7 +999,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: ret = rk3399_saradc_set_clk(priv->cru, rate); break; + case ACLK_VIO: + case ACLK_HDCP: + case ACLK_GIC_PRE: + case PCLK_DDR: + return 0; default: + log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; } diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index a8f311bbd6..21df227717 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -91,6 +91,52 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) #endif } +/* Simple SPL interface to GPIOs */ +#ifdef CONFIG_SPL_BUILD + +enum { + PULL_NONE_1V8 = 0, + PULL_DOWN_1V8 = 1, + PULL_UP_1V8 = 3, +}; + +int spl_gpio_set_pull(void *vregs, uint gpio, int pull) +{ + u32 *regs = vregs; + uint val; + + regs += gpio >> GPIO_BANK_SHIFT; + gpio &= GPIO_OFFSET_MASK; + switch (pull) { + case GPIO_PULL_UP: + val = PULL_UP_1V8; + break; + case GPIO_PULL_DOWN: + val = PULL_DOWN_1V8; + break; + case GPIO_PULL_NORMAL: + default: + val = PULL_NONE_1V8; + break; + } + clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2)); + + return 0; +} + +int spl_gpio_output(void *vregs, uint gpio, int value) +{ + struct rockchip_gpio_regs * const regs = vregs; + + clrsetbits_le32(®s->swport_dr, 1 << gpio, value << gpio); + + /* Set direction */ + clrsetbits_le32(®s->swport_ddr, 1 << gpio, 1 << gpio); + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ + static int rockchip_gpio_probe(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index fb441b3bf1..be709f73d7 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -158,96 +158,6 @@ config PINCTRL_QCA953X the GPIO definitions and pin control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RK3036 - bool "Rockchip rk3036 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3036 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3128 - bool "Rockchip rk3128 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3128 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3188 - bool "Rockchip rk3188 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3188 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK322X - bool "Rockchip rk322x pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk322x SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3288 - bool "Rockchip rk3288 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3288 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3328 - bool "Rockchip rk3328 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3328 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3368 - bool "Rockchip RK3368 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3368 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3399 - bool "Rockchip rk3399 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3399 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3399_FULL - bool "Rockchip rk3399 pin control driver (full)" - depends on PINCTRL_FULL && PINCTRL_ROCKCHIP_RK3399 - help - Support full pin multiplexing control on Rockchip rk3399 SoCs. - - This enables the full pinctrl driver for the RK3399. - Contrary to the non-full pinctrl driver, this will evaluate - the board DTB to get the pinctrl settings. - config PINCTRL_ROCKCHIP_RV1108 bool "Rockchip rv1108 pin control driver" depends on DM @@ -310,14 +220,15 @@ config ASPEED_AST2500_PINCTRL endif -source "drivers/pinctrl/meson/Kconfig" +source "drivers/pinctrl/broadcom/Kconfig" +source "drivers/pinctrl/exynos/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" +source "drivers/pinctrl/meson/Kconfig" +source "drivers/pinctrl/mscc/Kconfig" +source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" +source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" -source "drivers/pinctrl/exynos/Kconfig" -source "drivers/pinctrl/mscc/Kconfig" -source "drivers/pinctrl/mvebu/Kconfig" -source "drivers/pinctrl/broadcom/Kconfig" endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 66d36b99d1..e2c2b159d8 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -6,10 +6,10 @@ obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-y += nxp/ +obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ -obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ diff --git a/drivers/pinctrl/rockchip/Kconfig b/drivers/pinctrl/rockchip/Kconfig new file mode 100644 index 0000000000..dc4ba34ae5 --- /dev/null +++ b/drivers/pinctrl/rockchip/Kconfig @@ -0,0 +1,17 @@ +if ARCH_ROCKCHIP + +config PINCTRL_ROCKCHIP + bool "Rockchip pin control drivers" + depends on ARCH_ROCKCHIP && PINCTRL_GENERIC + default y + help + Enable support pin control functions for Rockchip SoCs. + +config SPL_PINCTRL_ROCKCHIP + bool "Support Rockchip pin controllers in SPL" + depends on ARCH_ROCKCHIP && SPL_PINCTRL_GENERIC + default y + help + This option is an SPL-variant of the PINCTRL_ROCKCHIP option. + +endif diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 5e3fbcb4bc..a616d8587f 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -2,12 +2,13 @@ # # Copyright (c) 2017 Rockchip Electronics Co., Ltd -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3128) += pinctrl_rk3128.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3399) += pinctrl_rk3399.o -obj-$(CONFIG_PINCTRL_ROCKCHIP_RV1108) += pinctrl_rv1108.o +obj-y += pinctrl-rockchip-core.o +obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o +obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o +obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o +obj-$(CONFIG_ROCKCHIP_RK3288) += pinctrl-rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o +obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o +obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o +obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c new file mode 100644 index 0000000000..2729b03443 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +#define RK3036_PULL_OFFSET 0x118 +#define RK3036_PULL_PINS_PER_REG 16 +#define RK3036_PULL_BANK_STRIDE 8 + +static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3036_PULL_OFFSET; + *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE; + *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4; + + *bit = pin_num % RK3036_PULL_PINS_PER_REG; +}; + +static struct rockchip_pin_bank rk3036_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), +}; + +static struct rockchip_pin_ctrl rk3036_pin_ctrl = { + .pin_banks = rk3036_pin_banks, + .nr_banks = ARRAY_SIZE(rk3036_pin_banks), + .label = "RK3036-GPIO", + .type = RK3036, + .grf_mux_offset = 0xa8, + .pull_calc_reg = rk3036_calc_pull_reg_and_bit, +}; + +static const struct udevice_id rk3036_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3036-pinctrl", + .data = (ulong)&rk3036_pin_ctrl + }, + {} +}; + +U_BOOT_DRIVER(pinctrl_rockchip) = { + .name = "rk3036-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3036_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c new file mode 100644 index 0000000000..43a6c173a0 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { + { + .num = 2, + .pin = 20, + .reg = 0xe8, + .bit = 0, + .mask = 0x7 + }, { + .num = 2, + .pin = 21, + .reg = 0xe8, + .bit = 4, + .mask = 0x7 + }, { + .num = 2, + .pin = 22, + .reg = 0xe8, + .bit = 8, + .mask = 0x7 + }, { + .num = 2, + .pin = 23, + .reg = 0xe8, + .bit = 12, + .mask = 0x7 + }, { + .num = 2, + .pin = 24, + .reg = 0xd4, + .bit = 12, + .mask = 0x7 + }, +}; + +static struct rockchip_mux_route_data rk3128_mux_route_data[] = { + { + /* spi-0 */ + .bank_num = 1, + .pin = 10, + .func = 1, + .route_offset = 0x144, + .route_val = BIT(16 + 3) | BIT(16 + 4), + }, { + /* spi-1 */ + .bank_num = 1, + .pin = 27, + .func = 3, + .route_offset = 0x144, + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), + }, { + /* spi-2 */ + .bank_num = 0, + .pin = 13, + .func = 2, + .route_offset = 0x144, + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), + }, { + /* i2s-0 */ + .bank_num = 1, + .pin = 5, + .func = 1, + .route_offset = 0x144, + .route_val = BIT(16 + 5), + }, { + /* i2s-1 */ + .bank_num = 0, + .pin = 14, + .func = 1, + .route_offset = 0x144, + .route_val = BIT(16 + 5) | BIT(5), + }, { + /* emmc-0 */ + .bank_num = 1, + .pin = 22, + .func = 2, + .route_offset = 0x144, + .route_val = BIT(16 + 6), + }, { + /* emmc-1 */ + .bank_num = 2, + .pin = 4, + .func = 2, + .route_offset = 0x144, + .route_val = BIT(16 + 6) | BIT(6), + }, +}; + +#define RK3128_PULL_OFFSET 0x118 +#define RK3128_PULL_PINS_PER_REG 16 +#define RK3128_PULL_BANK_STRIDE 8 + +static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3128_PULL_OFFSET; + *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4); + + *bit = pin_num % RK3128_PULL_PINS_PER_REG; +} + +static struct rockchip_pin_bank rk3128_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3128_pin_ctrl = { + .pin_banks = rk3128_pin_banks, + .nr_banks = ARRAY_SIZE(rk3128_pin_banks), + .label = "RK3128-GPIO", + .type = RK3128, + .grf_mux_offset = 0xa8, + .iomux_recalced = rk3128_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), + .iomux_routes = rk3128_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), + .pull_calc_reg = rk3128_calc_pull_reg_and_bit, +}; + +static const struct udevice_id rk3128_pinctrl_ids[] = { + { .compatible = "rockchip,rk3128-pinctrl", + .data = (ulong)&rk3128_pin_ctrl }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3128) = { + .name = "pinctrl_rk3128", + .id = UCLASS_PINCTRL, + .of_match = rk3128_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c new file mode 100644 index 0000000000..5ed9aec938 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +#define RK3188_PULL_OFFSET 0x164 +#define RK3188_PULL_PMU_OFFSET 0x64 + +static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 12 pins of the first bank are located elsewhere */ + if (bank->bank_num == 0 && pin_num < 12) { + *regmap = priv->regmap_pmu; + *reg = RK3188_PULL_PMU_OFFSET; + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } else { + *regmap = priv->regmap_base; + *reg = RK3188_PULL_OFFSET; + + /* correct the offset, as it is the 2nd pull register */ + *reg -= 4; + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + /* + * The bits in these registers have an inverse ordering + * with the lowest pin being in bits 15:14 and the highest + * pin in bits 1:0 + */ + *bit = 7 - (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } +} + +static struct rockchip_pin_bank rk3188_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3188_pin_ctrl = { + .pin_banks = rk3188_pin_banks, + .nr_banks = ARRAY_SIZE(rk3188_pin_banks), + .label = "RK3188-GPIO", + .type = RK3188, + .grf_mux_offset = 0x60, + .pull_calc_reg = rk3188_calc_pull_reg_and_bit, +}; + +static const struct udevice_id rk3188_pinctrl_ids[] = { + { .compatible = "rockchip,rk3188-pinctrl", + .data = (ulong)&rk3188_pin_ctrl }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3188) = { + .name = "rockchip_rk3188_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3188_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c new file mode 100644 index 0000000000..d2a6cd7055 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_route_data rk3228_mux_route_data[] = { + { + /* pwm0-0 */ + .bank_num = 0, + .pin = 26, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16), + }, { + /* pwm0-1 */ + .bank_num = 3, + .pin = 21, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16) | BIT(0), + }, { + /* pwm1-0 */ + .bank_num = 0, + .pin = 27, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 1), + }, { + /* pwm1-1 */ + .bank_num = 0, + .pin = 30, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 1) | BIT(1), + }, { + /* pwm2-0 */ + .bank_num = 0, + .pin = 28, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 2), + }, { + /* pwm2-1 */ + .bank_num = 1, + .pin = 12, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 2) | BIT(2), + }, { + /* pwm3-0 */ + .bank_num = 3, + .pin = 26, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 3), + }, { + /* pwm3-1 */ + .bank_num = 1, + .pin = 11, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 3) | BIT(3), + }, { + /* sdio-0_d0 */ + .bank_num = 1, + .pin = 1, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 4), + }, { + /* sdio-1_d0 */ + .bank_num = 3, + .pin = 2, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 4) | BIT(4), + }, { + /* spi-0_rx */ + .bank_num = 0, + .pin = 13, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 5), + }, { + /* spi-1_rx */ + .bank_num = 2, + .pin = 0, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 5) | BIT(5), + }, { + /* emmc-0_cmd */ + .bank_num = 1, + .pin = 22, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 7), + }, { + /* emmc-1_cmd */ + .bank_num = 2, + .pin = 4, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 7) | BIT(7), + }, { + /* uart2-0_rx */ + .bank_num = 1, + .pin = 19, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 8), + }, { + /* uart2-1_rx */ + .bank_num = 1, + .pin = 10, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 8) | BIT(8), + }, { + /* uart1-0_rx */ + .bank_num = 1, + .pin = 10, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 11), + }, { + /* uart1-1_rx */ + .bank_num = 3, + .pin = 13, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 11) | BIT(11), + }, +}; + +#define RK3228_PULL_OFFSET 0x100 + +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3228_PULL_OFFSET; + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +#define RK3228_DRV_GRF_OFFSET 0x200 + +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3228_DRV_GRF_OFFSET; + *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +} + +static struct rockchip_pin_bank rk3228_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { + .pin_banks = rk3228_pin_banks, + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .label = "RK3228-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .iomux_routes = rk3228_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, +}; + +static const struct udevice_id rk3228_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3228-pinctrl", + .data = (ulong)&rk3228_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3228) = { + .name = "rockchip_rk3228_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3228_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c new file mode 100644 index 0000000000..60585f3208 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_route_data rk3288_mux_route_data[] = { + { + /* edphdmi_cecinoutt1 */ + .bank_num = 7, + .pin = 16, + .func = 2, + .route_offset = 0x264, + .route_val = BIT(16 + 12) | BIT(12), + }, { + /* edphdmi_cecinout */ + .bank_num = 7, + .pin = 23, + .func = 4, + .route_offset = 0x264, + .route_val = BIT(16 + 12), + }, +}; + +#define RK3288_PULL_OFFSET 0x140 +#define RK3288_PULL_PMU_OFFSET 0x64 + +static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = priv->regmap_pmu; + *reg = RK3288_PULL_PMU_OFFSET; + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } else { + *regmap = priv->regmap_base; + *reg = RK3288_PULL_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } +} + +#define RK3288_DRV_PMU_OFFSET 0x70 +#define RK3288_DRV_GRF_OFFSET 0x1c0 + +static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = priv->regmap_pmu; + *reg = RK3288_DRV_PMU_OFFSET; + + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; + } else { + *regmap = priv->regmap_base; + *reg = RK3288_DRV_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; + } +} + +static struct rockchip_pin_bank rk3288_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_UNROUTED + ), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, + IOMUX_UNROUTED, + IOMUX_UNROUTED, + 0 + ), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0 + ), + PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, + 0, + 0, + IOMUX_UNROUTED + ), + PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), + PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, + 0, + IOMUX_WIDTH_4BIT, + IOMUX_UNROUTED + ), + PIN_BANK(8, 16, "gpio8"), +}; + +static struct rockchip_pin_ctrl rk3288_pin_ctrl = { + .pin_banks = rk3288_pin_banks, + .nr_banks = ARRAY_SIZE(rk3288_pin_banks), + .label = "RK3288-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x84, + .iomux_routes = rk3288_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), + .pull_calc_reg = rk3288_calc_pull_reg_and_bit, + .drv_calc_reg = rk3288_calc_drv_reg_and_bit, +}; + +static const struct udevice_id rk3288_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3288-pinctrl", + .data = (ulong)&rk3288_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3288) = { + .name = "rockchip_rk3288_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3288_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c new file mode 100644 index 0000000000..f1b3d10dbe --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { + { + .num = 2, + .pin = 12, + .reg = 0x24, + .bit = 8, + .mask = 0x3 + }, { + .num = 2, + .pin = 15, + .reg = 0x28, + .bit = 0, + .mask = 0x7 + }, { + .num = 2, + .pin = 23, + .reg = 0x30, + .bit = 14, + .mask = 0x3 + }, +}; + +static struct rockchip_mux_route_data rk3328_mux_route_data[] = { + { + /* uart2dbg_rxm0 */ + .bank_num = 1, + .pin = 1, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16) | BIT(16 + 1), + }, { + /* uart2dbg_rxm1 */ + .bank_num = 2, + .pin = 1, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16) | BIT(16 + 1) | BIT(0), + }, { + /* gmac-m1_rxd0 */ + .bank_num = 1, + .pin = 11, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 2) | BIT(2), + }, { + /* gmac-m1-optimized_rxd3 */ + .bank_num = 1, + .pin = 14, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 10) | BIT(10), + }, { + /* pdm_sdi0m0 */ + .bank_num = 2, + .pin = 19, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 3), + }, { + /* pdm_sdi0m1 */ + .bank_num = 1, + .pin = 23, + .func = 3, + .route_offset = 0x50, + .route_val = BIT(16 + 3) | BIT(3), + }, { + /* spi_rxdm2 */ + .bank_num = 3, + .pin = 2, + .func = 4, + .route_offset = 0x50, + .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), + }, { + /* i2s2_sdim0 */ + .bank_num = 1, + .pin = 24, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 6), + }, { + /* i2s2_sdim1 */ + .bank_num = 3, + .pin = 2, + .func = 6, + .route_offset = 0x50, + .route_val = BIT(16 + 6) | BIT(6), + }, { + /* card_iom1 */ + .bank_num = 2, + .pin = 22, + .func = 3, + .route_offset = 0x50, + .route_val = BIT(16 + 7) | BIT(7), + }, { + /* tsp_d5m1 */ + .bank_num = 2, + .pin = 16, + .func = 3, + .route_offset = 0x50, + .route_val = BIT(16 + 8) | BIT(8), + }, { + /* cif_data5m1 */ + .bank_num = 2, + .pin = 16, + .func = 4, + .route_offset = 0x50, + .route_val = BIT(16 + 9) | BIT(9), + }, +}; + +#define RK3328_PULL_OFFSET 0x100 + +static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3328_PULL_OFFSET; + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +#define RK3328_DRV_GRF_OFFSET 0x200 + +static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3328_DRV_GRF_OFFSET; + *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +} + +#define RK3328_SCHMITT_BITS_PER_PIN 1 +#define RK3328_SCHMITT_PINS_PER_REG 16 +#define RK3328_SCHMITT_BANK_STRIDE 8 +#define RK3328_SCHMITT_GRF_OFFSET 0x380 + +static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3328_SCHMITT_GRF_OFFSET; + + *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; + *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); + *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; + + return 0; +} + +static struct rockchip_pin_bank rk3328_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, + IOMUX_WIDTH_3BIT, + IOMUX_WIDTH_3BIT, + 0), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_3BIT, + IOMUX_WIDTH_3BIT, + 0, + 0), +}; + +static struct rockchip_pin_ctrl rk3328_pin_ctrl = { + .pin_banks = rk3328_pin_banks, + .nr_banks = ARRAY_SIZE(rk3328_pin_banks), + .label = "RK3328-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .iomux_recalced = rk3328_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), + .iomux_routes = rk3328_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), + .pull_calc_reg = rk3328_calc_pull_reg_and_bit, + .drv_calc_reg = rk3328_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, +}; + +static const struct udevice_id rk3328_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3328-pinctrl", + .data = (ulong)&rk3328_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3328) = { + .name = "rockchip_rk3328_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3328_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c new file mode 100644 index 0000000000..f5cd6ff24e --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +#define RK3368_PULL_GRF_OFFSET 0x100 +#define RK3368_PULL_PMU_OFFSET 0x10 + +static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = priv->regmap_pmu; + *reg = RK3368_PULL_PMU_OFFSET; + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } else { + *regmap = priv->regmap_base; + *reg = RK3368_PULL_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } +} + +#define RK3368_DRV_PMU_OFFSET 0x20 +#define RK3368_DRV_GRF_OFFSET 0x200 + +static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = priv->regmap_pmu; + *reg = RK3368_DRV_PMU_OFFSET; + + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; + } else { + *regmap = priv->regmap_base; + *reg = RK3368_DRV_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; + } +} + +static struct rockchip_pin_bank rk3368_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU + ), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3368_pin_ctrl = { + .pin_banks = rk3368_pin_banks, + .nr_banks = ARRAY_SIZE(rk3368_pin_banks), + .label = "RK3368-GPIO", + .type = RK3368, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x0, + .pull_calc_reg = rk3368_calc_pull_reg_and_bit, + .drv_calc_reg = rk3368_calc_drv_reg_and_bit, +}; + +static const struct udevice_id rk3368_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3368-pinctrl", + .data = (ulong)&rk3368_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3368) = { + .name = "rockchip_rk3368_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3368_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c new file mode 100644 index 0000000000..c5aab647a5 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_route_data rk3399_mux_route_data[] = { + { + /* uart2dbga_rx */ + .bank_num = 4, + .pin = 8, + .func = 2, + .route_offset = 0xe21c, + .route_val = BIT(16 + 10) | BIT(16 + 11), + }, { + /* uart2dbgb_rx */ + .bank_num = 4, + .pin = 16, + .func = 2, + .route_offset = 0xe21c, + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), + }, { + /* uart2dbgc_rx */ + .bank_num = 4, + .pin = 19, + .func = 1, + .route_offset = 0xe21c, + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), + }, { + /* pcie_clkreqn */ + .bank_num = 2, + .pin = 26, + .func = 2, + .route_offset = 0xe21c, + .route_val = BIT(16 + 14), + }, { + /* pcie_clkreqnb */ + .bank_num = 4, + .pin = 24, + .func = 1, + .route_offset = 0xe21c, + .route_val = BIT(16 + 14) | BIT(14), + }, +}; + +#define RK3399_PULL_GRF_OFFSET 0xe040 +#define RK3399_PULL_PMU_OFFSET 0x40 + +static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The bank0:16 and bank1:32 pins are located in PMU */ + if (bank->bank_num == 0 || bank->bank_num == 1) { + *regmap = priv->regmap_pmu; + *reg = RK3399_PULL_PMU_OFFSET; + + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } else { + *regmap = priv->regmap_base; + *reg = RK3399_PULL_GRF_OFFSET; + + /* correct the offset, as we're starting with the 3rd bank */ + *reg -= 0x20; + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + } +} + +static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int drv_num = (pin_num / 8); + + /* The bank0:16 and bank1:32 pins are located in PMU */ + if (bank->bank_num == 0 || bank->bank_num == 1) + *regmap = priv->regmap_pmu; + else + *regmap = priv->regmap_base; + + *reg = bank->drv[drv_num].offset; + if (bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO || + bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY) + *bit = (pin_num % 8) * 3; + else + *bit = (pin_num % 8) * 2; +} + +static struct rockchip_pin_bank rk3399_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + DRV_TYPE_IO_1V8_ONLY, + DRV_TYPE_IO_1V8_ONLY, + DRV_TYPE_IO_DEFAULT, + DRV_TYPE_IO_DEFAULT, + 0x80, + 0x88, + -1, + -1, + PULL_TYPE_IO_1V8_ONLY, + PULL_TYPE_IO_1V8_ONLY, + PULL_TYPE_IO_DEFAULT, + PULL_TYPE_IO_DEFAULT + ), + PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_OR_3V0, + 0xa0, + 0xa8, + 0xb0, + 0xb8 + ), + PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_ONLY, + DRV_TYPE_IO_1V8_ONLY, + PULL_TYPE_IO_DEFAULT, + PULL_TYPE_IO_DEFAULT, + PULL_TYPE_IO_1V8_ONLY, + PULL_TYPE_IO_1V8_ONLY + ), + PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, + DRV_TYPE_IO_3V3_ONLY, + DRV_TYPE_IO_3V3_ONLY, + DRV_TYPE_IO_1V8_OR_3V0 + ), + PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_3V0_AUTO, + DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_OR_3V0 + ), +}; + +static struct rockchip_pin_ctrl rk3399_pin_ctrl = { + .pin_banks = rk3399_pin_banks, + .nr_banks = ARRAY_SIZE(rk3399_pin_banks), + .label = "RK3399-GPIO", + .type = RK3399, + .grf_mux_offset = 0xe000, + .pmu_mux_offset = 0x0, + .grf_drv_offset = 0xe100, + .pmu_drv_offset = 0x80, + .iomux_routes = rk3399_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), + .pull_calc_reg = rk3399_calc_pull_reg_and_bit, + .drv_calc_reg = rk3399_calc_drv_reg_and_bit, +}; + +static const struct udevice_id rk3399_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3399-pinctrl", + .data = (ulong)&rk3399_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3399) = { + .name = "rockchip_rk3399_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3399_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c new file mode 100644 index 0000000000..b84b079064 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -0,0 +1,788 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> +#include <fdtdec.h> + +#include "pinctrl-rockchip.h" + +#define MAX_ROCKCHIP_PINS_ENTRIES 30 +#define MAX_ROCKCHIP_GPIO_PER_BANK 32 +#define RK_FUNC_GPIO 0 + +static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) +{ + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + + if (bank >= ctrl->nr_banks) { + debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); + return -EINVAL; + } + + if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { + debug("pin conf pin %d >= %d\n", pin, + MAX_ROCKCHIP_GPIO_PER_BANK); + return -EINVAL; + } + + return 0; +} + +static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, + int *reg, u8 *bit, int *mask) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + struct rockchip_mux_recalced_data *data; + int i; + + for (i = 0; i < ctrl->niomux_recalced; i++) { + data = &ctrl->iomux_recalced[i]; + if (data->num == bank->bank_num && + data->pin == pin) + break; + } + + if (i >= ctrl->niomux_recalced) + return; + + *reg = data->reg; + *mask = data->mask; + *bit = data->bit; +} + +static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + struct rockchip_mux_route_data *data; + int i; + + for (i = 0; i < ctrl->niomux_routes; i++) { + data = &ctrl->iomux_routes[i]; + if (data->bank_num == bank->bank_num && + data->pin == pin && data->func == mux) + break; + } + + if (i >= ctrl->niomux_routes) + return false; + + *reg = data->route_offset; + *value = data->route_val; + + return true; +} + +static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) +{ + int offset = 0; + + if (mux_type & IOMUX_WIDTH_4BIT) { + if ((pin % 8) >= 4) + offset = 0x4; + *bit = (pin % 4) * 4; + *mask = 0xf; + } else if (mux_type & IOMUX_WIDTH_3BIT) { + /* + * pin0 ~ pin4 are at first register, and + * pin5 ~ pin7 are at second register. + */ + if ((pin % 8) >= 5) + offset = 0x4; + *bit = (pin % 8 % 5) * 3; + *mask = 0x7; + } else { + *bit = (pin % 8) * 2; + *mask = 0x3; + } + + return offset; +} + +static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + unsigned int val; + int reg, ret, mask, mux_type; + u8 bit; + + if (iomux_num > 3) + return -EINVAL; + + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { + debug("pin %d is unrouted\n", pin); + return -EINVAL; + } + + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) + return RK_FUNC_GPIO; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + ret = regmap_read(regmap, reg, &val); + if (ret) + return ret; + + return ((val >> bit) & mask); +} + +static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, + int index) +{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + + return rockchip_get_mux(&ctrl->pin_banks[banknum], index); +} + +static int rockchip_verify_mux(struct rockchip_pin_bank *bank, + int pin, int mux) +{ + int iomux_num = (pin / 8); + + if (iomux_num > 3) + return -EINVAL; + + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { + debug("pin %d is unrouted\n", pin); + return -EINVAL; + } + + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { + if (mux != IOMUX_GPIO_ONLY) { + debug("pin %d only supports a gpio mux\n", pin); + return -ENOTSUPP; + } + } + + return 0; +} + +/* + * Set a new mux function for a pin. + * + * The register is divided into the upper and lower 16 bit. When changing + * a value, the previous register value is not read and changed. Instead + * it seems the changed bits are marked in the upper 16 bit, while the + * changed value gets set in the same offset in the lower 16 bit. + * All pin settings seem to be 2 bit wide in both the upper and lower + * parts. + * @bank: pin bank to change + * @pin: pin to change + * @mux: new mux function to set + */ +static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + ret = rockchip_verify_mux(bank, pin, mux); + if (ret < 0) + return ret; + + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) + return 0; + + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + +static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { + { 2, 4, 8, 12, -1, -1, -1, -1 }, + { 3, 6, 9, 12, -1, -1, -1, -1 }, + { 5, 10, 15, 20, -1, -1, -1, -1 }, + { 4, 6, 8, 10, 12, 14, 16, 18 }, + { 4, 7, 10, 13, 16, 19, 22, 26 } +}; + +static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + struct regmap *regmap; + int reg, ret, i; + u32 data, rmask_bits, temp; + u8 bit; + int drv_type = bank->drv[pin_num / 8].drv_type; + + debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, + pin_num, strength); + + ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); + + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { + if (rockchip_perpin_drv_list[drv_type][i] == strength) { + ret = i; + break; + } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { + ret = rockchip_perpin_drv_list[drv_type][i]; + break; + } + } + + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + switch (drv_type) { + case DRV_TYPE_IO_1V8_3V0_AUTO: + case DRV_TYPE_IO_3V3_ONLY: + rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; + switch (bit) { + case 0 ... 12: + /* regular case, nothing to do */ + break; + case 15: + /* + * drive-strength offset is special, as it is spread + * over 2 registers, the bit data[15] contains bit 0 + * of the value while temp[1:0] contains bits 2 and 1 + */ + data = (ret & 0x1) << 15; + temp = (ret >> 0x1) & 0x3; + + data |= BIT(31); + ret = regmap_write(regmap, reg, data); + if (ret) + return ret; + + temp |= (0x3 << 16); + reg += 0x4; + ret = regmap_write(regmap, reg, temp); + + return ret; + case 18 ... 21: + /* setting fully enclosed in the second register */ + reg += 4; + bit -= 16; + break; + default: + debug("unsupported bit: %d for pinctrl drive type: %d\n", + bit, drv_type); + return -EINVAL; + } + break; + case DRV_TYPE_IO_DEFAULT: + case DRV_TYPE_IO_1V8_OR_3V0: + case DRV_TYPE_IO_1V8_ONLY: + rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; + break; + default: + debug("unsupported pinctrl drive type: %d\n", + drv_type); + return -EINVAL; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + data |= (ret << bit); + + ret = regmap_write(regmap, reg, data); + return ret; +} + +static int rockchip_pull_list[PULL_TYPE_MAX][4] = { + { + PIN_CONFIG_BIAS_DISABLE, + PIN_CONFIG_BIAS_PULL_UP, + PIN_CONFIG_BIAS_PULL_DOWN, + PIN_CONFIG_BIAS_BUS_HOLD + }, + { + PIN_CONFIG_BIAS_DISABLE, + PIN_CONFIG_BIAS_PULL_DOWN, + PIN_CONFIG_BIAS_DISABLE, + PIN_CONFIG_BIAS_PULL_UP + }, +}; + +static int rockchip_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + struct regmap *regmap; + int reg, ret, i, pull_type; + u8 bit; + u32 data; + + debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, + pin_num, pull); + + ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); + + switch (ctrl->type) { + case RK3036: + case RK3128: + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + break; + case RV1108: + case RK3188: + case RK3288: + case RK3368: + case RK3399: + pull_type = bank->pull_type[pin_num / 8]; + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); + i++) { + if (rockchip_pull_list[pull_type][i] == pull) { + ret = i; + break; + } + } + + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + + ret = regmap_write(regmap, reg, data); + break; + default: + debug("unsupported pinctrl type\n"); + return -EINVAL; + } + + return ret; +} + +static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, + pin_num, enable); + + ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + + /* enable the write to the equivalent lower bits */ + data = BIT(bit + 16) | (enable << bit); + + return regmap_write(regmap, reg, data); +} + +/* + * Pinconf_ops handling + */ +static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, + unsigned int pull) +{ + switch (ctrl->type) { + case RK3036: + case RK3128: + return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || + pull == PIN_CONFIG_BIAS_DISABLE); + case RV1108: + case RK3188: + case RK3288: + case RK3368: + case RK3399: + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); + } + + return false; +} + +/* set the pin config settings for a specified pin */ +static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, + u32 pin, u32 param, u32 arg) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + int rc; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + rc = rockchip_set_pull(bank, pin, param); + if (rc) + return rc; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_BUS_HOLD: + if (!rockchip_pinconf_pull_valid(ctrl, param)) + return -ENOTSUPP; + + if (!arg) + return -EINVAL; + + rc = rockchip_set_pull(bank, pin, param); + if (rc) + return rc; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + if (!ctrl->drv_calc_reg) + return -ENOTSUPP; + + rc = rockchip_set_drive_perpin(bank, pin, arg); + if (rc < 0) + return rc; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!ctrl->schmitt_calc_reg) + return -ENOTSUPP; + + rc = rockchip_set_schmitt(bank, pin, arg); + if (rc < 0) + return rc; + break; + + default: + break; + } + + return 0; +} + +static const struct pinconf_param rockchip_conf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, +}; + +static int rockchip_pinconf_prop_name_to_param(const char *property, + u32 *default_value) +{ + const struct pinconf_param *p, *end; + + p = rockchip_conf_params; + end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); + + /* See if this pctldev supports this parameter */ + for (; p < end; p++) { + if (!strcmp(property, p->property)) { + *default_value = p->default_value; + return p->param; + } + } + + *default_value = 0; + return -EPERM; +} + +static int rockchip_pinctrl_set_state(struct udevice *dev, + struct udevice *config) +{ + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; + u32 bank, pin, mux, conf, arg, default_val; + int ret, count, i; + const char *prop_name; + const void *value; + int prop_len, param; + const u32 *data; + ofnode node; +#ifdef CONFIG_OF_LIVE + const struct device_node *np; + struct property *pp; +#else + int property_offset, pcfg_node; + const void *blob = gd->fdt_blob; +#endif + data = dev_read_prop(config, "rockchip,pins", &count); + if (count < 0) { + debug("%s: bad array size %d\n", __func__, count); + return -EINVAL; + } + + count /= sizeof(u32); + if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { + debug("%s: unsupported pins array count %d\n", + __func__, count); + return -EINVAL; + } + + for (i = 0; i < count; i++) + cells[i] = fdt32_to_cpu(data[i]); + + for (i = 0; i < (count >> 2); i++) { + bank = cells[4 * i + 0]; + pin = cells[4 * i + 1]; + mux = cells[4 * i + 2]; + conf = cells[4 * i + 3]; + + ret = rockchip_verify_config(dev, bank, pin); + if (ret) + return ret; + + ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); + if (ret) + return ret; + + node = ofnode_get_by_phandle(conf); + if (!ofnode_valid(node)) + return -ENODEV; +#ifdef CONFIG_OF_LIVE + np = ofnode_to_np(node); + for (pp = np->properties; pp; pp = pp->next) { + prop_name = pp->name; + prop_len = pp->length; + value = pp->value; +#else + pcfg_node = ofnode_to_offset(node); + fdt_for_each_property_offset(property_offset, blob, pcfg_node) { + value = fdt_getprop_by_offset(blob, property_offset, + &prop_name, &prop_len); + if (!value) + return -ENOENT; +#endif + param = rockchip_pinconf_prop_name_to_param(prop_name, + &default_val); + if (param < 0) + break; + + if (prop_len >= sizeof(fdt32_t)) + arg = fdt32_to_cpu(*(fdt32_t *)value); + else + arg = default_val; + + ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, + param, arg); + if (ret) { + debug("%s: rockchip_pinconf_set fail: %d\n", + __func__, ret); + return ret; + } + } + } + + return 0; +} + +const struct pinctrl_ops rockchip_pinctrl_ops = { + .set_state = rockchip_pinctrl_set_state, + .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, +}; + +/* retrieve the soc specific data */ +static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) +{ + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_ctrl *ctrl = + (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); + struct rockchip_pin_bank *bank; + int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; + + grf_offs = ctrl->grf_mux_offset; + pmu_offs = ctrl->pmu_mux_offset; + drv_pmu_offs = ctrl->pmu_drv_offset; + drv_grf_offs = ctrl->grf_drv_offset; + bank = ctrl->pin_banks; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + int bank_pins = 0; + + bank->priv = priv; + bank->pin_base = ctrl->nr_pins; + ctrl->nr_pins += bank->nr_pins; + + /* calculate iomux and drv offsets */ + for (j = 0; j < 4; j++) { + struct rockchip_iomux *iom = &bank->iomux[j]; + struct rockchip_drv *drv = &bank->drv[j]; + int inc; + + if (bank_pins >= bank->nr_pins) + break; + + /* preset iomux offset value, set new start value */ + if (iom->offset >= 0) { + if (iom->type & IOMUX_SOURCE_PMU) + pmu_offs = iom->offset; + else + grf_offs = iom->offset; + } else { /* set current iomux offset */ + iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? + pmu_offs : grf_offs; + } + + /* preset drv offset value, set new start value */ + if (drv->offset >= 0) { + if (iom->type & IOMUX_SOURCE_PMU) + drv_pmu_offs = drv->offset; + else + drv_grf_offs = drv->offset; + } else { /* set current drv offset */ + drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? + drv_pmu_offs : drv_grf_offs; + } + + debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", + i, j, iom->offset, drv->offset); + + /* + * Increase offset according to iomux width. + * 4bit iomux'es are spread over two registers. + */ + inc = (iom->type & (IOMUX_WIDTH_4BIT | + IOMUX_WIDTH_3BIT)) ? 8 : 4; + if (iom->type & IOMUX_SOURCE_PMU) + pmu_offs += inc; + else + grf_offs += inc; + + /* + * Increase offset according to drv width. + * 3bit drive-strenth'es are spread over two registers. + */ + if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || + (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) + inc = 8; + else + inc = 4; + + if (iom->type & IOMUX_SOURCE_PMU) + drv_pmu_offs += inc; + else + drv_grf_offs += inc; + + bank_pins += 8; + } + + /* calculate the per-bank recalced_mask */ + for (j = 0; j < ctrl->niomux_recalced; j++) { + int pin = 0; + + if (ctrl->iomux_recalced[j].num == bank->bank_num) { + pin = ctrl->iomux_recalced[j].pin; + bank->recalced_mask |= BIT(pin); + } + } + + /* calculate the per-bank route_mask */ + for (j = 0; j < ctrl->niomux_routes; j++) { + int pin = 0; + + if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { + pin = ctrl->iomux_routes[j].pin; + bank->route_mask |= BIT(pin); + } + } + } + + return ctrl; +} + +int rockchip_pinctrl_probe(struct udevice *dev) +{ + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_ctrl *ctrl; + struct udevice *syscon; + struct regmap *regmap; + int ret = 0; + + /* get rockchip grf syscon phandle */ + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", + &syscon); + if (ret) { + debug("unable to find rockchip,grf syscon device (%d)\n", ret); + return ret; + } + + /* get grf-reg base address */ + regmap = syscon_get_regmap(syscon); + if (!regmap) { + debug("unable to find rockchip grf regmap\n"); + return -ENODEV; + } + priv->regmap_base = regmap; + + /* option: get pmu-reg base address */ + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", + &syscon); + if (!ret) { + /* get pmugrf-reg base address */ + regmap = syscon_get_regmap(syscon); + if (!regmap) { + debug("unable to find rockchip pmu regmap\n"); + return -ENODEV; + } + priv->regmap_pmu = regmap; + } + + ctrl = rockchip_pinctrl_get_soc_data(dev); + if (!ctrl) { + debug("driver data not available\n"); + return -EINVAL; + } + + priv->ctrl = ctrl; + return 0; +} diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h new file mode 100644 index 0000000000..bc809630c1 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -0,0 +1,302 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __DRIVERS_PINCTRL_ROCKCHIP_H +#define __DRIVERS_PINCTRL_ROCKCHIP_H + +#include <linux/types.h> + +enum rockchip_pinctrl_type { + RV1108, + RK3036, + RK3128, + RK3188, + RK3288, + RK3368, + RK3399, +}; + +/** + * Encode variants of iomux registers into a type variable + */ +#define IOMUX_GPIO_ONLY BIT(0) +#define IOMUX_WIDTH_4BIT BIT(1) +#define IOMUX_SOURCE_PMU BIT(2) +#define IOMUX_UNROUTED BIT(3) +#define IOMUX_WIDTH_3BIT BIT(4) + +/** + * Defined some common pins constants + */ +#define ROCKCHIP_PULL_BITS_PER_PIN 2 +#define ROCKCHIP_PULL_PINS_PER_REG 8 +#define ROCKCHIP_PULL_BANK_STRIDE 16 +#define ROCKCHIP_DRV_BITS_PER_PIN 2 +#define ROCKCHIP_DRV_PINS_PER_REG 8 +#define ROCKCHIP_DRV_BANK_STRIDE 16 +#define ROCKCHIP_DRV_3BITS_PER_PIN 3 + +/** + * @type: iomux variant using IOMUX_* constants + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset + * to a new value for autocalculating the following iomux registers. + */ +struct rockchip_iomux { + int type; + int offset; +}; + +/** + * enum type index corresponding to rockchip_perpin_drv_list arrays index. + */ +enum rockchip_pin_drv_type { + DRV_TYPE_IO_DEFAULT = 0, + DRV_TYPE_IO_1V8_OR_3V0, + DRV_TYPE_IO_1V8_ONLY, + DRV_TYPE_IO_1V8_3V0_AUTO, + DRV_TYPE_IO_3V3_ONLY, + DRV_TYPE_MAX +}; + +/** + * enum type index corresponding to rockchip_pull_list arrays index. + */ +enum rockchip_pin_pull_type { + PULL_TYPE_IO_DEFAULT = 0, + PULL_TYPE_IO_1V8_ONLY, + PULL_TYPE_MAX +}; + +/** + * @drv_type: drive strength variant using rockchip_perpin_drv_type + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset + * to a new value for autocalculating the following drive strength + * registers. if used chips own cal_drv func instead to calculate + * registers offset, the variant could be ignored. + */ +struct rockchip_drv { + enum rockchip_pin_drv_type drv_type; + int offset; +}; + +/** + * @priv: common pinctrl private basedata + * @pin_base: first pin number + * @nr_pins: number of pins in this bank + * @name: name of the bank + * @bank_num: number of the bank, to account for holes + * @iomux: array describing the 4 iomux sources of the bank + * @drv: array describing the 4 drive strength sources of the bank + * @pull_type: array describing the 4 pull type sources of the bank + * @recalced_mask: bits describing the mux recalced pins of per bank + * @route_mask: bits describing the routing pins of per bank + */ +struct rockchip_pin_bank { + struct rockchip_pinctrl_priv *priv; + u32 pin_base; + u8 nr_pins; + char *name; + u8 bank_num; + struct rockchip_iomux iomux[4]; + struct rockchip_drv drv[4]; + enum rockchip_pin_pull_type pull_type[4]; + u32 recalced_mask; + u32 route_mask; +}; + +#define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + }, \ + } + +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ + }, \ + } + +#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + }, \ + .drv = { \ + { .drv_type = type0, .offset = -1 }, \ + { .drv_type = type1, .offset = -1 }, \ + { .drv_type = type2, .offset = -1 }, \ + { .drv_type = type3, .offset = -1 }, \ + }, \ + } + +#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ + drv2, drv3, pull0, pull1, \ + pull2, pull3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + .pull_type[0] = pull0, \ + .pull_type[1] = pull1, \ + .pull_type[2] = pull2, \ + .pull_type[3] = pull3, \ + } + +#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ + iom2, iom3, drv0, drv1, drv2, \ + drv3, offset0, offset1, \ + offset2, offset3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = offset0 }, \ + { .drv_type = drv1, .offset = offset1 }, \ + { .drv_type = drv2, .offset = offset2 }, \ + { .drv_type = drv3, .offset = offset3 }, \ + }, \ + } + +#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ + label, iom0, iom1, iom2, \ + iom3, drv0, drv1, drv2, \ + drv3, offset0, offset1, \ + offset2, offset3, pull0, \ + pull1, pull2, pull3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = offset0 }, \ + { .drv_type = drv1, .offset = offset1 }, \ + { .drv_type = drv2, .offset = offset2 }, \ + { .drv_type = drv3, .offset = offset3 }, \ + }, \ + .pull_type[0] = pull0, \ + .pull_type[1] = pull1, \ + .pull_type[2] = pull2, \ + .pull_type[3] = pull3, \ + } + +/** + * struct rockchip_mux_recalced_data: recalculate a pin iomux data. + * @num: bank number. + * @pin: pin number. + * @reg: register offset. + * @bit: index at register. + * @mask: mask bit + */ +struct rockchip_mux_recalced_data { + u8 num; + u8 pin; + u32 reg; + u8 bit; + u8 mask; +}; + +/** + * struct rockchip_mux_route_data: route a pin iomux data. + * @bank_num: bank number. + * @pin: index at register or used to calc index. + * @func: the min pin. + * @route_offset: the max pin. + * @route_val: the register offset. + */ +struct rockchip_mux_route_data { + u8 bank_num; + u8 pin; + u8 func; + u32 route_offset; + u32 route_val; +}; + +/** + */ +struct rockchip_pin_ctrl { + struct rockchip_pin_bank *pin_banks; + u32 nr_banks; + u32 nr_pins; + char *label; + enum rockchip_pinctrl_type type; + int grf_mux_offset; + int pmu_mux_offset; + int grf_drv_offset; + int pmu_drv_offset; + struct rockchip_mux_recalced_data *iomux_recalced; + u32 niomux_recalced; + struct rockchip_mux_route_data *iomux_routes; + u32 niomux_routes; + + void (*pull_calc_reg)(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit); + void (*drv_calc_reg)(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit); + int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit); +}; + +/** + */ +struct rockchip_pinctrl_priv { + struct rockchip_pin_ctrl *ctrl; + struct regmap *regmap_base; + struct regmap *regmap_pmu; +}; + +extern const struct pinctrl_ops rockchip_pinctrl_ops; +int rockchip_pinctrl_probe(struct udevice *dev); + +#endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c new file mode 100644 index 0000000000..f4a09a6824 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { + { + .num = 1, + .pin = 0, + .reg = 0x418, + .bit = 0, + .mask = 0x3 + }, { + .num = 1, + .pin = 1, + .reg = 0x418, + .bit = 2, + .mask = 0x3 + }, { + .num = 1, + .pin = 2, + .reg = 0x418, + .bit = 4, + .mask = 0x3 + }, { + .num = 1, + .pin = 3, + .reg = 0x418, + .bit = 6, + .mask = 0x3 + }, { + .num = 1, + .pin = 4, + .reg = 0x418, + .bit = 8, + .mask = 0x3 + }, { + .num = 1, + .pin = 5, + .reg = 0x418, + .bit = 10, + .mask = 0x3 + }, { + .num = 1, + .pin = 6, + .reg = 0x418, + .bit = 12, + .mask = 0x3 + }, { + .num = 1, + .pin = 7, + .reg = 0x418, + .bit = 14, + .mask = 0x3 + }, { + .num = 1, + .pin = 8, + .reg = 0x41c, + .bit = 0, + .mask = 0x3 + }, { + .num = 1, + .pin = 9, + .reg = 0x41c, + .bit = 2, + .mask = 0x3 + }, +}; + +#define RV1108_PULL_PMU_OFFSET 0x10 +#define RV1108_PULL_OFFSET 0x110 + +static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = priv->regmap_pmu; + *reg = RV1108_PULL_PMU_OFFSET; + } else { + *reg = RV1108_PULL_OFFSET; + *regmap = priv->regmap_base; + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; + } + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +#define RV1108_DRV_PMU_OFFSET 0x20 +#define RV1108_DRV_GRF_OFFSET 0x210 + +static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = priv->regmap_pmu; + *reg = RV1108_DRV_PMU_OFFSET; + } else { + *regmap = priv->regmap_base; + *reg = RV1108_DRV_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; + } + + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +} + +#define RV1108_SCHMITT_PMU_OFFSET 0x30 +#define RV1108_SCHMITT_GRF_OFFSET 0x388 +#define RV1108_SCHMITT_BANK_STRIDE 8 +#define RV1108_SCHMITT_PINS_PER_GRF_REG 16 +#define RV1108_SCHMITT_PINS_PER_PMU_REG 8 + +static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int pins_per_reg; + + if (bank->bank_num == 0) { + *regmap = priv->regmap_pmu; + *reg = RV1108_SCHMITT_PMU_OFFSET; + pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; + } else { + *regmap = priv->regmap_base; + *reg = RV1108_SCHMITT_GRF_OFFSET; + pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; + *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; + } + *reg += ((pin_num / pins_per_reg) * 4); + *bit = pin_num % pins_per_reg; + + return 0; +} + +static struct rockchip_pin_bank rv1108_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), +}; + +static struct rockchip_pin_ctrl rv1108_pin_ctrl = { + .pin_banks = rv1108_pin_banks, + .nr_banks = ARRAY_SIZE(rv1108_pin_banks), + .label = "RV1108-GPIO", + .type = RV1108, + .grf_mux_offset = 0x10, + .pmu_mux_offset = 0x0, + .iomux_recalced = rv1108_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), + .pull_calc_reg = rv1108_calc_pull_reg_and_bit, + .drv_calc_reg = rv1108_calc_drv_reg_and_bit, + .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, +}; + +static const struct udevice_id rv1108_pinctrl_ids[] = { + { + .compatible = "rockchip,rv1108-pinctrl", + .data = (ulong)&rv1108_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rv1108) = { + .name = "pinctrl_rv1108", + .id = UCLASS_PINCTRL, + .of_match = rv1108_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c deleted file mode 100644 index ecfeb31355..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c +++ /dev/null @@ -1,671 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinctrl driver for Rockchip 3036 SoCs - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3036.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <dm/pinctrl.h> - -/* GRF_GPIO0A_IOMUX */ -enum { - GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, - GPIO0A3_GPIO = 0, - GPIO0A3_I2C1_SDA, - - GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, - GPIO0A2_GPIO = 0, - GPIO0A2_I2C1_SCL, - - GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, - GPIO0A1_GPIO = 0, - GPIO0A1_I2C0_SDA, - GPIO0A1_PWM2, - - GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, - GPIO0A0_GPIO = 0, - GPIO0A0_I2C0_SCL, - GPIO0A0_PWM1, -}; - -/* GRF_GPIO0B_IOMUX */ -enum { - GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, - GPIO0B6_GPIO = 0, - GPIO0B6_MMC1_D3, - GPIO0B6_I2S1_SCLK, - - GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, - GPIO0B5_GPIO = 0, - GPIO0B5_MMC1_D2, - GPIO0B5_I2S1_SDI, - - GPIO0B4_SHIFT = 8, - GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, - GPIO0B4_GPIO = 0, - GPIO0B4_MMC1_D1, - GPIO0B4_I2S1_LRCKTX, - - GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, - GPIO0B3_GPIO = 0, - GPIO0B3_MMC1_D0, - GPIO0B3_I2S1_LRCKRX, - - GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, - GPIO0B1_GPIO = 0, - GPIO0B1_MMC1_CLKOUT, - GPIO0B1_I2S1_MCLK, - - GPIO0B0_SHIFT = 0, - GPIO0B0_MASK = 3, - GPIO0B0_GPIO = 0, - GPIO0B0_MMC1_CMD, - GPIO0B0_I2S1_SDO, -}; - -/* GRF_GPIO0C_IOMUX */ -enum { - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, - GPIO0C4_GPIO = 0, - GPIO0C4_DRIVE_VBUS, - - GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, - GPIO0C3_GPIO = 0, - GPIO0C3_UART0_CTSN, - - GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, - GPIO0C2_GPIO = 0, - GPIO0C2_UART0_RTSN, - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, - GPIO0C1_GPIO = 0, - GPIO0C1_UART0_SIN, - - - GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, - GPIO0C0_GPIO = 0, - GPIO0C0_UART0_SOUT, -}; - -/* GRF_GPIO0D_IOMUX */ -enum { - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_SPDIF, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_PWM3, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_PWM0, -}; - -/* GRF_GPIO1A_IOMUX */ -enum { - GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, - GPIO1A5_GPIO = 0, - GPIO1A5_I2S_SDI, - - GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, - GPIO1A4_GPIO = 0, - GPIO1A4_I2S_SD0, - - GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, - GPIO1A3_GPIO = 0, - GPIO1A3_I2S_LRCKTX, - - GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, - GPIO1A2_GPIO = 0, - GPIO1A2_I2S_LRCKRX, - GPIO1A2_PWM1_0, - - GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, - GPIO1A1_GPIO = 0, - GPIO1A1_I2S_SCLK, - - GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, - GPIO1A0_GPIO = 0, - GPIO1A0_I2S_MCLK, - -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, - GPIO1B7_GPIO = 0, - GPIO1B7_MMC0_CMD, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, - GPIO1B3_GPIO = 0, - GPIO1B3_HDMI_HPD, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_HDMI_SCL, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_HDMI_SDA, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, - GPIO1B0_GPIO = 0, - GPIO1B0_HDMI_CEC, -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, - GPIO1C5_GPIO = 0, - GPIO1C5_MMC0_D3, - GPIO1C5_JTAG_TMS, - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, - GPIO1C4_GPIO = 0, - GPIO1C4_MMC0_D2, - GPIO1C4_JTAG_TCK, - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, - GPIO1C3_GPIO = 0, - GPIO1C3_MMC0_D1, - GPIO1C3_UART2_SOUT, - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , - GPIO1C2_GPIO = 0, - GPIO1C2_MMC0_D0, - GPIO1C2_UART2_SIN, - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, - GPIO1C1_GPIO = 0, - GPIO1C1_MMC0_DETN, - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, - GPIO1C0_GPIO = 0, - GPIO1C0_MMC0_CLKOUT, -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, - GPIO1D7_GPIO = 0, - GPIO1D7_NAND_D7, - GPIO1D7_EMMC_D7, - GPIO1D7_SPI_CSN1, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, - GPIO1D6_GPIO = 0, - GPIO1D6_NAND_D6, - GPIO1D6_EMMC_D6, - GPIO1D6_SPI_CSN0, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, - GPIO1D5_GPIO = 0, - GPIO1D5_NAND_D5, - GPIO1D5_EMMC_D5, - GPIO1D5_SPI_TXD, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, - GPIO1D4_GPIO = 0, - GPIO1D4_NAND_D4, - GPIO1D4_EMMC_D4, - GPIO1D4_SPI_RXD, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_NAND_D3, - GPIO1D3_EMMC_D3, - GPIO1D3_SFC_SIO3, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_NAND_D2, - GPIO1D2_EMMC_D2, - GPIO1D2_SFC_SIO2, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, - GPIO1D1_GPIO = 0, - GPIO1D1_NAND_D1, - GPIO1D1_EMMC_D1, - GPIO1D1_SFC_SIO1, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, - GPIO1D0_GPIO = 0, - GPIO1D0_NAND_D0, - GPIO1D0_EMMC_D0, - GPIO1D0_SFC_SIO0, -}; - -/* GRF_GPIO2A_IOMUX */ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_TESTCLK_OUT, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_NAND_CS0, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_NAND_RDY, - GPIO2A4_EMMC_CMD, - GPIO2A3_SFC_CLK, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_NAND_RDN, - GPIO2A4_SFC_CSN1, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_NAND_WRN, - GPIO2A4_SFC_CSN0, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_NAND_CLE, - GPIO2A1_EMMC_CLKOUT, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_NAND_ALE, - GPIO2A0_SPI_CLK, -}; - -/* GRF_GPIO2B_IOMUX */ -enum { - GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, - GPIO2B7_GPIO = 0, - GPIO2B7_MAC_RXER, - - GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, - GPIO2B6_GPIO = 0, - GPIO2B6_MAC_CLKOUT, - GPIO2B6_MAC_CLKIN, - - GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, - GPIO2B5_GPIO = 0, - GPIO2B5_MAC_TXEN, - - GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, - GPIO2B4_GPIO = 0, - GPIO2B4_MAC_MDIO, - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, - GPIO2B2_GPIO = 0, - GPIO2B2_MAC_CRS, -}; - -/* GRF_GPIO2C_IOMUX */ -enum { - GPIO2C7_SHIFT = 14, - GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, - GPIO2C7_GPIO = 0, - GPIO2C7_UART1_SOUT, - GPIO2C7_TESTCLK_OUT1, - - GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, - GPIO2C6_GPIO = 0, - GPIO2C6_UART1_SIN, - - GPIO2C5_SHIFT = 10, - GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, - GPIO2C5_GPIO = 0, - GPIO2C5_I2C2_SCL, - - GPIO2C4_SHIFT = 8, - GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, - GPIO2C4_GPIO = 0, - GPIO2C4_I2C2_SDA, - - GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, - GPIO2C3_GPIO = 0, - GPIO2C3_MAC_TXD0, - - GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, - GPIO2C2_GPIO = 0, - GPIO2C2_MAC_TXD1, - - GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, - GPIO2C1_GPIO = 0, - GPIO2C1_MAC_RXD0, - - GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, - GPIO2C0_GPIO = 0, - GPIO2C0_MAC_RXD1, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_I2S_SDO1, - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, - GPIO2D5_GPIO = 0, - GPIO2D5_I2S_SDO2, - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, - GPIO2D4_GPIO = 0, - GPIO2D4_I2S_SDO3, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_MAC_MDC, -}; - -struct rk3036_pinctrl_priv { - struct rk3036_grf *grf; -}; - -static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id) -{ - switch (pwm_id) { - case PERIPH_ID_PWM0: - rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, - GPIO0D2_PWM0 << GPIO0D2_SHIFT); - break; - case PERIPH_ID_PWM1: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK, - GPIO0A0_PWM1 << GPIO0A0_SHIFT); - break; - case PERIPH_ID_PWM2: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK, - GPIO0A1_PWM2 << GPIO0A1_SHIFT); - break; - case PERIPH_ID_PWM3: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK, - GPIO0D3_PWM3 << GPIO0D3_SHIFT); - break; - default: - debug("pwm id = %d iomux error!\n", pwm_id); - break; - } -} - -static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id) -{ - switch (i2c_id) { - case PERIPH_ID_I2C0: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A1_MASK | GPIO0A0_MASK, - GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | - GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); - - break; - case PERIPH_ID_I2C1: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A3_MASK | GPIO0A2_MASK, - GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | - GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); - break; - case PERIPH_ID_I2C2: - rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C5_MASK | GPIO2C4_MASK, - GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | - GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); - - break; - } -} - -static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs) -{ - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK, - GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK, - GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT); - break; - } - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D5_MASK | GPIO1D4_MASK, - GPIO1D5_SPI_TXD << GPIO1D5_SHIFT | - GPIO1D4_SPI_RXD << GPIO1D4_SHIFT); - - rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK, - GPIO2A0_SPI_CLK << GPIO2A0_SHIFT); -} - -static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) -{ - switch (uart_id) { - case PERIPH_ID_UART0: - rk_clrsetreg(&grf->gpio0c_iomux, - GPIO0C3_MASK | GPIO0C2_MASK | - GPIO0C1_MASK | GPIO0C0_MASK, - GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT | - GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT | - GPIO0C1_UART0_SIN << GPIO0C1_SHIFT | - GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT); - break; - case PERIPH_ID_UART1: - rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C7_MASK | GPIO2C6_MASK, - GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT | - GPIO2C6_UART1_SIN << GPIO2C6_SHIFT); - break; - case PERIPH_ID_UART2: - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C3_MASK | GPIO1C2_MASK, - GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | - GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); - break; - } -} - -static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id) -{ - switch (mmc_id) { - case PERIPH_ID_EMMC: - rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, - GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | - GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | - GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | - GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | - GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | - GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | - GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | - GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A4_MASK | GPIO2A1_MASK, - GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT | - GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT); - break; - case PERIPH_ID_SDCARD: - rk_clrsetreg(&grf->gpio1c_iomux, 0xffff, - GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT | - GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT | - GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT | - GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT | - GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT | - GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT); - break; - } -} - -static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%x, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - pinctrl_rk3036_pwm_config(priv->grf, func); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - pinctrl_rk3036_i2c_config(priv->grf, func); - break; - case PERIPH_ID_SPI0: - pinctrl_rk3036_spi_config(priv->grf, flags); - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - pinctrl_rk3036_uart_config(priv->grf, func); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - pinctrl_rk3036_sdmmc_config(priv->grf, func); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int rk3036_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ - u32 cell[3]; - int ret; - - ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 14: - return PERIPH_ID_SDCARD; - case 16: - return PERIPH_ID_EMMC; - case 20: - return PERIPH_ID_UART0; - case 21: - return PERIPH_ID_UART1; - case 22: - return PERIPH_ID_UART2; - case 23: - return PERIPH_ID_SPI0; - case 24: - return PERIPH_ID_I2C0; - case 25: - return PERIPH_ID_I2C1; - case 26: - return PERIPH_ID_I2C2; - case 30: - return PERIPH_ID_PWM0; - } - return -ENOENT; -} - -static int rk3036_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk3036_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - return rk3036_pinctrl_request(dev, func, 0); -} - -static struct pinctrl_ops rk3036_pinctrl_ops = { - .set_state_simple = rk3036_pinctrl_set_state_simple, - .request = rk3036_pinctrl_request, - .get_periph_id = rk3036_pinctrl_get_periph_id, -}; - -static int rk3036_pinctrl_probe(struct udevice *dev) -{ - struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - debug("%s: grf=%p\n", __func__, priv->grf); - return 0; -} - -static const struct udevice_id rk3036_pinctrl_ids[] = { - { .compatible = "rockchip,rk3036-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3036) = { - .name = "pinctrl_rk3036", - .id = UCLASS_PINCTRL, - .of_match = rk3036_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv), - .ops = &rk3036_pinctrl_ops, - .bind = dm_scan_fdt_dev, - .probe = rk3036_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3128.c b/drivers/pinctrl/rockchip/pinctrl_rk3128.c deleted file mode 100644 index 8b87f74d16..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk3128.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinctrl driver for Rockchip 3128 SoCs - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3128.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <dm/pinctrl.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct rk3128_pinctrl_priv { - struct rk3128_grf *grf; -}; - -static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id) -{ - switch (i2c_id) { - case PERIPH_ID_I2C0: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A1_MASK | GPIO0A0_MASK, - GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | - GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); - - break; - case PERIPH_ID_I2C1: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A3_MASK | GPIO0A2_MASK, - GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | - GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); - break; - case PERIPH_ID_I2C2: - rk_clrsetreg(&grf->gpio2c_iomux2, - GPIO2C5_MASK | GPIO2C4_MASK, - GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | - GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); - break; - case PERIPH_ID_I2C3: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A7_MASK | GPIO0A6_MASK, - GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT | - GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT); - - break; - } -} - -static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id) -{ - switch (mmc_id) { - case PERIPH_ID_EMMC: - rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, - GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | - GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | - GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | - GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | - GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | - GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | - GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | - GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A5_MASK | GPIO2A7_MASK, - GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT | - GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT); - break; - case PERIPH_ID_SDCARD: - rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff, - GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT | - GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT | - GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT | - GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT | - GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT | - GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT); - break; - } -} - -static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk3128_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%x, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - pinctrl_rk3128_i2c_config(priv->grf, func); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - pinctrl_rk3128_sdmmc_config(priv->grf, func); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int rk3128_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ - u32 cell[3]; - int ret; - - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 14: - return PERIPH_ID_SDCARD; - case 16: - return PERIPH_ID_EMMC; - case 20: - return PERIPH_ID_UART0; - case 21: - return PERIPH_ID_UART1; - case 22: - return PERIPH_ID_UART2; - case 23: - return PERIPH_ID_SPI0; - case 24: - return PERIPH_ID_I2C0; - case 25: - return PERIPH_ID_I2C1; - case 26: - return PERIPH_ID_I2C2; - case 27: - return PERIPH_ID_I2C3; - case 30: - return PERIPH_ID_PWM0; - } - return -ENOENT; -} - -static int rk3128_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk3128_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - return rk3128_pinctrl_request(dev, func, 0); -} - -static struct pinctrl_ops rk3128_pinctrl_ops = { - .set_state_simple = rk3128_pinctrl_set_state_simple, - .request = rk3128_pinctrl_request, - .get_periph_id = rk3128_pinctrl_get_periph_id, -}; - -static int rk3128_pinctrl_probe(struct udevice *dev) -{ - struct rk3128_pinctrl_priv *priv = dev_get_priv(dev); - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - debug("%s: grf=%p\n", __func__, priv->grf); - return 0; -} - -static const struct udevice_id rk3128_pinctrl_ids[] = { - { .compatible = "rockchip,rk3128-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3128) = { - .name = "pinctrl_rk3128", - .id = UCLASS_PINCTRL, - .of_match = rk3128_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv), - .ops = &rk3128_pinctrl_ops, - .bind = dm_scan_fdt_dev, - .probe = rk3128_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c deleted file mode 100644 index 4612279656..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c +++ /dev/null @@ -1,989 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinctrl driver for Rockchip RK3188 SoCs - * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3188.h> -#include <dm/pinctrl.h> -#include <dm/root.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* GRF_GPIO0D_IOMUX */ -enum { - GPIO0D7_SHIFT = 14, - GPIO0D7_MASK = 1, - GPIO0D7_GPIO = 0, - GPIO0D7_SPI1_CSN0, - - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = 1, - GPIO0D6_GPIO = 0, - GPIO0D6_SPI1_CLK, - - GPIO0D5_SHIFT = 10, - GPIO0D5_MASK = 1, - GPIO0D5_GPIO = 0, - GPIO0D5_SPI1_TXD, - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1, - GPIO0D4_GPIO = 0, - GPIO0D4_SPI0_RXD, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 3, - GPIO0D3_GPIO = 0, - GPIO0D3_FLASH_CSN3, - GPIO0D3_EMMC_RSTN_OUT, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 3, - GPIO0D2_GPIO = 0, - GPIO0D2_FLASH_CSN2, - GPIO0D2_EMMC_CMD, - - GPIO0D1_SHIFT = 2, - GPIO0D1_MASK = 1, - GPIO0D1_GPIO = 0, - GPIO0D1_FLASH_CSN1, - - GPIO0D0_SHIFT = 0, - GPIO0D0_MASK = 3, - GPIO0D0_GPIO = 0, - GPIO0D0_FLASH_DQS, - GPIO0D0_EMMC_CLKOUT -}; - -/* GRF_GPIO1A_IOMUX */ -enum { - GPIO1A7_SHIFT = 14, - GPIO1A7_MASK = 3, - GPIO1A7_GPIO = 0, - GPIO1A7_UART1_RTS_N, - GPIO1A7_SPI0_CSN0, - - GPIO1A6_SHIFT = 12, - GPIO1A6_MASK = 3, - GPIO1A6_GPIO = 0, - GPIO1A6_UART1_CTS_N, - GPIO1A6_SPI0_CLK, - - GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 3, - GPIO1A5_GPIO = 0, - GPIO1A5_UART1_SOUT, - GPIO1A5_SPI0_TXD, - - GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 3, - GPIO1A4_GPIO = 0, - GPIO1A4_UART1_SIN, - GPIO1A4_SPI0_RXD, - - GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1, - GPIO1A3_GPIO = 0, - GPIO1A3_UART0_RTS_N, - - GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 1, - GPIO1A2_GPIO = 0, - GPIO1A2_UART0_CTS_N, - - GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 1, - GPIO1A1_GPIO = 0, - GPIO1A1_UART0_SOUT, - - GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 1, - GPIO1A0_GPIO = 0, - GPIO1A0_UART0_SIN, -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1, - GPIO1B7_GPIO = 0, - GPIO1B7_SPI0_CSN1, - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = 3, - GPIO1B6_GPIO = 0, - GPIO1B6_SPDIF_TX, - GPIO1B6_SPI1_CSN1, - - GPIO1B5_SHIFT = 10, - GPIO1B5_MASK = 3, - GPIO1B5_GPIO = 0, - GPIO1B5_UART3_RTS_N, - GPIO1B5_RESERVED, - - GPIO1B4_SHIFT = 8, - GPIO1B4_MASK = 3, - GPIO1B4_GPIO = 0, - GPIO1B4_UART3_CTS_N, - GPIO1B4_GPS_RFCLK, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 3, - GPIO1B3_GPIO = 0, - GPIO1B3_UART3_SOUT, - GPIO1B3_GPS_SIG, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3, - GPIO1B2_GPIO = 0, - GPIO1B2_UART3_SIN, - GPIO1B2_GPS_MAG, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3, - GPIO1B1_GPIO = 0, - GPIO1B1_UART2_SOUT, - GPIO1B1_JTAG_TDO, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 3, - GPIO1B0_GPIO = 0, - GPIO1B0_UART2_SIN, - GPIO1B0_JTAG_TDI, -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 1, - GPIO1D7_GPIO = 0, - GPIO1D7_I2C4_SCL, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 1, - GPIO1D6_GPIO = 0, - GPIO1D6_I2C4_SDA, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 1, - GPIO1D5_GPIO = 0, - GPIO1D5_I2C2_SCL, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 1, - GPIO1D4_GPIO = 0, - GPIO1D4_I2C2_SDA, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 1, - GPIO1D3_GPIO = 0, - GPIO1D3_I2C1_SCL, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 1, - GPIO1D2_GPIO = 0, - GPIO1D2_I2C1_SDA, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 1, - GPIO1D1_GPIO = 0, - GPIO1D1_I2C0_SCL, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 1, - GPIO1D0_GPIO = 0, - GPIO1D0_I2C0_SDA, -}; - -/* GRF_GPIO3A_IOMUX */ -enum { - GPIO3A7_SHIFT = 14, - GPIO3A7_MASK = 1, - GPIO3A7_GPIO = 0, - GPIO3A7_SDMMC0_DATA3, - - GPIO3A6_SHIFT = 12, - GPIO3A6_MASK = 1, - GPIO3A6_GPIO = 0, - GPIO3A6_SDMMC0_DATA2, - - GPIO3A5_SHIFT = 10, - GPIO3A5_MASK = 1, - GPIO3A5_GPIO = 0, - GPIO3A5_SDMMC0_DATA1, - - GPIO3A4_SHIFT = 8, - GPIO3A4_MASK = 1, - GPIO3A4_GPIO = 0, - GPIO3A4_SDMMC0_DATA0, - - GPIO3A3_SHIFT = 6, - GPIO3A3_MASK = 1, - GPIO3A3_GPIO = 0, - GPIO3A3_SDMMC0_CMD, - - GPIO3A2_SHIFT = 4, - GPIO3A2_MASK = 1, - GPIO3A2_GPIO = 0, - GPIO3A2_SDMMC0_CLKOUT, - - GPIO3A1_SHIFT = 2, - GPIO3A1_MASK = 1, - GPIO3A1_GPIO = 0, - GPIO3A1_SDMMC0_PWREN, - - GPIO3A0_SHIFT = 0, - GPIO3A0_MASK = 1, - GPIO3A0_GPIO = 0, - GPIO3A0_SDMMC0_RSTN, -}; - -/* GRF_GPIO3B_IOMUX */ -enum { - GPIO3B7_SHIFT = 14, - GPIO3B7_MASK = 3, - GPIO3B7_GPIO = 0, - GPIO3B7_CIF_DATA11, - GPIO3B7_I2C3_SCL, - - GPIO3B6_SHIFT = 12, - GPIO3B6_MASK = 3, - GPIO3B6_GPIO = 0, - GPIO3B6_CIF_DATA10, - GPIO3B6_I2C3_SDA, - - GPIO3B5_SHIFT = 10, - GPIO3B5_MASK = 3, - GPIO3B5_GPIO = 0, - GPIO3B5_CIF_DATA1, - GPIO3B5_HSADC_DATA9, - - GPIO3B4_SHIFT = 8, - GPIO3B4_MASK = 3, - GPIO3B4_GPIO = 0, - GPIO3B4_CIF_DATA0, - GPIO3B4_HSADC_DATA8, - - GPIO3B3_SHIFT = 6, - GPIO3B3_MASK = 1, - GPIO3B3_GPIO = 0, - GPIO3B3_CIF_CLKOUT, - - GPIO3B2_SHIFT = 4, - GPIO3B2_MASK = 1, - GPIO3B2_GPIO = 0, - /* no muxes */ - - GPIO3B1_SHIFT = 2, - GPIO3B1_MASK = 1, - GPIO3B1_GPIO = 0, - GPIO3B1_SDMMC0_WRITE_PRT, - - GPIO3B0_SHIFT = 0, - GPIO3B0_MASK = 1, - GPIO3B0_GPIO = 0, - GPIO3B0_SDMMC_DETECT_N, -}; - -/* GRF_GPIO3C_IOMUX */ -enum { - GPIO3C7_SHIFT = 14, - GPIO3C7_MASK = 3, - GPIO3C7_GPIO = 0, - GPIO3C7_SDMMC1_WRITE_PRT, - GPIO3C7_RMII_CRS_DVALID, - GPIO3C7_RESERVED, - - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 3, - GPIO3C6_GPIO = 0, - GPIO3C6_SDMMC1_DECTN, - GPIO3C6_RMII_RX_ERR, - GPIO3C6_RESERVED, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 3, - GPIO3C5_GPIO = 0, - GPIO3C5_SDMMC1_CLKOUT, - GPIO3C5_RMII_CLKOUT, - GPIO3C5_RMII_CLKIN, - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = 3, - GPIO3C4_GPIO = 0, - GPIO3C4_SDMMC1_DATA3, - GPIO3C4_RMII_RXD1, - GPIO3C4_RESERVED, - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = 3, - GPIO3C3_GPIO = 0, - GPIO3C3_SDMMC1_DATA2, - GPIO3C3_RMII_RXD0, - GPIO3C3_RESERVED, - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3, - GPIO3C2_GPIO = 0, - GPIO3C2_SDMMC1_DATA1, - GPIO3C2_RMII_TXD0, - GPIO3C2_RESERVED, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3, - GPIO3C1_GPIO = 0, - GPIO3C1_SDMMC1_DATA0, - GPIO3C1_RMII_TXD1, - GPIO3C1_RESERVED, - - GPIO3C0_SHIFT = 0, - GPIO3C0_MASK = 3, - GPIO3C0_GPIO = 0, - GPIO3C0_SDMMC1_CMD, - GPIO3C0_RMII_TX_EN, - GPIO3C0_RESERVED, -}; - -/* GRF_GPIO3D_IOMUX */ -enum { - GPIO3D6_SHIFT = 12, - GPIO3D6_MASK = 3, - GPIO3D6_GPIO = 0, - GPIO3D6_PWM_3, - GPIO3D6_JTAG_TMS, - GPIO3D6_HOST_DRV_VBUS, - - GPIO3D5_SHIFT = 10, - GPIO3D5_MASK = 3, - GPIO3D5_GPIO = 0, - GPIO3D5_PWM_2, - GPIO3D5_JTAG_TCK, - GPIO3D5_OTG_DRV_VBUS, - - GPIO3D4_SHIFT = 8, - GPIO3D4_MASK = 3, - GPIO3D4_GPIO = 0, - GPIO3D4_PWM_1, - GPIO3D4_JTAG_TRSTN, - - GPIO3D3_SHIFT = 6, - GPIO3D3_MASK = 3, - GPIO3D3_GPIO = 0, - GPIO3D3_PWM_0, - - GPIO3D2_SHIFT = 4, - GPIO3D2_MASK = 3, - GPIO3D2_GPIO = 0, - GPIO3D2_SDMMC1_INT_N, - - GPIO3D1_SHIFT = 2, - GPIO3D1_MASK = 3, - GPIO3D1_GPIO = 0, - GPIO3D1_SDMMC1_BACKEND_PWR, - GPIO3D1_MII_MDCLK, - - GPIO3D0_SHIFT = 0, - GPIO3D0_MASK = 3, - GPIO3D0_GPIO = 0, - GPIO3D0_SDMMC1_PWR_EN, - GPIO3D0_MII_MD, -}; - -struct rk3188_pinctrl_priv { - struct rk3188_grf *grf; - struct rk3188_pmu *pmu; - int num_banks; -}; - -/** - * Encode variants of iomux registers into a type variable - */ -#define IOMUX_GPIO_ONLY BIT(0) - -/** - * @type: iomux variant using IOMUX_* constants - * @offset: if initialized to -1 it will be autocalculated, by specifying - * an initial offset value the relevant source offset can be reset - * to a new value for autocalculating the following iomux registers. - */ -struct rockchip_iomux { - u8 type; - s16 offset; -}; - -/** - * @reg: register offset of the gpio bank - * @nr_pins: number of pins in this bank - * @bank_num: number of the bank, to account for holes - * @name: name of the bank - * @iomux: array describing the 4 iomux sources of the bank - */ -struct rockchip_pin_bank { - u16 reg; - u8 nr_pins; - u8 bank_num; - char *name; - struct rockchip_iomux iomux[4]; -}; - -#define PIN_BANK(id, pins, label) \ - { \ - .bank_num = id, \ - .nr_pins = pins, \ - .name = label, \ - .iomux = { \ - { .offset = -1 }, \ - { .offset = -1 }, \ - { .offset = -1 }, \ - { .offset = -1 }, \ - }, \ - } - -#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ - { \ - .bank_num = id, \ - .nr_pins = pins, \ - .name = label, \ - .iomux = { \ - { .type = iom0, .offset = -1 }, \ - { .type = iom1, .offset = -1 }, \ - { .type = iom2, .offset = -1 }, \ - { .type = iom3, .offset = -1 }, \ - }, \ - } - -#ifndef CONFIG_SPL_BUILD -static struct rockchip_pin_bank rk3188_pin_banks[] = { - PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), - PIN_BANK(1, 32, "gpio1"), - PIN_BANK(2, 32, "gpio2"), - PIN_BANK(3, 32, "gpio3"), -}; -#endif - -static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id) -{ - switch (pwm_id) { - case PERIPH_ID_PWM0: - rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT, - GPIO3D3_PWM_0 << GPIO3D3_SHIFT); - break; - case PERIPH_ID_PWM1: - rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT, - GPIO3D4_PWM_1 << GPIO3D4_SHIFT); - break; - case PERIPH_ID_PWM2: - rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT, - GPIO3D5_PWM_2 << GPIO3D5_SHIFT); - break; - case PERIPH_ID_PWM3: - rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT, - GPIO3D6_PWM_3 << GPIO3D6_SHIFT); - break; - default: - debug("pwm id = %d iomux error!\n", pwm_id); - break; - } -} - -static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf, - struct rk3188_pmu *pmu, int i2c_id) -{ - switch (i2c_id) { - case PERIPH_ID_I2C0: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D1_MASK << GPIO1D1_SHIFT | - GPIO1D0_MASK << GPIO1D0_SHIFT, - GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT | - GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT); - /* enable new i2c controller */ - rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, - 1 << RKI2C0_SEL_SHIFT); - break; - case PERIPH_ID_I2C1: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D3_MASK << GPIO1D3_SHIFT | - GPIO1D2_MASK << GPIO1D2_SHIFT, - GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT | - GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT); - rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT, - 1 << RKI2C1_SEL_SHIFT); - break; - case PERIPH_ID_I2C2: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D5_MASK << GPIO1D5_SHIFT | - GPIO1D4_MASK << GPIO1D4_SHIFT, - GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT | - GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT); - rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT, - 1 << RKI2C2_SEL_SHIFT); - break; - case PERIPH_ID_I2C3: - rk_clrsetreg(&grf->gpio3b_iomux, - GPIO3B7_MASK << GPIO3B7_SHIFT | - GPIO3B6_MASK << GPIO3B6_SHIFT, - GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT | - GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT); - rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT, - 1 << RKI2C3_SEL_SHIFT); - break; - case PERIPH_ID_I2C4: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D7_MASK << GPIO1D7_SHIFT | - GPIO1D6_MASK << GPIO1D6_SHIFT, - GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT | - GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT); - rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT, - 1 << RKI2C4_SEL_SHIFT); - break; - default: - debug("i2c id = %d iomux error!\n", i2c_id); - break; - } -} - -static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf, - enum periph_id spi_id, int cs) -{ - switch (spi_id) { - case PERIPH_ID_SPI0: - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio1a_iomux, - GPIO1A7_MASK << GPIO1A7_SHIFT, - GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B7_MASK << GPIO1B7_SHIFT, - GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT); - break; - default: - goto err; - } - rk_clrsetreg(&grf->gpio1a_iomux, - GPIO1A4_MASK << GPIO1A4_SHIFT | - GPIO1A5_MASK << GPIO1A5_SHIFT | - GPIO1A6_MASK << GPIO1A6_SHIFT, - GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT | - GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT | - GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT); - break; - case PERIPH_ID_SPI1: - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio0d_iomux, - GPIO0D7_MASK << GPIO0D7_SHIFT, - GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B6_MASK << GPIO1B6_SHIFT, - GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT); - break; - default: - goto err; - } - rk_clrsetreg(&grf->gpio0d_iomux, - GPIO0D4_MASK << GPIO0D4_SHIFT | - GPIO0D5_MASK << GPIO0D5_SHIFT | - GPIO0D6_MASK << GPIO0D6_SHIFT, - GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT | - GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT | - GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT); - break; - default: - goto err; - } - - return 0; -err: - debug("rkspi: periph%d cs=%d not supported", spi_id, cs); - return -ENOENT; -} - -static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id) -{ - switch (uart_id) { - case PERIPH_ID_UART0: - rk_clrsetreg(&grf->gpio1a_iomux, - GPIO1A3_MASK << GPIO1A3_SHIFT | - GPIO1A2_MASK << GPIO1A2_SHIFT | - GPIO1A1_MASK << GPIO1A1_SHIFT | - GPIO1A0_MASK << GPIO1A0_SHIFT, - GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT | - GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT | - GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT | - GPIO1A0_UART0_SIN << GPIO1A0_SHIFT); - break; - case PERIPH_ID_UART1: - rk_clrsetreg(&grf->gpio1a_iomux, - GPIO1A7_MASK << GPIO1A7_SHIFT | - GPIO1A6_MASK << GPIO1A6_SHIFT | - GPIO1A5_MASK << GPIO1A5_SHIFT | - GPIO1A4_MASK << GPIO1A4_SHIFT, - GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT | - GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT | - GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT | - GPIO1A4_UART1_SIN << GPIO1A4_SHIFT); - break; - case PERIPH_ID_UART2: - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK << GPIO1B1_SHIFT | - GPIO1B0_MASK << GPIO1B0_SHIFT, - GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | - GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); - break; - case PERIPH_ID_UART3: - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B5_MASK << GPIO1B5_SHIFT | - GPIO1B4_MASK << GPIO1B4_SHIFT | - GPIO1B3_MASK << GPIO1B3_SHIFT | - GPIO1B2_MASK << GPIO1B2_SHIFT, - GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT | - GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT | - GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT | - GPIO1B2_UART3_SIN << GPIO1B2_SHIFT); - break; - default: - debug("uart id = %d iomux error!\n", uart_id); - break; - } -} - -static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id) -{ - switch (mmc_id) { - case PERIPH_ID_EMMC: - rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT, - 1 << EMMC_FLASH_SEL_SHIFT); - rk_clrsetreg(&grf->gpio0d_iomux, - GPIO0D2_MASK << GPIO0D2_SHIFT | - GPIO0D0_MASK << GPIO0D0_SHIFT, - GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT | - GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT); - break; - case PERIPH_ID_SDCARD: - rk_clrsetreg(&grf->gpio3b_iomux, - GPIO3B0_MASK << GPIO3B0_SHIFT, - GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT); - rk_clrsetreg(&grf->gpio3a_iomux, - GPIO3A7_MASK << GPIO3A7_SHIFT | - GPIO3A6_MASK << GPIO3A6_SHIFT | - GPIO3A5_MASK << GPIO3A5_SHIFT | - GPIO3A4_MASK << GPIO3A4_SHIFT | - GPIO3A3_MASK << GPIO3A3_SHIFT | - GPIO3A3_MASK << GPIO3A2_SHIFT, - GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT | - GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT | - GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT | - GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT | - GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT | - GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT); - break; - default: - debug("mmc id = %d iomux error!\n", mmc_id); - break; - } -} - -static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%x, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - case PERIPH_ID_PWM4: - pinctrl_rk3188_pwm_config(priv->grf, func); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func); - break; - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - pinctrl_rk3188_spi_config(priv->grf, func, flags); - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - case PERIPH_ID_UART4: - pinctrl_rk3188_uart_config(priv->grf, func); - break; - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - pinctrl_rk3188_sdmmc_config(priv->grf, func); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int rk3188_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - u32 cell[3]; - int ret; - - ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 44: - return PERIPH_ID_SPI0; - case 45: - return PERIPH_ID_SPI1; - case 46: - return PERIPH_ID_SPI2; - case 60: - return PERIPH_ID_I2C0; - case 62: /* Note strange order */ - return PERIPH_ID_I2C1; - case 61: - return PERIPH_ID_I2C2; - case 63: - return PERIPH_ID_I2C3; - case 64: - return PERIPH_ID_I2C4; - case 65: - return PERIPH_ID_I2C5; - } -#endif - - return -ENOENT; -} - -static int rk3188_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk3188_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - return rk3188_pinctrl_request(dev, func, 0); -} - -#ifndef CONFIG_SPL_BUILD -int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv, - int banknum, int ind, u32 **addrp, uint *shiftp, - uint *maskp) -{ - struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum]; - uint muxnum; - u32 *addr; - - for (muxnum = 0; muxnum < 4; muxnum++) { - struct rockchip_iomux *mux = &bank->iomux[muxnum]; - - if (ind >= 8) { - ind -= 8; - continue; - } - - addr = &priv->grf->gpio0c_iomux - 2; - addr += mux->offset; - *shiftp = ind & 7; - *maskp = 3; - *shiftp *= 2; - - debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr, - *maskp, *shiftp); - *addrp = addr; - return 0; - } - - return -EINVAL; -} - -static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, - int index) -{ - struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); - uint shift; - uint mask; - u32 *addr; - int ret; - - ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, - &mask); - if (ret) - return ret; - return (readl(addr) & mask) >> shift; -} - -static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index, - int muxval, int flags) -{ - struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); - uint shift, ind = index; - uint mask; - u32 *addr; - int ret; - - debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags); - ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, - &mask); - if (ret) - return ret; - rk_clrsetreg(addr, mask << shift, muxval << shift); - - /* Handle pullup/pulldown */ - if (flags) { - uint val = 0; - - if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP)) - val = 1; - else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) - val = 2; - - ind = index >> 3; - - if (banknum == 0 && index < 12) { - addr = &priv->pmu->gpio0_p[ind]; - shift = (index & 7) * 2; - } else if (banknum == 0 && index >= 12) { - addr = &priv->grf->gpio0_p[ind - 1]; - /* - * The bits in the grf-registers have an inverse - * ordering with the lowest pin being in bits 15:14 - * and the highest pin in bits 1:0 . - */ - shift = (7 - (index & 7)) * 2; - } else { - addr = &priv->grf->gpio1_p[banknum - 1][ind]; - shift = (7 - (index & 7)) * 2; - } - debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, - shift); - rk_clrsetreg(addr, 3 << shift, val << shift); - } - - return 0; -} - -static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config) -{ - const void *blob = gd->fdt_blob; - int pcfg_node, ret, flags, count, i; - u32 cell[60], *ptr; - - debug("%s: %s %s\n", __func__, dev->name, config->name); - ret = fdtdec_get_int_array_count(blob, dev_of_offset(config), - "rockchip,pins", cell, - ARRAY_SIZE(cell)); - if (ret < 0) { - debug("%s: bad array %d\n", __func__, ret); - return -EINVAL; - } - count = ret; - for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) { - pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]); - if (pcfg_node < 0) - return -EINVAL; - flags = pinctrl_decode_pin_config(blob, pcfg_node); - if (flags < 0) - return flags; - - ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2], - flags); - if (ret) - return ret; - } - - return 0; -} -#endif - -static struct pinctrl_ops rk3188_pinctrl_ops = { -#ifndef CONFIG_SPL_BUILD - .set_state = rk3188_pinctrl_set_state, - .get_gpio_mux = rk3188_pinctrl_get_gpio_mux, -#endif - .set_state_simple = rk3188_pinctrl_set_state_simple, - .request = rk3188_pinctrl_request, - .get_periph_id = rk3188_pinctrl_get_periph_id, -}; - -#ifndef CONFIG_SPL_BUILD -static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv, - struct rockchip_pin_bank *banks, - int count) -{ - struct rockchip_pin_bank *bank; - uint reg, muxnum, banknum; - - reg = 0; - for (banknum = 0; banknum < count; banknum++) { - bank = &banks[banknum]; - bank->reg = reg; - debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4); - for (muxnum = 0; muxnum < 4; muxnum++) { - struct rockchip_iomux *mux = &bank->iomux[muxnum]; - - mux->offset = reg; - reg += 1; - } - } - - return 0; -} -#endif - -static int rk3188_pinctrl_probe(struct udevice *dev) -{ - struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); - int ret = 0; - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); - debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu); -#ifndef CONFIG_SPL_BUILD - ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks, - ARRAY_SIZE(rk3188_pin_banks)); -#endif - - return ret; -} - -static const struct udevice_id rk3188_pinctrl_ids[] = { - { .compatible = "rockchip,rk3188-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3188) = { - .name = "rockchip_rk3188_pinctrl", - .id = UCLASS_PINCTRL, - .of_match = rk3188_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv), - .ops = &rk3188_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - .bind = dm_scan_fdt_dev, -#endif - .probe = rk3188_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c deleted file mode 100644 index f4139d35b8..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c +++ /dev/null @@ -1,894 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <dm/pinctrl.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* GRF_GPIO0A_IOMUX */ -enum { - GPIO0A7_SHIFT = 14, - GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, - GPIO0A7_GPIO = 0, - GPIO0A7_I2C3_SDA, - GPIO0A7_HDMI_DDCSDA, - - GPIO0A6_SHIFT = 12, - GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, - GPIO0A6_GPIO = 0, - GPIO0A6_I2C3_SCL, - GPIO0A6_HDMI_DDCSCL, - - GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, - GPIO0A3_GPIO = 0, - GPIO0A3_I2C1_SDA, - GPIO0A3_SDIO_CMD, - - GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, - GPIO0A2_GPIO = 0, - GPIO0A2_I2C1_SCL, - - GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, - GPIO0A1_GPIO = 0, - GPIO0A1_I2C0_SDA, - - GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, - GPIO0A0_GPIO = 0, - GPIO0A0_I2C0_SCL, -}; - -/* GRF_GPIO0B_IOMUX */ -enum { - GPIO0B7_SHIFT = 14, - GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, - GPIO0B7_GPIO = 0, - GPIO0B7_HDMI_HDP, - - GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, - GPIO0B6_GPIO = 0, - GPIO0B6_I2S_SDI, - GPIO0B6_SPI_CSN0, - - GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, - GPIO0B5_GPIO = 0, - GPIO0B5_I2S_SDO, - GPIO0B5_SPI_RXD, - - GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, - GPIO0B3_GPIO = 0, - GPIO0B3_I2S1_LRCKRX, - GPIO0B3_SPI_TXD, - - GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, - GPIO0B1_GPIO = 0, - GPIO0B1_I2S_SCLK, - GPIO0B1_SPI_CLK, - - GPIO0B0_SHIFT = 0, - GPIO0B0_MASK = 3, - GPIO0B0_GPIO = 0, - GPIO0B0_I2S_MCLK, -}; - -/* GRF_GPIO0C_IOMUX */ -enum { - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, - GPIO0C4_GPIO = 0, - GPIO0C4_HDMI_CECSDA, - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, - GPIO0C1_GPIO = 0, - GPIO0C1_UART0_RSTN, - GPIO0C1_CLK_OUT1, -}; - -/* GRF_GPIO0D_IOMUX */ -enum { - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, - GPIO0D6_GPIO = 0, - GPIO0D6_SDIO_PWREN, - GPIO0D6_PWM11, - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_PWM2, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_PWM1, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_PWM0, -}; - -/* GRF_GPIO1A_IOMUX */ -enum { - GPIO1A7_SHIFT = 14, - GPIO1A7_MASK = 1, - GPIO1A7_GPIO = 0, - GPIO1A7_SDMMC_WRPRT, -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, - GPIO1B7_GPIO = 0, - GPIO1B7_SDMMC_CMD, - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, - GPIO1B6_GPIO = 0, - GPIO1B6_SDMMC_PWREN, - - GPIO1B4_SHIFT = 8, - GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, - GPIO1B4_GPIO = 0, - GPIO1B4_SPI_CSN1, - GPIO1B4_PWM12, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, - GPIO1B3_GPIO = 0, - GPIO1B3_UART1_RSTN, - GPIO1B3_PWM13, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART1_SIN, - GPIO1B2_UART21_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_UART1_SOUT, - GPIO1B1_UART21_SOUT, -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C7_SHIFT = 14, - GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, - GPIO1C7_GPIO = 0, - GPIO1C7_NAND_CS3, - GPIO1C7_EMMC_RSTNOUT, - - GPIO1C6_SHIFT = 12, - GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, - GPIO1C6_GPIO = 0, - GPIO1C6_NAND_CS2, - GPIO1C6_EMMC_CMD, - - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, - GPIO1C5_GPIO = 0, - GPIO1C5_SDMMC_D3, - GPIO1C5_JTAG_TMS, - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, - GPIO1C4_GPIO = 0, - GPIO1C4_SDMMC_D2, - GPIO1C4_JTAG_TCK, - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, - GPIO1C3_GPIO = 0, - GPIO1C3_SDMMC_D1, - GPIO1C3_UART2_SIN, - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, - GPIO1C2_GPIO = 0, - GPIO1C2_SDMMC_D0, - GPIO1C2_UART2_SOUT, - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, - GPIO1C1_GPIO = 0, - GPIO1C1_SDMMC_DETN, - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, - GPIO1C0_GPIO = 0, - GPIO1C0_SDMMC_CLKOUT, -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, - GPIO1D7_GPIO = 0, - GPIO1D7_NAND_D7, - GPIO1D7_EMMC_D7, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, - GPIO1D6_GPIO = 0, - GPIO1D6_NAND_D6, - GPIO1D6_EMMC_D6, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, - GPIO1D5_GPIO = 0, - GPIO1D5_NAND_D5, - GPIO1D5_EMMC_D5, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, - GPIO1D4_GPIO = 0, - GPIO1D4_NAND_D4, - GPIO1D4_EMMC_D4, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_NAND_D3, - GPIO1D3_EMMC_D3, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_NAND_D2, - GPIO1D2_EMMC_D2, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, - GPIO1D1_GPIO = 0, - GPIO1D1_NAND_D1, - GPIO1D1_EMMC_D1, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, - GPIO1D0_GPIO = 0, - GPIO1D0_NAND_D0, - GPIO1D0_EMMC_D0, -}; - -/* GRF_GPIO2A_IOMUX */ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_NAND_DQS, - GPIO2A7_EMMC_CLKOUT, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_NAND_WP, - GPIO2A5_EMMC_PWREN, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_NAND_RDY, - GPIO2A4_EMMC_CMD, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_NAND_RDN, - GPIO2A4_SPI1_CSN1, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_NAND_WRN, - GPIO2A4_SPI1_CSN0, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_NAND_CLE, - GPIO2A1_SPI1_TXD, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_NAND_ALE, - GPIO2A0_SPI1_RXD, -}; - -/* GRF_GPIO2B_IOMUX */ -enum { - GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, - GPIO2B7_GPIO = 0, - GPIO2B7_GMAC_RXER, - - GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, - GPIO2B6_GPIO = 0, - GPIO2B6_GMAC_CLK, - GPIO2B6_MAC_LINK, - - GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, - GPIO2B5_GPIO = 0, - GPIO2B5_GMAC_TXEN, - - GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, - GPIO2B4_GPIO = 0, - GPIO2B4_GMAC_MDIO, - - GPIO2B3_SHIFT = 6, - GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, - GPIO2B3_GPIO = 0, - GPIO2B3_GMAC_RXCLK, - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, - GPIO2B2_GPIO = 0, - GPIO2B2_GMAC_CRS, - - GPIO2B1_SHIFT = 2, - GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, - GPIO2B1_GPIO = 0, - GPIO2B1_GMAC_TXCLK, - - GPIO2B0_SHIFT = 0, - GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, - GPIO2B0_GPIO = 0, - GPIO2B0_GMAC_RXDV, - GPIO2B0_MAC_SPEED_IOUT, -}; - -/* GRF_GPIO2C_IOMUX */ -enum { - GPIO2C7_SHIFT = 14, - GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, - GPIO2C7_GPIO = 0, - GPIO2C7_GMAC_TXD3, - - GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, - GPIO2C6_GPIO = 0, - GPIO2C6_GMAC_TXD2, - - GPIO2C5_SHIFT = 10, - GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, - GPIO2C5_GPIO = 0, - GPIO2C5_I2C2_SCL, - GPIO2C5_GMAC_RXD2, - - GPIO2C4_SHIFT = 8, - GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, - GPIO2C4_GPIO = 0, - GPIO2C4_I2C2_SDA, - GPIO2C4_GMAC_RXD3, - - GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, - GPIO2C3_GPIO = 0, - GPIO2C3_GMAC_TXD0, - - GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, - GPIO2C2_GPIO = 0, - GPIO2C2_GMAC_TXD1, - - GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, - GPIO2C1_GPIO = 0, - GPIO2C1_GMAC_RXD0, - - GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, - GPIO2C0_GPIO = 0, - GPIO2C0_GMAC_RXD1, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_GMAC_MDC, - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = 3, - GPIO2D0_GPIO = 0, - GPIO2D0_GMAC_COL, -}; - -/* GRF_GPIO3C_IOMUX */ -enum { - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, - GPIO3C6_GPIO = 0, - GPIO3C6_DRV_VBUS1, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, - GPIO3C5_GPIO = 0, - GPIO3C5_PWM10, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, - GPIO3C1_GPIO = 0, - GPIO3C1_DRV_VBUS, -}; - -/* GRF_GPIO3D_IOMUX */ -enum { - GPIO3D2_SHIFT = 4, - GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, - GPIO3D2_GPIO = 0, - GPIO3D2_PWM3, -}; - -/* GRF_CON_IOMUX */ -enum { - CON_IOMUX_GMACSEL_SHIFT = 15, - CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT, - CON_IOMUX_GMACSEL_1 = 1, - CON_IOMUX_UART1SEL_SHIFT = 11, - CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT, - CON_IOMUX_UART2SEL_SHIFT = 8, - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, - CON_IOMUX_UART2SEL_2 = 0, - CON_IOMUX_UART2SEL_21, - CON_IOMUX_EMMCSEL_SHIFT = 7, - CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT, - CON_IOMUX_PWM3SEL_SHIFT = 3, - CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT, - CON_IOMUX_PWM2SEL_SHIFT = 2, - CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT, - CON_IOMUX_PWM1SEL_SHIFT = 1, - CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT, - CON_IOMUX_PWM0SEL_SHIFT = 0, - CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, -}; - -/* GRF_GPIO2B_E */ -enum { - GRF_GPIO2B0_E_SHIFT = 0, - GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT, - GRF_GPIO2B1_E_SHIFT = 2, - GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT, - GRF_GPIO2B3_E_SHIFT = 6, - GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT, - GRF_GPIO2B4_E_SHIFT = 8, - GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT, - GRF_GPIO2B5_E_SHIFT = 10, - GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT, - GRF_GPIO2B6_E_SHIFT = 12, - GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT, -}; - -/* GRF_GPIO2C_E */ -enum { - GRF_GPIO2C0_E_SHIFT = 0, - GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT, - GRF_GPIO2C1_E_SHIFT = 2, - GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT, - GRF_GPIO2C2_E_SHIFT = 4, - GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT, - GRF_GPIO2C3_E_SHIFT = 6, - GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT, - GRF_GPIO2C4_E_SHIFT = 8, - GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT, - GRF_GPIO2C5_E_SHIFT = 10, - GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT, - GRF_GPIO2C6_E_SHIFT = 12, - GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT, - GRF_GPIO2C7_E_SHIFT = 14, - GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT, -}; - -/* GRF_GPIO2D_E */ -enum { - GRF_GPIO2D1_E_SHIFT = 2, - GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT, -}; - -/* GPIO Bias drive strength settings */ -enum GPIO_BIAS { - GPIO_BIAS_2MA = 0, - GPIO_BIAS_4MA, - GPIO_BIAS_8MA, - GPIO_BIAS_12MA, -}; - -struct rk322x_pinctrl_priv { - struct rk322x_grf *grf; -}; - -static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id) -{ - u32 mux_con = readl(&grf->con_iomux); - - switch (pwm_id) { - case PERIPH_ID_PWM0: - if (mux_con & CON_IOMUX_PWM0SEL_MASK) - rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK, - GPIO3C5_PWM10 << GPIO3C5_SHIFT); - else - rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, - GPIO0D2_PWM0 << GPIO0D2_SHIFT); - break; - case PERIPH_ID_PWM1: - if (mux_con & CON_IOMUX_PWM1SEL_MASK) - rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK, - GPIO0D6_PWM11 << GPIO0D6_SHIFT); - else - rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK, - GPIO0D3_PWM1 << GPIO0D3_SHIFT); - break; - case PERIPH_ID_PWM2: - if (mux_con & CON_IOMUX_PWM2SEL_MASK) - rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK, - GPIO1B4_PWM12 << GPIO1B4_SHIFT); - else - rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK, - GPIO0D4_PWM2 << GPIO0D4_SHIFT); - break; - case PERIPH_ID_PWM3: - if (mux_con & CON_IOMUX_PWM3SEL_MASK) - rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK, - GPIO1B3_PWM13 << GPIO1B3_SHIFT); - else - rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK, - GPIO3D2_PWM3 << GPIO3D2_SHIFT); - break; - default: - debug("pwm id = %d iomux error!\n", pwm_id); - break; - } -} - -static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id) -{ - switch (i2c_id) { - case PERIPH_ID_I2C0: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A1_MASK | GPIO0A0_MASK, - GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | - GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); - - break; - case PERIPH_ID_I2C1: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A3_MASK | GPIO0A2_MASK, - GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | - GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); - break; - case PERIPH_ID_I2C2: - rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C5_MASK | GPIO2C4_MASK, - GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | - GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); - break; - case PERIPH_ID_I2C3: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A7_MASK | GPIO0A6_MASK, - GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT | - GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT); - - break; - } -} - -static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs) -{ - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK, - GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK, - GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT); - break; - } - rk_clrsetreg(&grf->gpio0b_iomux, - GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK, - GPIO0B5_SPI_RXD << GPIO0B5_SHIFT | - GPIO0B3_SPI_TXD << GPIO0B3_SHIFT | - GPIO0B1_SPI_CLK << GPIO0B1_SHIFT); -} - -static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id) -{ - u32 mux_con = readl(&grf->con_iomux); - - switch (uart_id) { - case PERIPH_ID_UART1: - if (!(mux_con & CON_IOMUX_UART1SEL_MASK)) - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT | - GPIO1B2_UART1_SIN << GPIO1B2_SHIFT); - break; - case PERIPH_ID_UART2: - if (mux_con & CON_IOMUX_UART2SEL_MASK) - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT | - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT); - else - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C3_MASK | GPIO1C2_MASK, - GPIO1C3_UART2_SIN << GPIO1C3_SHIFT | - GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT); - break; - } -} - -static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id) -{ - switch (mmc_id) { - case PERIPH_ID_EMMC: - rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, - GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | - GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | - GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | - GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | - GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | - GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | - GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | - GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A5_MASK | GPIO2A7_MASK, - GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT | - GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT); - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C6_MASK | GPIO1C7_MASK, - GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT | - GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT); - break; - case PERIPH_ID_SDCARD: - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B6_MASK | GPIO1B7_MASK, - GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT | - GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT); - rk_clrsetreg(&grf->gpio1c_iomux, 0xfff, - GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT | - GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT | - GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT | - GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT | - GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT | - GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT); - break; - } -} - -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) -static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id) -{ - switch (gmac_id) { - case PERIPH_ID_GMAC: - /* set rgmii pins mux */ - rk_clrsetreg(&grf->gpio2b_iomux, - GPIO2B0_MASK | - GPIO2B1_MASK | - GPIO2B3_MASK | - GPIO2B4_MASK | - GPIO2B5_MASK | - GPIO2B6_MASK, - GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT | - GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT | - GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT | - GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT | - GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT | - GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT); - - rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C0_MASK | - GPIO2C1_MASK | - GPIO2C2_MASK | - GPIO2C3_MASK | - GPIO2C4_MASK | - GPIO2C5_MASK | - GPIO2C6_MASK | - GPIO2C7_MASK, - GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT | - GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT | - GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT | - GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT | - GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT | - GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT | - GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT | - GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT); - - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D1_MASK, - GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT); - - /* - * set rgmii tx pins to 12ma drive-strength, - * clean others with 2ma. - */ - rk_clrsetreg(&grf->gpio2_e[1], - GRF_GPIO2B0_E_MASK | - GRF_GPIO2B1_E_MASK | - GRF_GPIO2B3_E_MASK | - GRF_GPIO2B4_E_MASK | - GRF_GPIO2B5_E_MASK | - GRF_GPIO2B6_E_MASK, - GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT); - - rk_clrsetreg(&grf->gpio2_e[2], - GRF_GPIO2C0_E_MASK | - GRF_GPIO2C1_E_MASK | - GRF_GPIO2C2_E_MASK | - GRF_GPIO2C3_E_MASK | - GRF_GPIO2C4_E_MASK | - GRF_GPIO2C5_E_MASK | - GRF_GPIO2C6_E_MASK | - GRF_GPIO2C7_E_MASK, - GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT); - - rk_clrsetreg(&grf->gpio2_e[3], - GRF_GPIO2D1_E_MASK, - GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT); - break; - default: - debug("gmac id = %d iomux error!\n", gmac_id); - break; - } -} -#endif - -static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%x, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - pinctrl_rk322x_pwm_config(priv->grf, func); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - pinctrl_rk322x_i2c_config(priv->grf, func); - break; - case PERIPH_ID_SPI0: - pinctrl_rk322x_spi_config(priv->grf, flags); - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - pinctrl_rk322x_uart_config(priv->grf, func); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - pinctrl_rk322x_sdmmc_config(priv->grf, func); - break; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case PERIPH_ID_GMAC: - pinctrl_rk322x_gmac_config(priv->grf, func); - break; -#endif - default: - return -EINVAL; - } - - return 0; -} - -static int rk322x_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ - u32 cell[3]; - int ret; - - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 12: - return PERIPH_ID_SDCARD; - case 14: - return PERIPH_ID_EMMC; - case 36: - return PERIPH_ID_I2C0; - case 37: - return PERIPH_ID_I2C1; - case 38: - return PERIPH_ID_I2C2; - case 49: - return PERIPH_ID_SPI0; - case 50: - return PERIPH_ID_PWM0; - case 55: - return PERIPH_ID_UART0; - case 56: - return PERIPH_ID_UART1; - case 57: - return PERIPH_ID_UART2; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case 24: - return PERIPH_ID_GMAC; -#endif - } - return -ENOENT; -} - -static int rk322x_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk322x_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - return rk322x_pinctrl_request(dev, func, 0); -} - -static struct pinctrl_ops rk322x_pinctrl_ops = { - .set_state_simple = rk322x_pinctrl_set_state_simple, - .request = rk322x_pinctrl_request, - .get_periph_id = rk322x_pinctrl_get_periph_id, -}; - -static int rk322x_pinctrl_probe(struct udevice *dev) -{ - struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - debug("%s: grf=%p\n", __func__, priv->grf); - return 0; -} - -static const struct udevice_id rk322x_pinctrl_ids[] = { - { .compatible = "rockchip,rk3228-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3228) = { - .name = "pinctrl_rk3228", - .id = UCLASS_PINCTRL, - .of_match = rk322x_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv), - .ops = &rk322x_pinctrl_ops, - .bind = dm_scan_fdt_dev, - .probe = rk322x_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c deleted file mode 100644 index 3e01cfd98f..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ /dev/null @@ -1,869 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinctrl driver for Rockchip SoCs - * Copyright (c) 2015 Google, Inc - * Written by Simon Glass <sjg@chromium.org> - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <dm/pinctrl.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct rk3288_pinctrl_priv { - struct rk3288_grf *grf; - struct rk3288_pmu *pmu; - int num_banks; -}; - -/** - * Encode variants of iomux registers into a type variable - */ -#define IOMUX_GPIO_ONLY BIT(0) -#define IOMUX_WIDTH_4BIT BIT(1) -#define IOMUX_SOURCE_PMU BIT(2) -#define IOMUX_UNROUTED BIT(3) - -/** - * @type: iomux variant using IOMUX_* constants - * @offset: if initialized to -1 it will be autocalculated, by specifying - * an initial offset value the relevant source offset can be reset - * to a new value for autocalculating the following iomux registers. - */ -struct rockchip_iomux { - u8 type; - s16 offset; -}; - -/** - * @reg: register offset of the gpio bank - * @nr_pins: number of pins in this bank - * @bank_num: number of the bank, to account for holes - * @name: name of the bank - * @iomux: array describing the 4 iomux sources of the bank - */ -struct rockchip_pin_bank { - u16 reg; - u8 nr_pins; - u8 bank_num; - char *name; - struct rockchip_iomux iomux[4]; -}; - -#define PIN_BANK(id, pins, label) \ - { \ - .bank_num = id, \ - .nr_pins = pins, \ - .name = label, \ - .iomux = { \ - { .offset = -1 }, \ - { .offset = -1 }, \ - { .offset = -1 }, \ - { .offset = -1 }, \ - }, \ - } - -#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ - { \ - .bank_num = id, \ - .nr_pins = pins, \ - .name = label, \ - .iomux = { \ - { .type = iom0, .offset = -1 }, \ - { .type = iom1, .offset = -1 }, \ - { .type = iom2, .offset = -1 }, \ - { .type = iom3, .offset = -1 }, \ - }, \ - } - -#ifndef CONFIG_SPL_BUILD -static struct rockchip_pin_bank rk3288_pin_banks[] = { - PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, - IOMUX_SOURCE_PMU, - IOMUX_SOURCE_PMU, - IOMUX_UNROUTED - ), - PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, - IOMUX_UNROUTED, - IOMUX_UNROUTED, - 0 - ), - PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), - PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), - PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, - IOMUX_WIDTH_4BIT, - 0, - 0 - ), - PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, - 0, - 0, - IOMUX_UNROUTED - ), - PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), - PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, - 0, - IOMUX_WIDTH_4BIT, - IOMUX_UNROUTED - ), - PIN_BANK(8, 16, "gpio8"), -}; -#endif - -static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id) -{ - switch (pwm_id) { - case PERIPH_ID_PWM0: - rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT, - GPIO7A0_PWM_0 << GPIO7A0_SHIFT); - break; - case PERIPH_ID_PWM1: - rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT, - GPIO7A1_PWM_1 << GPIO7A1_SHIFT); - break; - case PERIPH_ID_PWM2: - rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C6_PWM_2 << GPIO7C6_SHIFT); - break; - case PERIPH_ID_PWM3: - rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT, - GPIO7C7_PWM_3 << GPIO7C7_SHIFT); - break; - default: - debug("pwm id = %d iomux error!\n", pwm_id); - break; - } -} - -static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf, - struct rk3288_pmu *pmu, int i2c_id) -{ - switch (i2c_id) { - case PERIPH_ID_I2C0: - clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B], - GPIO0_B7_MASK << GPIO0_B7_SHIFT, - GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT); - clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C], - GPIO0_C0_MASK << GPIO0_C0_SHIFT, - GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT); - break; -#ifndef CONFIG_SPL_BUILD - case PERIPH_ID_I2C1: - rk_clrsetreg(&grf->gpio8a_iomux, - GPIO8A4_MASK << GPIO8A4_SHIFT | - GPIO8A5_MASK << GPIO8A5_SHIFT, - GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT | - GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT); - break; - case PERIPH_ID_I2C2: - rk_clrsetreg(&grf->gpio6b_iomux, - GPIO6B1_MASK << GPIO6B1_SHIFT | - GPIO6B2_MASK << GPIO6B2_SHIFT, - GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT | - GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT); - break; - case PERIPH_ID_I2C3: - rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C1_MASK << GPIO2C1_SHIFT | - GPIO2C0_MASK << GPIO2C0_SHIFT, - GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT | - GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT); - break; - case PERIPH_ID_I2C4: - rk_clrsetreg(&grf->gpio7cl_iomux, - GPIO7C1_MASK << GPIO7C1_SHIFT | - GPIO7C2_MASK << GPIO7C2_SHIFT, - GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT | - GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT); - break; - case PERIPH_ID_I2C5: - rk_clrsetreg(&grf->gpio7cl_iomux, - GPIO7C3_MASK << GPIO7C3_SHIFT, - GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT); - rk_clrsetreg(&grf->gpio7ch_iomux, - GPIO7C4_MASK << GPIO7C4_SHIFT, - GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT); - break; -#endif - default: - debug("i2c id = %d iomux error!\n", i2c_id); - break; - } -} - -#ifndef CONFIG_SPL_BUILD -static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id) -{ - switch (lcd_id) { - case PERIPH_ID_LCDC0: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D3_MASK << GPIO1D0_SHIFT | - GPIO1D2_MASK << GPIO1D2_SHIFT | - GPIO1D1_MASK << GPIO1D1_SHIFT | - GPIO1D0_MASK << GPIO1D0_SHIFT, - GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT | - GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT | - GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT | - GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT); - break; - default: - debug("lcdc id = %d iomux error!\n", lcd_id); - break; - } -} -#endif - -static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf, - enum periph_id spi_id, int cs) -{ - switch (spi_id) { -#ifndef CONFIG_SPL_BUILD - case PERIPH_ID_SPI0: - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio5b_iomux, - GPIO5B5_MASK << GPIO5B5_SHIFT, - GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio5c_iomux, - GPIO5C0_MASK << GPIO5C0_SHIFT, - GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT); - break; - default: - goto err; - } - rk_clrsetreg(&grf->gpio5b_iomux, - GPIO5B7_MASK << GPIO5B7_SHIFT | - GPIO5B6_MASK << GPIO5B6_SHIFT | - GPIO5B4_MASK << GPIO5B4_SHIFT, - GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT | - GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT | - GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT); - break; - case PERIPH_ID_SPI1: - if (cs != 0) - goto err; - rk_clrsetreg(&grf->gpio7b_iomux, - GPIO7B6_MASK << GPIO7B6_SHIFT | - GPIO7B7_MASK << GPIO7B7_SHIFT | - GPIO7B5_MASK << GPIO7B5_SHIFT | - GPIO7B4_MASK << GPIO7B4_SHIFT, - GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT | - GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT | - GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT | - GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT); - break; -#endif - case PERIPH_ID_SPI2: - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio8a_iomux, - GPIO8A7_MASK << GPIO8A7_SHIFT, - GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio8a_iomux, - GPIO8A3_MASK << GPIO8A3_SHIFT, - GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT); - break; - default: - goto err; - } - rk_clrsetreg(&grf->gpio8b_iomux, - GPIO8B1_MASK << GPIO8B1_SHIFT | - GPIO8B0_MASK << GPIO8B0_SHIFT, - GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT | - GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT); - rk_clrsetreg(&grf->gpio8a_iomux, - GPIO8A6_MASK << GPIO8A6_SHIFT, - GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT); - break; - default: - goto err; - } - - return 0; -err: - debug("rkspi: periph%d cs=%d not supported", spi_id, cs); - return -ENOENT; -} - -static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id) -{ - switch (uart_id) { -#ifndef CONFIG_SPL_BUILD - case PERIPH_ID_UART_BT: - rk_clrsetreg(&grf->gpio4c_iomux, - GPIO4C3_MASK << GPIO4C3_SHIFT | - GPIO4C2_MASK << GPIO4C2_SHIFT | - GPIO4C1_MASK << GPIO4C1_SHIFT | - GPIO4C0_MASK << GPIO4C0_SHIFT, - GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT | - GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT | - GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT | - GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT); - break; - case PERIPH_ID_UART_BB: - rk_clrsetreg(&grf->gpio5b_iomux, - GPIO5B3_MASK << GPIO5B3_SHIFT | - GPIO5B2_MASK << GPIO5B2_SHIFT | - GPIO5B1_MASK << GPIO5B1_SHIFT | - GPIO5B0_MASK << GPIO5B0_SHIFT, - GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT | - GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT | - GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT | - GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT); - break; -#endif - case PERIPH_ID_UART_DBG: - rk_clrsetreg(&grf->gpio7ch_iomux, - GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); - break; -#ifndef CONFIG_SPL_BUILD - case PERIPH_ID_UART_GPS: - rk_clrsetreg(&grf->gpio7b_iomux, - GPIO7B2_MASK << GPIO7B2_SHIFT | - GPIO7B1_MASK << GPIO7B1_SHIFT | - GPIO7B0_MASK << GPIO7B0_SHIFT, - GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT | - GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT | - GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT); - rk_clrsetreg(&grf->gpio7a_iomux, - GPIO7A7_MASK << GPIO7A7_SHIFT, - GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT); - break; - case PERIPH_ID_UART_EXP: - rk_clrsetreg(&grf->gpio5b_iomux, - GPIO5B5_MASK << GPIO5B5_SHIFT | - GPIO5B4_MASK << GPIO5B4_SHIFT | - GPIO5B6_MASK << GPIO5B6_SHIFT | - GPIO5B7_MASK << GPIO5B7_SHIFT, - GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT | - GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT | - GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT | - GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT); - break; -#endif - default: - debug("uart id = %d iomux error!\n", uart_id); - break; - } -} - -static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id) -{ - switch (mmc_id) { - case PERIPH_ID_EMMC: - rk_clrsetreg(&grf->gpio3a_iomux, 0xffff, - GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT | - GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT | - GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT | - GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT | - GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT | - GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT | - GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT | - GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT); - rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT, - GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT); - rk_clrsetreg(&grf->gpio3c_iomux, - GPIO3C0_MASK << GPIO3C0_SHIFT, - GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT); - break; - case PERIPH_ID_SDCARD: - rk_clrsetreg(&grf->gpio6c_iomux, 0xffff, - GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT | - GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT | - GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT | - GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT | - GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT | - GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT | - GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT); - - /* use sdmmc0 io, disable JTAG function */ - rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0); - break; - default: - debug("mmc id = %d iomux error!\n", mmc_id); - break; - } -} - -static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id) -{ - switch (gmac_id) { - case PERIPH_ID_GMAC: - rk_clrsetreg(&grf->gpio3dl_iomux, - GPIO3D3_MASK << GPIO3D3_SHIFT | - GPIO3D2_MASK << GPIO3D2_SHIFT | - GPIO3D2_MASK << GPIO3D1_SHIFT | - GPIO3D0_MASK << GPIO3D0_SHIFT, - GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT | - GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT | - GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT | - GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT); - - rk_clrsetreg(&grf->gpio3dh_iomux, - GPIO3D7_MASK << GPIO3D7_SHIFT | - GPIO3D6_MASK << GPIO3D6_SHIFT | - GPIO3D5_MASK << GPIO3D5_SHIFT | - GPIO3D4_MASK << GPIO3D4_SHIFT, - GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT | - GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT | - GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT | - GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT); - - /* switch the Tx pins to 12ma drive-strength */ - rk_clrsetreg(&grf->gpio1_e[2][3], - GPIO_BIAS_MASK | - (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) | - (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) | - (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)), - (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) | - (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) | - (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) | - (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5))); - - /* Set normal pull for all GPIO3D pins */ - rk_clrsetreg(&grf->gpio1_p[2][3], - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)), - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7))); - - rk_clrsetreg(&grf->gpio4al_iomux, - GPIO4A3_MASK << GPIO4A3_SHIFT | - GPIO4A1_MASK << GPIO4A1_SHIFT | - GPIO4A0_MASK << GPIO4A0_SHIFT, - GPIO4A3_MAC_CLK << GPIO4A3_SHIFT | - GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT | - GPIO4A0_MAC_MDC << GPIO4A0_SHIFT); - - rk_clrsetreg(&grf->gpio4ah_iomux, - GPIO4A6_MASK << GPIO4A6_SHIFT | - GPIO4A5_MASK << GPIO4A5_SHIFT | - GPIO4A4_MASK << GPIO4A4_SHIFT, - GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT | - GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT | - GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT); - - /* switch GPIO4A4 to 12ma drive-strength */ - rk_clrsetreg(&grf->gpio1_e[3][0], - GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4), - GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)); - - /* Set normal pull for all GPIO4A pins */ - rk_clrsetreg(&grf->gpio1_p[3][0], - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)), - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) | - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7))); - - rk_clrsetreg(&grf->gpio4bl_iomux, - GPIO4B1_MASK << GPIO4B1_SHIFT, - GPIO4B1_MAC_TXCLK << GPIO4B1_SHIFT); - - /* switch GPIO4B1 to 12ma drive-strength */ - rk_clrsetreg(&grf->gpio1_e[3][1], - GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1), - GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)); - - /* Set pull normal for GPIO4B1 */ - rk_clrsetreg(&grf->gpio1_p[3][1], - (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)), - (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1))); - - break; - default: - printf("gmac id = %d iomux error!\n", gmac_id); - break; - } -} - -#ifndef CONFIG_SPL_BUILD -static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id) -{ - switch (hdmi_id) { - case PERIPH_ID_HDMI: - rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT, - GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT); - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT, - GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT); - break; - default: - debug("hdmi id = %d iomux error!\n", hdmi_id); - break; - } -} -#endif - -static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk3288_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%x, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - case PERIPH_ID_PWM4: - pinctrl_rk3288_pwm_config(priv->grf, func); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func); - break; - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - pinctrl_rk3288_spi_config(priv->grf, func, flags); - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - case PERIPH_ID_UART4: - pinctrl_rk3288_uart_config(priv->grf, func); - break; -#ifndef CONFIG_SPL_BUILD - case PERIPH_ID_LCDC0: - case PERIPH_ID_LCDC1: - pinctrl_rk3288_lcdc_config(priv->grf, func); - break; - case PERIPH_ID_HDMI: - pinctrl_rk3288_hdmi_config(priv->grf, func); - break; -#endif - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - pinctrl_rk3288_sdmmc_config(priv->grf, func); - break; - case PERIPH_ID_GMAC: - pinctrl_rk3288_gmac_config(priv->grf, func); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int rk3288_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - u32 cell[3]; - int ret; - - ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 27: - return PERIPH_ID_GMAC; - case 44: - return PERIPH_ID_SPI0; - case 45: - return PERIPH_ID_SPI1; - case 46: - return PERIPH_ID_SPI2; - case 60: - return PERIPH_ID_I2C0; - case 62: /* Note strange order */ - return PERIPH_ID_I2C1; - case 61: - return PERIPH_ID_I2C2; - case 63: - return PERIPH_ID_I2C3; - case 64: - return PERIPH_ID_I2C4; - case 65: - return PERIPH_ID_I2C5; - case 103: - return PERIPH_ID_HDMI; - } -#endif - - return -ENOENT; -} - -static int rk3288_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk3288_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - return rk3288_pinctrl_request(dev, func, 0); -} - -#ifndef CONFIG_SPL_BUILD -int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv, - int banknum, int ind, u32 **addrp, uint *shiftp, - uint *maskp) -{ - struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum]; - uint muxnum; - u32 *addr; - - for (muxnum = 0; muxnum < 4; muxnum++) { - struct rockchip_iomux *mux = &bank->iomux[muxnum]; - - if (ind >= 8) { - ind -= 8; - continue; - } - - if (mux->type & IOMUX_SOURCE_PMU) - addr = priv->pmu->gpio0_iomux; - else - addr = (u32 *)priv->grf - 4; - addr += mux->offset; - *shiftp = ind & 7; - if (mux->type & IOMUX_WIDTH_4BIT) { - *maskp = 0xf; - *shiftp *= 4; - if (*shiftp >= 16) { - *shiftp -= 16; - addr++; - } - } else { - *maskp = 3; - *shiftp *= 2; - } - - debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr, - *maskp, *shiftp); - *addrp = addr; - return 0; - } - - return -EINVAL; -} - -static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, - int index) -{ - struct rk3288_pinctrl_priv *priv = dev_get_priv(dev); - uint shift; - uint mask; - u32 *addr; - int ret; - - ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, - &mask); - if (ret) - return ret; - return (readl(addr) & mask) >> shift; -} - -static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, - int muxval, int flags) -{ - struct rk3288_pinctrl_priv *priv = dev_get_priv(dev); - uint shift, ind = index; - uint mask; - uint value; - u32 *addr; - int ret; - - debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags); - ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, - &mask); - if (ret) - return ret; - - /* - * PMU_GPIO0 registers cannot be selectively written so we cannot use - * rk_clrsetreg() here. However, the upper 16 bits are reserved and - * are ignored when written, so we can use the same code as for the - * other GPIO banks providing that we preserve the value of the other - * bits. - */ - value = readl(addr); - value &= ~(mask << shift); - value |= (mask << (shift + 16)) | (muxval << shift); - writel(value, addr); - - /* Handle pullup/pulldown/drive-strength */ - if (flags) { - uint val = 0; - - if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP)) - val = 1; - else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) - val = 2; - else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH)) - val = 3; - - shift = (index & 7) * 2; - ind = index >> 3; - if (banknum == 0) - addr = &priv->pmu->gpio0pull[ind]; - else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH)) - addr = &priv->grf->gpio1_e[banknum - 1][ind]; - else - addr = &priv->grf->gpio1_p[banknum - 1][ind]; - debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, - shift); - - /* As above, rk_clrsetreg() cannot be used here. */ - value = readl(addr); - value &= ~(mask << shift); - value |= (3 << (shift + 16)) | (val << shift); - writel(value, addr); - } - - return 0; -} - -static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config) -{ - const void *blob = gd->fdt_blob; - int pcfg_node, ret, flags, count, i; - u32 cell[60], *ptr; - - debug("%s: %s %s\n", __func__, dev->name, config->name); - ret = fdtdec_get_int_array_count(blob, dev_of_offset(config), - "rockchip,pins", cell, - ARRAY_SIZE(cell)); - if (ret < 0) { - debug("%s: bad array %d\n", __func__, ret); - return -EINVAL; - } - count = ret; - for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) { - pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]); - if (pcfg_node < 0) - return -EINVAL; - flags = pinctrl_decode_pin_config(blob, pcfg_node); - if (flags < 0) - return flags; - - if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12) - flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH; - - ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2], - flags); - if (ret) - return ret; - } - - return 0; -} -#endif - -static struct pinctrl_ops rk3288_pinctrl_ops = { -#ifndef CONFIG_SPL_BUILD - .set_state = rk3288_pinctrl_set_state, - .get_gpio_mux = rk3288_pinctrl_get_gpio_mux, -#endif - .set_state_simple = rk3288_pinctrl_set_state_simple, - .request = rk3288_pinctrl_request, - .get_periph_id = rk3288_pinctrl_get_periph_id, -}; - -#ifndef CONFIG_SPL_BUILD -static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv, - struct rockchip_pin_bank *banks, - int count) -{ - struct rockchip_pin_bank *bank; - uint reg, muxnum, banknum; - - reg = 0; - for (banknum = 0; banknum < count; banknum++) { - bank = &banks[banknum]; - bank->reg = reg; - debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4); - for (muxnum = 0; muxnum < 4; muxnum++) { - struct rockchip_iomux *mux = &bank->iomux[muxnum]; - - if (!(mux->type & IOMUX_UNROUTED)) - mux->offset = reg; - if (mux->type & IOMUX_WIDTH_4BIT) - reg += 2; - else - reg += 1; - } - } - - return 0; -} -#endif - -static int rk3288_pinctrl_probe(struct udevice *dev) -{ - struct rk3288_pinctrl_priv *priv = dev_get_priv(dev); - int ret = 0; - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); - debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu); -#ifndef CONFIG_SPL_BUILD - ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks, - ARRAY_SIZE(rk3288_pin_banks)); -#endif - - return ret; -} - -static const struct udevice_id rk3288_pinctrl_ids[] = { - { .compatible = "rockchip,rk3288-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3288) = { - .name = "rockchip_rk3288_pinctrl", - .id = UCLASS_PINCTRL, - .of_match = rk3288_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv), - .ops = &rk3288_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - .bind = dm_scan_fdt_dev, -#endif - .probe = rk3288_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c deleted file mode 100644 index fce41f3932..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ /dev/null @@ -1,705 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3328.h> -#include <asm/arch/periph.h> -#include <asm/io.h> -#include <dm/pinctrl.h> - -enum { - /* GPIO0A_IOMUX */ - GPIO0A5_SEL_SHIFT = 10, - GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, - GPIO0A5_I2C3_SCL = 2, - - GPIO0A6_SEL_SHIFT = 12, - GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, - GPIO0A6_I2C3_SDA = 2, - - GPIO0A7_SEL_SHIFT = 14, - GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, - GPIO0A7_EMMC_DATA0 = 2, - - /* GPIO0B_IOMUX*/ - GPIO0B0_SEL_SHIFT = 0, - GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT, - GPIO0B0_GAMC_CLKTXM0 = 1, - - GPIO0B4_SEL_SHIFT = 8, - GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT, - GPIO0B4_GAMC_TXENM0 = 1, - - /* GPIO0C_IOMUX*/ - GPIO0C0_SEL_SHIFT = 0, - GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT, - GPIO0C0_GAMC_TXD1M0 = 1, - - GPIO0C1_SEL_SHIFT = 2, - GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT, - GPIO0C1_GAMC_TXD0M0 = 1, - - GPIO0C6_SEL_SHIFT = 12, - GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT, - GPIO0C6_GAMC_TXD2M0 = 1, - - GPIO0C7_SEL_SHIFT = 14, - GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT, - GPIO0C7_GAMC_TXD3M0 = 1, - - /* GPIO0D_IOMUX*/ - GPIO0D0_SEL_SHIFT = 0, - GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT, - GPIO0D0_GMAC_CLKM0 = 1, - - GPIO0D6_SEL_SHIFT = 12, - GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, - GPIO0D6_GPIO = 0, - GPIO0D6_SDMMC0_PWRENM1 = 3, - - /* GPIO1A_IOMUX */ - GPIO1A0_SEL_SHIFT = 0, - GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, - GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, - - /* GPIO1B_IOMUX */ - GPIO1B0_SEL_SHIFT = 0, - GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT, - GPIO1B0_GMAC_TXD1M1 = 2, - - GPIO1B1_SEL_SHIFT = 2, - GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT, - GPIO1B1_GMAC_TXD0M1 = 2, - - GPIO1B2_SEL_SHIFT = 4, - GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT, - GPIO1B2_GMAC_RXD1M1 = 2, - - GPIO1B3_SEL_SHIFT = 6, - GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT, - GPIO1B3_GMAC_RXD0M1 = 2, - - GPIO1B4_SEL_SHIFT = 8, - GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT, - GPIO1B4_GMAC_TXCLKM1 = 2, - - GPIO1B5_SEL_SHIFT = 10, - GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT, - GPIO1B5_GMAC_RXCLKM1 = 2, - - GPIO1B6_SEL_SHIFT = 12, - GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT, - GPIO1B6_GMAC_RXD3M1 = 2, - - GPIO1B7_SEL_SHIFT = 14, - GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT, - GPIO1B7_GMAC_RXD2M1 = 2, - - /* GPIO1C_IOMUX */ - GPIO1C0_SEL_SHIFT = 0, - GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT, - GPIO1C0_GMAC_TXD3M1 = 2, - - GPIO1C1_SEL_SHIFT = 2, - GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT, - GPIO1C1_GMAC_TXD2M1 = 2, - - GPIO1C3_SEL_SHIFT = 6, - GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT, - GPIO1C3_GMAC_MDIOM1 = 2, - - GPIO1C5_SEL_SHIFT = 10, - GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT, - GPIO1C5_GMAC_CLKM1 = 2, - - GPIO1C6_SEL_SHIFT = 12, - GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT, - GPIO1C6_GMAC_RXDVM1 = 2, - - GPIO1C7_SEL_SHIFT = 14, - GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT, - GPIO1C7_GMAC_MDCM1 = 2, - - /* GPIO1D_IOMUX */ - GPIO1D1_SEL_SHIFT = 2, - GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT, - GPIO1D1_GMAC_TXENM1 = 2, - - /* GPIO2A_IOMUX */ - GPIO2A0_SEL_SHIFT = 0, - GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, - GPIO2A0_UART2_TX_M1 = 1, - - GPIO2A1_SEL_SHIFT = 2, - GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, - GPIO2A1_UART2_RX_M1 = 1, - - GPIO2A2_SEL_SHIFT = 4, - GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, - GPIO2A2_PWM_IR = 1, - - GPIO2A4_SEL_SHIFT = 8, - GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, - GPIO2A4_PWM_0 = 1, - GPIO2A4_I2C1_SDA, - - GPIO2A5_SEL_SHIFT = 10, - GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, - GPIO2A5_PWM_1 = 1, - GPIO2A5_I2C1_SCL, - - GPIO2A6_SEL_SHIFT = 12, - GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, - GPIO2A6_PWM_2 = 1, - - GPIO2A7_SEL_SHIFT = 14, - GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_SDMMC0_PWRENM0, - - /* GPIO2BL_IOMUX */ - GPIO2BL0_SEL_SHIFT = 0, - GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, - GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, - - GPIO2BL3_SEL_SHIFT = 6, - GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, - GPIO2BL3_SPI_CSN0_M0 = 1, - - GPIO2BL4_SEL_SHIFT = 8, - GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, - GPIO2BL4_SPI_CSN1_M0 = 1, - - GPIO2BL5_SEL_SHIFT = 10, - GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, - GPIO2BL5_I2C2_SDA = 1, - - GPIO2BL6_SEL_SHIFT = 12, - GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, - GPIO2BL6_I2C2_SCL = 1, - - /* GPIO2D_IOMUX */ - GPIO2D0_SEL_SHIFT = 0, - GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, - GPIO2D0_I2C0_SCL = 1, - - GPIO2D1_SEL_SHIFT = 2, - GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, - GPIO2D1_I2C0_SDA = 1, - - GPIO2D4_SEL_SHIFT = 8, - GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, - GPIO2D4_EMMC_DATA1234 = 0xaa, - - /* GPIO3C_IOMUX */ - GPIO3C0_SEL_SHIFT = 0, - GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, - GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, - - /* COM_IOMUX */ - IOMUX_SEL_UART2_SHIFT = 0, - IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, - IOMUX_SEL_UART2_M0 = 0, - IOMUX_SEL_UART2_M1, - - IOMUX_SEL_GMAC_SHIFT = 2, - IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT, - IOMUX_SEL_GMAC_M0 = 0, - IOMUX_SEL_GMAC_M1, - - IOMUX_SEL_SPI_SHIFT = 4, - IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, - IOMUX_SEL_SPI_M0 = 0, - IOMUX_SEL_SPI_M1, - IOMUX_SEL_SPI_M2, - - IOMUX_SEL_SDMMC_SHIFT = 7, - IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, - IOMUX_SEL_SDMMC_M0 = 0, - IOMUX_SEL_SDMMC_M1, - - IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10, - IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT, - IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0, - IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER, - - /* GRF_GPIO1B_E */ - GRF_GPIO1B0_E_SHIFT = 0, - GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT, - GRF_GPIO1B1_E_SHIFT = 2, - GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT, - GRF_GPIO1B2_E_SHIFT = 4, - GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT, - GRF_GPIO1B3_E_SHIFT = 6, - GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT, - GRF_GPIO1B4_E_SHIFT = 8, - GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT, - GRF_GPIO1B5_E_SHIFT = 10, - GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT, - GRF_GPIO1B6_E_SHIFT = 12, - GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT, - GRF_GPIO1B7_E_SHIFT = 14, - GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT, - - /* GRF_GPIO1C_E */ - GRF_GPIO1C0_E_SHIFT = 0, - GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT, - GRF_GPIO1C1_E_SHIFT = 2, - GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT, - GRF_GPIO1C3_E_SHIFT = 6, - GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT, - GRF_GPIO1C5_E_SHIFT = 10, - GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT, - GRF_GPIO1C6_E_SHIFT = 12, - GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT, - GRF_GPIO1C7_E_SHIFT = 14, - GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT, - - /* GRF_GPIO1D_E */ - GRF_GPIO1D1_E_SHIFT = 2, - GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT, -}; - -/* GPIO Bias drive strength settings */ -enum GPIO_BIAS { - GPIO_BIAS_2MA = 0, - GPIO_BIAS_4MA, - GPIO_BIAS_8MA, - GPIO_BIAS_12MA, -}; - -struct rk3328_pinctrl_priv { - struct rk3328_grf_regs *grf; -}; - -static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id) -{ - switch (pwm_id) { - case PERIPH_ID_PWM0: - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A4_SEL_MASK, - GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT); - break; - case PERIPH_ID_PWM1: - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A5_SEL_MASK, - GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT); - break; - case PERIPH_ID_PWM2: - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A6_SEL_MASK, - GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT); - break; - case PERIPH_ID_PWM3: - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A2_SEL_MASK, - GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT); - break; - default: - debug("pwm id = %d iomux error!\n", pwm_id); - break; - } -} - -static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id) -{ - switch (i2c_id) { - case PERIPH_ID_I2C0: - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK, - GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT | - GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT); - break; - case PERIPH_ID_I2C1: - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK, - GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT | - GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT); - break; - case PERIPH_ID_I2C2: - rk_clrsetreg(&grf->gpio2bl_iomux, - GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK, - GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT | - GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT); - break; - case PERIPH_ID_I2C3: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK, - GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT | - GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT); - break; - default: - debug("i2c id = %d iomux error!\n", i2c_id); - break; - } -} - -static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id) -{ - switch (lcd_id) { - case PERIPH_ID_LCDC0: - break; - default: - debug("lcdc id = %d iomux error!\n", lcd_id); - break; - } -} - -static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf, - enum periph_id spi_id, int cs) -{ - u32 com_iomux = readl(&grf->com_iomux); - - if ((com_iomux & IOMUX_SEL_SPI_MASK) != - IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) { - debug("driver do not support iomux other than m0\n"); - goto err; - } - - switch (spi_id) { - case PERIPH_ID_SPI0: - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio2bl_iomux, - GPIO2BL3_SEL_MASK, - GPIO2BL3_SPI_CSN0_M0 - << GPIO2BL3_SEL_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio2bl_iomux, - GPIO2BL4_SEL_MASK, - GPIO2BL4_SPI_CSN1_M0 - << GPIO2BL4_SEL_SHIFT); - break; - default: - goto err; - } - rk_clrsetreg(&grf->gpio2bl_iomux, - GPIO2BL0_SEL_MASK, - GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT); - break; - default: - goto err; - } - - return 0; -err: - debug("rkspi: periph%d cs=%d not supported", spi_id, cs); - return -ENOENT; -} - -static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id) -{ - u32 com_iomux = readl(&grf->com_iomux); - - switch (uart_id) { - case PERIPH_ID_UART2: - break; - if (com_iomux & IOMUX_SEL_UART2_MASK) - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK, - GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT | - GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); - - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART3: - case PERIPH_ID_UART4: - default: - debug("uart id = %d iomux error!\n", uart_id); - break; - } -} - -static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, - int mmc_id) -{ - u32 com_iomux = readl(&grf->com_iomux); - - switch (mmc_id) { - case PERIPH_ID_EMMC: - rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A7_SEL_MASK, - GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D4_SEL_MASK, - GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT); - rk_clrsetreg(&grf->gpio3c_iomux, - GPIO3C0_SEL_MASK, - GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD - << GPIO3C0_SEL_SHIFT); - break; - case PERIPH_ID_SDCARD: - /* SDMMC_PWREN use GPIO and init as regulator-fiexed */ - if (com_iomux & IOMUX_SEL_SDMMC_MASK) - rk_clrsetreg(&grf->gpio0d_iomux, - GPIO0D6_SEL_MASK, - GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT); - else - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A7_SEL_MASK, - GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT); - rk_clrsetreg(&grf->gpio1a_iomux, - GPIO1A0_SEL_MASK, - GPIO1A0_CARD_DATA_CLK_CMD_DETN - << GPIO1A0_SEL_SHIFT); - break; - default: - debug("mmc id = %d iomux error!\n", mmc_id); - break; - } -} - -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) -static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id) -{ - switch (gmac_id) { - case PERIPH_ID_GMAC: - /* set rgmii m1 pins mux */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B0_SEL_MASK | - GPIO1B1_SEL_MASK | - GPIO1B2_SEL_MASK | - GPIO1B3_SEL_MASK | - GPIO1B4_SEL_MASK | - GPIO1B5_SEL_MASK | - GPIO1B6_SEL_MASK | - GPIO1B7_SEL_MASK, - GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT | - GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT | - GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT | - GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT | - GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT | - GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT | - GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT | - GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT); - - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C0_SEL_MASK | - GPIO1C1_SEL_MASK | - GPIO1C3_SEL_MASK | - GPIO1C5_SEL_MASK | - GPIO1C6_SEL_MASK | - GPIO1C7_SEL_MASK, - GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT | - GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT | - GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT | - GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT | - GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT | - GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT); - - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D1_SEL_MASK, - GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT); - - /* set rgmii m0 tx pins mux */ - rk_clrsetreg(&grf->gpio0b_iomux, - GPIO0B0_SEL_MASK | - GPIO0B4_SEL_MASK, - GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT | - GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT); - - rk_clrsetreg(&grf->gpio0c_iomux, - GPIO0C0_SEL_MASK | - GPIO0C1_SEL_MASK | - GPIO0C6_SEL_MASK | - GPIO0C7_SEL_MASK, - GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT | - GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT | - GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT | - GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT); - - rk_clrsetreg(&grf->gpio0d_iomux, - GPIO0D0_SEL_MASK, - GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT); - - /* set com mux */ - rk_clrsetreg(&grf->com_iomux, - IOMUX_SEL_GMAC_MASK | - IOMUX_SEL_GMACM1_OPTIMIZATION_MASK, - IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT | - IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER << - IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT); - - /* - * set rgmii m1 tx pins to 12ma drive-strength, - * and clean others to 2ma. - */ - rk_clrsetreg(&grf->gpio1b_e, - GRF_GPIO1B0_E_MASK | - GRF_GPIO1B1_E_MASK | - GRF_GPIO1B2_E_MASK | - GRF_GPIO1B3_E_MASK | - GRF_GPIO1B4_E_MASK | - GRF_GPIO1B5_E_MASK | - GRF_GPIO1B6_E_MASK | - GRF_GPIO1B7_E_MASK, - GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT); - - rk_clrsetreg(&grf->gpio1c_e, - GRF_GPIO1C0_E_MASK | - GRF_GPIO1C1_E_MASK | - GRF_GPIO1C3_E_MASK | - GRF_GPIO1C5_E_MASK | - GRF_GPIO1C6_E_MASK | - GRF_GPIO1C7_E_MASK, - GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT | - GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT | - GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT); - - rk_clrsetreg(&grf->gpio1d_e, - GRF_GPIO1D1_E_MASK, - GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT); - break; - default: - debug("gmac id = %d iomux error!\n", gmac_id); - break; - } -} -#endif - -static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%x, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - pinctrl_rk3328_pwm_config(priv->grf, func); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - pinctrl_rk3328_i2c_config(priv->grf, func); - break; - case PERIPH_ID_SPI0: - pinctrl_rk3328_spi_config(priv->grf, func, flags); - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - case PERIPH_ID_UART4: - pinctrl_rk3328_uart_config(priv->grf, func); - break; - case PERIPH_ID_LCDC0: - case PERIPH_ID_LCDC1: - pinctrl_rk3328_lcdc_config(priv->grf, func); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - pinctrl_rk3328_sdmmc_config(priv->grf, func); - break; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case PERIPH_ID_GMAC: - pinctrl_rk3328_gmac_config(priv->grf, func); - break; -#endif - default: - return -EINVAL; - } - - return 0; -} - -static int rk3328_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ - u32 cell[3]; - int ret; - - ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 49: - return PERIPH_ID_SPI0; - case 50: - return PERIPH_ID_PWM0; - case 36: - return PERIPH_ID_I2C0; - case 37: /* Note strange order */ - return PERIPH_ID_I2C1; - case 38: - return PERIPH_ID_I2C2; - case 39: - return PERIPH_ID_I2C3; - case 12: - return PERIPH_ID_SDCARD; - case 14: - return PERIPH_ID_EMMC; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case 24: - return PERIPH_ID_GMAC; -#endif - } - - return -ENOENT; -} - -static int rk3328_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk3328_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - - return rk3328_pinctrl_request(dev, func, 0); -} - -static struct pinctrl_ops rk3328_pinctrl_ops = { - .set_state_simple = rk3328_pinctrl_set_state_simple, - .request = rk3328_pinctrl_request, - .get_periph_id = rk3328_pinctrl_get_periph_id, -}; - -static int rk3328_pinctrl_probe(struct udevice *dev) -{ - struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); - int ret = 0; - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - debug("%s: grf=%p\n", __func__, priv->grf); - - return ret; -} - -static const struct udevice_id rk3328_pinctrl_ids[] = { - { .compatible = "rockchip,rk3328-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3328) = { - .name = "rockchip_rk3328_pinctrl", - .id = UCLASS_PINCTRL, - .of_match = rk3328_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv), - .ops = &rk3328_pinctrl_ops, - .bind = dm_scan_fdt_dev, - .probe = rk3328_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c deleted file mode 100644 index 61df54f16d..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c +++ /dev/null @@ -1,739 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - * Author: Andy Yan <andy.yan@rock-chips.com> - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/periph.h> -#include <dm/pinctrl.h> - -/* PMUGRF_GPIO0B_IOMUX */ -enum { - GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT), - GPIO0B5_GPIO = 0, - GPIO0B5_SPI2_CSN0 = (2 << GPIO0B5_SHIFT), - - GPIO0B4_SHIFT = 8, - GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT), - GPIO0B4_GPIO = 0, - GPIO0B4_SPI2_CLK = (2 << GPIO0B4_SHIFT), - - GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT), - GPIO0B3_GPIO = 0, - GPIO0B3_SPI2_TXD = (2 << GPIO0B3_SHIFT), - - GPIO0B2_SHIFT = 4, - GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT), - GPIO0B2_GPIO = 0, - GPIO0B2_SPI2_RXD = (2 << GPIO0B2_SHIFT), -}; - -/*GRF_GPIO0C_IOMUX*/ -enum { - GPIO0C7_SHIFT = 14, - GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT), - GPIO0C7_GPIO = 0, - GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT), - GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT), - GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT), - - GPIO0C6_SHIFT = 12, - GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT), - GPIO0C6_GPIO = 0, - GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT), - GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT), - GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT), - - GPIO0C5_SHIFT = 10, - GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT), - GPIO0C5_GPIO = 0, - GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT), - GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT), - GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT), - - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT), - GPIO0C4_GPIO = 0, - GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT), - GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT), - GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT), - - GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT), - GPIO0C3_GPIO = 0, - GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT), - GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT), - GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT), - - GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT), - GPIO0C2_GPIO = 0, - GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT), - GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT), - GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT), - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT), - GPIO0C1_GPIO = 0, - GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT), - GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT), - GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT), - - GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT), - GPIO0C0_GPIO = 0, - GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT), - GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT), - GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT), -}; - -/*GRF_GPIO0D_IOMUX*/ -enum { - GPIO0D7_SHIFT = 14, - GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT), - GPIO0D7_GPIO = 0, - GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT), - GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT), - GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT), - - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT), - GPIO0D6_GPIO = 0, - GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT), - GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT), - GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT), - - GPIO0D5_SHIFT = 10, - GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT), - GPIO0D5_GPIO = 0, - GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT), - GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT), - GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT), - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT), - GPIO0D4_GPIO = 0, - GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT), - GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT), - GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT), - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT), - GPIO0D3_GPIO = 0, - GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT), - GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT), - GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT), - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT), - GPIO0D2_GPIO = 0, - GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT), - GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT), - GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT), - - GPIO0D1_SHIFT = 2, - GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT), - GPIO0D1_GPIO = 0, - GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT), - GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT), - GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT), - - GPIO0D0_SHIFT = 0, - GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT), - GPIO0D0_GPIO = 0, - GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT), - GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT), - GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT), -}; - -/*GRF_GPIO2A_IOMUX*/ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT), - GPIO2A7_GPIO = 0, - GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT), - GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT), - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT), - GPIO2A6_GPIO = 0, - GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT), - GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT), - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT), - GPIO2A5_GPIO = 0, - GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT), - GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT), - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT), - GPIO2A4_GPIO = 0, - GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT), - GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT), - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT), - GPIO2A3_GPIO = 0, - GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT), - GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT), - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT), - GPIO2A2_GPIO = 0, - GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT), - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT), - GPIO2A1_GPIO = 0, - GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT), - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT), - GPIO2A0_GPIO = 0, - GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT), -}; - -/*GRF_GPIO2B_IOMUX*/ -enum { - GPIO2B3_SHIFT = 6, - GPIO2B3_MASK = GENMASK(GPIO2B3_SHIFT + 1, GPIO2B3_SHIFT), - GPIO2B3_GPIO = 0, - GPIO2B3_SDMMC0_DTECTN = (1 << GPIO2B3_SHIFT), - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = GENMASK(GPIO2B2_SHIFT + 1, GPIO2B2_SHIFT), - GPIO2B2_GPIO = 0, - GPIO2B2_SDMMC0_CMD = (1 << GPIO2B2_SHIFT), - - GPIO2B1_SHIFT = 2, - GPIO2B1_MASK = GENMASK(GPIO2B1_SHIFT + 1, GPIO2B1_SHIFT), - GPIO2B1_GPIO = 0, - GPIO2B1_SDMMC0_CLKOUT = (1 << GPIO2B1_SHIFT), - - GPIO2B0_SHIFT = 0, - GPIO2B0_MASK = GENMASK(GPIO2B0_SHIFT + 1, GPIO2B0_SHIFT), - GPIO2B0_GPIO = 0, - GPIO2B0_SDMMC0_D3 = (1 << GPIO2B0_SHIFT), -}; - -/*GRF_GPIO2D_IOMUX*/ -enum { - GPIO2D7_SHIFT = 14, - GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT), - GPIO2D7_GPIO = 0, - GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT), - - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT), - GPIO2D6_GPIO = 0, - GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT), - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT), - GPIO2D5_GPIO = 0, - GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT), - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT), - GPIO2D4_GPIO = 0, - GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT), - - GPIO2D3_SHIFT = 6, - GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT), - GPIO2D3_GPIO = 0, - GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT), - - GPIO2D2_SHIFT = 4, - GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT), - GPIO2D2_GPIO = 0, - GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT), - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT), - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT), - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT), - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT), -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT), - GPIO1B7_GPIO = 0, - GPIO1B7_SPI1_CSN0 = (2 << GPIO1B7_SHIFT), - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT), - GPIO1B6_GPIO = 0, - GPIO1B6_SPI1_CLK = (2 << GPIO1B6_SHIFT), -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C7_SHIFT = 14, - GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT), - GPIO1C7_GPIO = 0, - GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT), - GPIO1C7_SPI0_TXD = (3 << GPIO1C7_SHIFT), - - GPIO1C6_SHIFT = 12, - GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT), - GPIO1C6_GPIO = 0, - GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT), - GPIO1C6_SPI0_RXD = (3 << GPIO1C6_SHIFT), - - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT), - GPIO1C5_GPIO = 0, - GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT), - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT), - GPIO1C4_GPIO = 0, - GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT), - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT), - GPIO1C3_GPIO = 0, - GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT), - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT), - GPIO1C2_GPIO = 0, - GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT), - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT), - GPIO1C1_GPIO = 0, - GPIO1C1_SPI1_RXD = (2 << GPIO1C1_SHIFT), - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT), - GPIO1C0_GPIO = 0, - GPIO1C0_SPI1_TXD = (2 << GPIO1C0_SHIFT), -}; - -/* GRF_GPIO1D_IOMUX*/ -enum { - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT), - GPIO1D5_GPIO = 0, - GPIO1D5_SPI0_CLK = (2 << GPIO1D5_SHIFT), - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT), - GPIO1D3_GPIO = 0, - GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT), - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT), - GPIO1D2_GPIO = 0, - GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT), - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT), - GPIO1D1_GPIO = 0, - GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT), - GPIO1D1_SPI0_CSN1 = (3 << GPIO1D1_SHIFT), - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT), - GPIO1D0_GPIO = 0, - GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT), - GPIO1D0_SPI0_CSN0 = (3 << GPIO1D0_SHIFT), -}; - - -/*GRF_GPIO3B_IOMUX*/ -enum { - GPIO3B7_SHIFT = 14, - GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT), - GPIO3B7_GPIO = 0, - GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT), - - GPIO3B6_SHIFT = 12, - GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT), - GPIO3B6_GPIO = 0, - GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT), - - GPIO3B5_SHIFT = 10, - GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT), - GPIO3B5_GPIO = 0, - GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT), - - GPIO3B4_SHIFT = 8, - GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT), - GPIO3B4_GPIO = 0, - GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT), - - GPIO3B3_SHIFT = 6, - GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT), - GPIO3B3_GPIO = 0, - GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT), - - GPIO3B2_SHIFT = 4, - GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT), - GPIO3B2_GPIO = 0, - GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT), - - GPIO3B1_SHIFT = 2, - GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT), - GPIO3B1_GPIO = 0, - GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT), - - GPIO3B0_SHIFT = 0, - GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT), - GPIO3B0_GPIO = 0, - GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT), - GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT), -}; - -/*GRF_GPIO3C_IOMUX*/ -enum { - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT), - GPIO3C6_GPIO = 0, - GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT), - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT), - GPIO3C5_GPIO = 0, - GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT), - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT), - GPIO3C4_GPIO = 0, - GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT), - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT), - GPIO3C3_GPIO = 0, - GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT), - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT), - GPIO3C2_GPIO = 0, - GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT), - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT), - GPIO3C1_GPIO = 0, - GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT), - - GPIO3C0_SHIFT = 0, - GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT), - GPIO3C0_GPIO = 0, - GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT), -}; - -/*GRF_GPIO3D_IOMUX*/ -enum { - GPIO3D4_SHIFT = 8, - GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT), - GPIO3D4_GPIO = 0, - GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT), - GPIO3D4_SPI1_CNS1 = (2 << GPIO3D4_SHIFT), - - GPIO3D1_SHIFT = 2, - GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT), - GPIO3D1_GPIO = 0, - GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT), - - GPIO3D0_SHIFT = 0, - GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT), - GPIO3D0_GPIO = 0, - GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT), -}; - -struct rk3368_pinctrl_priv { - struct rk3368_grf *grf; - struct rk3368_pmu_grf *pmugrf; -}; - -static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv, - int uart_id) -{ - struct rk3368_grf *grf = priv->grf; - struct rk3368_pmu_grf *pmugrf = priv->pmugrf; - - switch (uart_id) { - case PERIPH_ID_UART2: - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A6_MASK | GPIO2A5_MASK, - GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT); - break; - case PERIPH_ID_UART0: - break; - case PERIPH_ID_UART1: - break; - case PERIPH_ID_UART3: - break; - case PERIPH_ID_UART4: - rk_clrsetreg(&pmugrf->gpio0d_iomux, - GPIO0D0_MASK | GPIO0D1_MASK | - GPIO0D2_MASK | GPIO0D3_MASK, - GPIO0D0_GPIO | GPIO0D1_GPIO | - GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN); - break; - default: - debug("uart id = %d iomux error!\n", uart_id); - break; - } -} - -static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv, - int spi_id) -{ - struct rk3368_grf *grf = priv->grf; - struct rk3368_pmu_grf *pmugrf = priv->pmugrf; - - switch (spi_id) { - case PERIPH_ID_SPI0: - /* - * eMMC can only be connected with 4 bits, when SPI0 is used. - * This is all-or-nothing, so we assume that if someone asks us - * to configure SPI0, that their eMMC interface is unused or - * configured appropriately. - */ - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D0_MASK | GPIO1D1_MASK | - GPIO1D5_MASK, - GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 | - GPIO1D5_SPI0_CLK); - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C6_MASK | GPIO1C7_MASK, - GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD); - break; - case PERIPH_ID_SPI1: - /* - * We don't implement support for configuring SPI1_CSN#1, as it - * conflicts with the GMAC (MAC TX clk-out). - */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B6_MASK | GPIO1B7_MASK, - GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0); - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C0_MASK | GPIO1C1_MASK, - GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD); - break; - case PERIPH_ID_SPI2: - rk_clrsetreg(&pmugrf->gpio0b_iomux, - GPIO0B2_MASK | GPIO0B3_MASK | - GPIO0B4_MASK | GPIO0B5_MASK, - GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD | - GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0); - break; - default: - debug("%s: spi id = %d iomux error!\n", __func__, spi_id); - break; - } -} - -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) -static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id) -{ - rk_clrsetreg(&grf->gpio3b_iomux, - GPIO3B0_MASK | GPIO3B1_MASK | - GPIO3B2_MASK | GPIO3B5_MASK | - GPIO3B6_MASK | GPIO3B7_MASK, - GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 | - GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN | - GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0); - rk_clrsetreg(&grf->gpio3c_iomux, - GPIO3C0_MASK | GPIO3C1_MASK | - GPIO3C2_MASK | GPIO3C3_MASK | - GPIO3C4_MASK | GPIO3C5_MASK | - GPIO3C6_MASK, - GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 | - GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC | - GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN | - GPIO3C6_MAC_CLK); - rk_clrsetreg(&grf->gpio3d_iomux, - GPIO3D0_MASK | GPIO3D1_MASK | - GPIO3D4_MASK, - GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK | - GPIO3D4_MAC_TXCLK); -} -#endif - -static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id) -{ - switch (mmc_id) { - case PERIPH_ID_EMMC: - debug("mmc id = %d setting registers!\n", mmc_id); - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C2_MASK | GPIO1C3_MASK | - GPIO1C4_MASK | GPIO1C5_MASK | - GPIO1C6_MASK | GPIO1C7_MASK, - GPIO1C2_EMMC_DATA0 | - GPIO1C3_EMMC_DATA1 | - GPIO1C4_EMMC_DATA2 | - GPIO1C5_EMMC_DATA3 | - GPIO1C6_EMMC_DATA4 | - GPIO1C7_EMMC_DATA5); - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D0_MASK | GPIO1D1_MASK | - GPIO1D2_MASK | GPIO1D3_MASK, - GPIO1D0_EMMC_DATA6 | - GPIO1D1_EMMC_DATA7 | - GPIO1D2_EMMC_CMD | - GPIO1D3_EMMC_PWREN); - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A3_MASK | GPIO2A4_MASK, - GPIO2A3_EMMC_RSTNOUT | - GPIO2A4_EMMC_CLKOUT); - break; - case PERIPH_ID_SDCARD: - debug("mmc id = %d setting registers!\n", mmc_id); - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A5_MASK | GPIO2A7_MASK | - GPIO2A7_MASK, - GPIO2A5_SDMMC0_D0 | GPIO2A6_SDMMC0_D1 | - GPIO2A7_SDMMC0_D2); - rk_clrsetreg(&grf->gpio2b_iomux, - GPIO2B0_MASK | GPIO2B1_MASK | - GPIO2B2_MASK | GPIO2B3_MASK, - GPIO2B0_SDMMC0_D3 | GPIO2B1_SDMMC0_CLKOUT | - GPIO2B2_SDMMC0_CMD | GPIO2B3_SDMMC0_DTECTN); - break; - default: - debug("mmc id = %d iomux error!\n", mmc_id); - break; - } -} - -static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk3368_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%d, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - case PERIPH_ID_UART4: - pinctrl_rk3368_uart_config(priv, func); - break; - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - pinctrl_rk3368_spi_config(priv, func); - break; - case PERIPH_ID_EMMC: - case PERIPH_ID_SDCARD: - pinctrl_rk3368_sdmmc_config(priv->grf, func); - break; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case PERIPH_ID_GMAC: - pinctrl_rk3368_gmac_config(priv->grf, func); - break; -#endif - default: - return -EINVAL; - } - - return 0; -} - -static int rk3368_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ - u32 cell[3]; - int ret; - - ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 59: - return PERIPH_ID_UART4; - case 58: - return PERIPH_ID_UART3; - case 57: - return PERIPH_ID_UART2; - case 56: - return PERIPH_ID_UART1; - case 55: - return PERIPH_ID_UART0; - case 44: - return PERIPH_ID_SPI0; - case 45: - return PERIPH_ID_SPI1; - case 41: - return PERIPH_ID_SPI2; - case 35: - return PERIPH_ID_EMMC; - case 32: - return PERIPH_ID_SDCARD; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case 27: - return PERIPH_ID_GMAC; -#endif - } - - return -ENOENT; -} - -static int rk3368_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk3368_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - - return rk3368_pinctrl_request(dev, func, 0); -} - -static struct pinctrl_ops rk3368_pinctrl_ops = { - .set_state_simple = rk3368_pinctrl_set_state_simple, - .request = rk3368_pinctrl_request, - .get_periph_id = rk3368_pinctrl_get_periph_id, -}; - -static int rk3368_pinctrl_probe(struct udevice *dev) -{ - struct rk3368_pinctrl_priv *priv = dev_get_priv(dev); - int ret = 0; - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - - debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf); - - return ret; -} - -static const struct udevice_id rk3368_pinctrl_ids[] = { - { .compatible = "rockchip,rk3368-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3368) = { - .name = "rockchip_rk3368_pinctrl", - .id = UCLASS_PINCTRL, - .of_match = rk3368_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv), - .ops = &rk3368_pinctrl_ops, - .bind = dm_scan_fdt_dev, - .probe = rk3368_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c deleted file mode 100644 index 5c5af3a0bd..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ /dev/null @@ -1,740 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) 2018 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/clock.h> -#include <dm/pinctrl.h> - -#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) -static const u32 RK_GRF_P_PULLUP = 1; -static const u32 RK_GRF_P_PULLDOWN = 2; -#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ - -struct rk3399_pinctrl_priv { - struct rk3399_grf_regs *grf; - struct rk3399_pmugrf_regs *pmugrf; - struct rockchip_pin_bank *banks; -}; - -#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) -/* Location of pinctrl/pinconf registers. */ -enum rk_grf_location { - RK_GRF, - RK_PMUGRF, -}; - -/** - * @nr_pins: number of pins in this bank - * @grf_location: location of pinctrl/pinconf registers - * @bank_num: number of the bank, to account for holes - * @iomux: array describing the 4 iomux sources of the bank - */ -struct rockchip_pin_bank { - u8 nr_pins; - enum rk_grf_location grf_location; - size_t iomux_offset; - size_t pupd_offset; -}; - -#define PIN_BANK(pins, grf, iomux, pupd) \ - { \ - .nr_pins = pins, \ - .grf_location = grf, \ - .iomux_offset = iomux, \ - .pupd_offset = pupd, \ - } - -static struct rockchip_pin_bank rk3399_pin_banks[] = { - PIN_BANK(16, RK_PMUGRF, - offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux), - offsetof(struct rk3399_pmugrf_regs, gpio0_p)), - PIN_BANK(32, RK_PMUGRF, - offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux), - offsetof(struct rk3399_pmugrf_regs, gpio1_p)), - PIN_BANK(32, RK_GRF, - offsetof(struct rk3399_grf_regs, gpio2a_iomux), - offsetof(struct rk3399_grf_regs, gpio2_p)), - PIN_BANK(32, RK_GRF, - offsetof(struct rk3399_grf_regs, gpio3a_iomux), - offsetof(struct rk3399_grf_regs, gpio3_p)), - PIN_BANK(32, RK_GRF, - offsetof(struct rk3399_grf_regs, gpio4a_iomux), - offsetof(struct rk3399_grf_regs, gpio4_p)), -}; - -static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr, - u32 *shift, u32 *mask) -{ - /* - * In general we four subsequent 32-bit configuration registers - * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P). - * The configuration for each pin has two bits. - * - * @base...contains the address to the first register. - * @index...defines the pin within the bank (0..31). - * @addr...will be the address of the actual register to use - * @shift...will be the bit position in the configuration register - * @mask...will be the (unshifted) mask - */ - - const u32 pins_per_register = 8; - const u32 config_bits_per_pin = 2; - - /* Get the address of the configuration register. */ - *addr = base + (index / pins_per_register) * sizeof(u32); - - /* Get the bit offset within the configuration register. */ - *shift = (index & (pins_per_register - 1)) * config_bits_per_pin; - - /* Get the (unshifted) mask for the configuration pins. */ - *mask = ((1 << config_bits_per_pin) - 1); - - pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n", - __func__, *addr, *mask, *shift); -} - -static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr, - struct rockchip_pin_bank *bank, - u32 index, u32 muxval) -{ - uintptr_t iomux_base, addr; - u32 shift, mask; - - iomux_base = grf_addr + bank->iomux_offset; - rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask); - - /* Set pinmux register */ - rk_clrsetreg(addr, mask << shift, muxval << shift); -} - -static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr, - struct rockchip_pin_bank *bank, - u32 index, int pinconfig) -{ - uintptr_t pupd_base, addr; - u32 shift, mask, pupdval; - - /* Fast path in case there's nothing to do. */ - if (!pinconfig) - return; - - if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP)) - pupdval = RK_GRF_P_PULLUP; - else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) { - pupdval = RK_GRF_P_PULLDOWN; - } else { - /* Flag not supported. */ - pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__, - pinconfig); - return; - } - - pupd_base = grf_addr + (uintptr_t)bank->pupd_offset; - rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask); - - /* Set pull-up/pull-down regisrer */ - rk_clrsetreg(addr, mask << shift, pupdval << shift); -} - -static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index, - u32 muxval, int pinconfig) -{ - struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); - struct rockchip_pin_bank *bank = &priv->banks[banknum]; - uintptr_t grf_addr; - - pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval, - pinconfig); - - if (bank->grf_location == RK_GRF) - grf_addr = (uintptr_t)priv->grf; - else if (bank->grf_location == RK_PMUGRF) - grf_addr = (uintptr_t)priv->pmugrf; - else - return -EINVAL; - - rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval); - - rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig); - return 0; -} - -static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config) -{ - /* - * The order of the fields in this struct must match the order of - * the fields in the "rockchip,pins" property. - */ - struct rk_pin { - u32 banknum; - u32 index; - u32 muxval; - u32 phandle; - } __packed; - - u32 *fields = NULL; - const int fields_per_pin = 4; - int num_fields, num_pins; - int ret; - int size; - int i; - struct rk_pin *pin; - - pr_debug("%s: %s\n", __func__, config->name); - - size = dev_read_size(config, "rockchip,pins"); - if (size < 0) - return -EINVAL; - - num_fields = size / sizeof(u32); - num_pins = num_fields / fields_per_pin; - - if (num_fields * sizeof(u32) != size || - num_pins * fields_per_pin != num_fields) { - pr_warn("Invalid number of rockchip,pins fields.\n"); - return -EINVAL; - } - - fields = calloc(num_fields, sizeof(u32)); - if (!fields) - return -ENOMEM; - - ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields); - if (ret) { - pr_warn("%s: Failed to read rockchip,pins fields.\n", - config->name); - goto end; - } - - pin = (struct rk_pin *)fields; - for (i = 0; i < num_pins; i++, pin++) { - struct udevice *dev_pinconfig; - int pinconfig; - - ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG, - pin->phandle, - &dev_pinconfig); - if (ret) { - pr_debug("Could not get pinconfig device\n"); - goto end; - } - - pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig); - if (pinconfig < 0) { - pr_warn("Could not parse pinconfig\n"); - goto end; - } - - ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index, - pin->muxval, pinconfig); - if (ret) { - pr_warn("Could not set pinctrl settings\n"); - goto end; - } - } - -end: - free(fields); - return ret; -} - -#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ - -static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, - struct rk3399_pmugrf_regs *pmugrf, int pwm_id) -{ - switch (pwm_id) { - case PERIPH_ID_PWM0: - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C2_SEL_MASK, - GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT); - break; - case PERIPH_ID_PWM1: - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C6_SEL_MASK, - GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT); - break; - case PERIPH_ID_PWM2: - rk_clrsetreg(&pmugrf->gpio1c_iomux, - PMUGRF_GPIO1C3_SEL_MASK, - PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT); - break; - case PERIPH_ID_PWM3: - if (readl(&pmugrf->soc_con0) & (1 << 5)) - rk_clrsetreg(&pmugrf->gpio1b_iomux, - PMUGRF_GPIO1B6_SEL_MASK, - PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT); - else - rk_clrsetreg(&pmugrf->gpio0a_iomux, - PMUGRF_GPIO0A6_SEL_MASK, - PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT); - break; - default: - debug("pwm id = %d iomux error!\n", pwm_id); - break; - } -} - -static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, - struct rk3399_pmugrf_regs *pmugrf, - int i2c_id) -{ - switch (i2c_id) { - case PERIPH_ID_I2C0: - rk_clrsetreg(&pmugrf->gpio1b_iomux, - PMUGRF_GPIO1B7_SEL_MASK, - PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT); - rk_clrsetreg(&pmugrf->gpio1c_iomux, - PMUGRF_GPIO1C0_SEL_MASK, - PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT); - break; - - case PERIPH_ID_I2C1: - rk_clrsetreg(&grf->gpio4a_iomux, - GRF_GPIO4A1_SEL_MASK, - GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT); - rk_clrsetreg(&grf->gpio4a_iomux, - GRF_GPIO4A2_SEL_MASK, - GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT); - break; - - case PERIPH_ID_I2C2: - rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A0_SEL_MASK, - GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A1_SEL_MASK, - GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT); - break; - case PERIPH_ID_I2C3: - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C0_SEL_MASK, - GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT); - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C1_SEL_MASK, - GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT); - break; - - case PERIPH_ID_I2C4: - rk_clrsetreg(&pmugrf->gpio1b_iomux, - PMUGRF_GPIO1B3_SEL_MASK, - PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT); - rk_clrsetreg(&pmugrf->gpio1b_iomux, - PMUGRF_GPIO1B4_SEL_MASK, - PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT); - break; - - case PERIPH_ID_I2C7: - rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A7_SEL_MASK, - GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2b_iomux, - GRF_GPIO2B0_SEL_MASK, - GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT); - break; - - case PERIPH_ID_I2C6: - rk_clrsetreg(&grf->gpio2b_iomux, - GRF_GPIO2B1_SEL_MASK, - GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2b_iomux, - GRF_GPIO2B2_SEL_MASK, - GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT); - break; - - case PERIPH_ID_I2C8: - rk_clrsetreg(&pmugrf->gpio1c_iomux, - PMUGRF_GPIO1C4_SEL_MASK, - PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT); - rk_clrsetreg(&pmugrf->gpio1c_iomux, - PMUGRF_GPIO1C5_SEL_MASK, - PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT); - break; - - case PERIPH_ID_I2C5: - default: - debug("i2c id = %d iomux error!\n", i2c_id); - break; - } -} - -static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id) -{ - switch (lcd_id) { - case PERIPH_ID_LCDC0: - break; - default: - debug("lcdc id = %d iomux error!\n", lcd_id); - break; - } -} - -static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf, - struct rk3399_pmugrf_regs *pmugrf, - enum periph_id spi_id, int cs) -{ - switch (spi_id) { - case PERIPH_ID_SPI0: - switch (cs) { - case 0: - rk_clrsetreg(&grf->gpio3a_iomux, - GRF_GPIO3A7_SEL_MASK, - GRF_SPI0NORCODEC_CSN0 - << GRF_GPIO3A7_SEL_SHIFT); - break; - case 1: - rk_clrsetreg(&grf->gpio3b_iomux, - GRF_GPIO3B0_SEL_MASK, - GRF_SPI0NORCODEC_CSN1 - << GRF_GPIO3B0_SEL_SHIFT); - break; - default: - goto err; - } - rk_clrsetreg(&grf->gpio3a_iomux, - GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT - | GRF_GPIO3A6_SEL_SHIFT, - GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT - | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT - | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT); - break; - case PERIPH_ID_SPI1: - if (cs != 0) - goto err; - rk_clrsetreg(&pmugrf->gpio1a_iomux, - PMUGRF_GPIO1A7_SEL_MASK, - PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT); - rk_clrsetreg(&pmugrf->gpio1b_iomux, - PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK - | PMUGRF_GPIO1B2_SEL_MASK, - PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT - | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT - | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT); - break; - case PERIPH_ID_SPI2: - if (cs != 0) - goto err; - rk_clrsetreg(&grf->gpio2b_iomux, - GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK - | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK, - GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT - | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT - | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT - | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT); - break; - case PERIPH_ID_SPI5: - if (cs != 0) - goto err; - rk_clrsetreg(&grf->gpio2c_iomux, - GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK - | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK, - GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT - | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT - | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT - | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT); - break; - default: - printf("%s: spi_id %d is not supported.\n", __func__, spi_id); - goto err; - } - - return 0; -err: - debug("rkspi: periph%d cs=%d not supported", spi_id, cs); - return -ENOENT; -} - -static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf, - struct rk3399_pmugrf_regs *pmugrf, - int uart_id) -{ - switch (uart_id) { - case PERIPH_ID_UART2: - /* Using channel-C by default */ - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C4_SEL_MASK, - GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART3: - case PERIPH_ID_UART4: - default: - debug("uart id = %d iomux error!\n", uart_id); - break; - } -} - -static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) -{ - switch (mmc_id) { - case PERIPH_ID_EMMC: - break; - case PERIPH_ID_SDCARD: - rk_clrsetreg(&grf->gpio4b_iomux, - GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK - | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK - | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK, - GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT - | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT - | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT - | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT - | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT - | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT); - break; - default: - debug("mmc id = %d iomux error!\n", mmc_id); - break; - } -} - -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) -static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) -{ - rk_clrsetreg(&grf->gpio3a_iomux, - GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK | - GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK | - GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK | - GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK, - GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT | - GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT | - GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT | - GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT | - GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT | - GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT | - GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT | - GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT); - rk_clrsetreg(&grf->gpio3b_iomux, - GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK | - GRF_GPIO3B3_SEL_MASK | - GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK | - GRF_GPIO3B6_SEL_MASK, - GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT | - GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT | - GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT | - GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT | - GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT | - GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT); - rk_clrsetreg(&grf->gpio3c_iomux, - GRF_GPIO3C1_SEL_MASK, - GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); - - /* Set drive strength for GMAC tx io, value 3 means 13mA */ - rk_clrsetreg(&grf->gpio3_e[0], - GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK | - GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK, - 3 << GRF_GPIO3A0_E_SHIFT | - 3 << GRF_GPIO3A1_E_SHIFT | - 3 << GRF_GPIO3A4_E_SHIFT | - 1 << GRF_GPIO3A5_E0_SHIFT); - rk_clrsetreg(&grf->gpio3_e[1], - GRF_GPIO3A5_E12_MASK, - 1 << GRF_GPIO3A5_E12_SHIFT); - rk_clrsetreg(&grf->gpio3_e[2], - GRF_GPIO3B4_E_MASK, - 3 << GRF_GPIO3B4_E_SHIFT); - rk_clrsetreg(&grf->gpio3_e[4], - GRF_GPIO3C1_E_MASK, - 3 << GRF_GPIO3C1_E_SHIFT); -} -#endif - -#if !defined(CONFIG_SPL_BUILD) -static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id) -{ - switch (hdmi_id) { - case PERIPH_ID_HDMI: - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK, - (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) | - (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT)); - break; - default: - debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id); - break; - } -} -#endif - -static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); - - debug("%s: func=%x, flags=%x\n", __func__, func, flags); - switch (func) { - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - case PERIPH_ID_PWM4: - pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - case PERIPH_ID_I2C8: - pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func); - break; - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - case PERIPH_ID_SPI3: - case PERIPH_ID_SPI4: - case PERIPH_ID_SPI5: - pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags); - break; - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - case PERIPH_ID_UART4: - pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func); - break; - case PERIPH_ID_LCDC0: - case PERIPH_ID_LCDC1: - pinctrl_rk3399_lcdc_config(priv->grf, func); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - pinctrl_rk3399_sdmmc_config(priv->grf, func); - break; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case PERIPH_ID_GMAC: - pinctrl_rk3399_gmac_config(priv->grf, func); - break; -#endif -#if !defined(CONFIG_SPL_BUILD) - case PERIPH_ID_HDMI: - pinctrl_rk3399_hdmi_config(priv->grf, func); - break; -#endif - default: - return -EINVAL; - } - - return 0; -} - -static int rk3399_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - u32 cell[3]; - int ret; - - ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 68: - return PERIPH_ID_SPI0; - case 53: - return PERIPH_ID_SPI1; - case 52: - return PERIPH_ID_SPI2; - case 132: - return PERIPH_ID_SPI5; - case 57: - return PERIPH_ID_I2C0; - case 59: /* Note strange order */ - return PERIPH_ID_I2C1; - case 35: - return PERIPH_ID_I2C2; - case 34: - return PERIPH_ID_I2C3; - case 56: - return PERIPH_ID_I2C4; - case 38: - return PERIPH_ID_I2C5; - case 37: - return PERIPH_ID_I2C6; - case 36: - return PERIPH_ID_I2C7; - case 58: - return PERIPH_ID_I2C8; - case 65: - return PERIPH_ID_SDMMC1; -#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) - case 12: - return PERIPH_ID_GMAC; -#endif -#if !defined(CONFIG_SPL_BUILD) - case 23: - return PERIPH_ID_HDMI; -#endif - } -#endif - return -ENOENT; -} - -static int rk3399_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rk3399_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - - return rk3399_pinctrl_request(dev, func, 0); -} - -static struct pinctrl_ops rk3399_pinctrl_ops = { -#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) - .set_state = rk3399_pinctrl_set_state, -#endif - .set_state_simple = rk3399_pinctrl_set_state_simple, - .request = rk3399_pinctrl_request, - .get_periph_id = rk3399_pinctrl_get_periph_id, -}; - -static int rk3399_pinctrl_probe(struct udevice *dev) -{ - struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); - int ret = 0; - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); -#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) - priv->banks = rk3399_pin_banks; -#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ - - return ret; -} - -static const struct udevice_id rk3399_pinctrl_ids[] = { - { .compatible = "rockchip,rk3399-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rk3399) = { - .name = "rockchip_rk3399_pinctrl", - .id = UCLASS_PINCTRL, - .of_match = rk3399_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv), - .ops = &rk3399_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - .bind = dm_scan_fdt_dev, -#endif - .probe = rk3399_pinctrl_probe, -}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c deleted file mode 100644 index 5fb3915aa9..0000000000 --- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c +++ /dev/null @@ -1,580 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * Author: Andy Yan <andy.yan@rock-chips.com> - */ -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rv1108.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <dm/pinctrl.h> - -struct rv1108_pinctrl_priv { - struct rv1108_grf *grf; -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, - GPIO1B7_GPIO = 0, - GPIO1B7_LCDC_D12, - GPIO1B7_I2S_SDIO2_M0, - GPIO1B7_GMAC_RXDV, - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, - GPIO1B6_GPIO = 0, - GPIO1B6_LCDC_D13, - GPIO1B6_I2S_LRCLKTX_M0, - GPIO1B6_GMAC_RXD1, - - GPIO1B5_SHIFT = 10, - GPIO1B5_MASK = 3 << GPIO1B5_SHIFT, - GPIO1B5_GPIO = 0, - GPIO1B5_LCDC_D14, - GPIO1B5_I2S_SDIO1_M0, - GPIO1B5_GMAC_RXD0, - - GPIO1B4_SHIFT = 8, - GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, - GPIO1B4_GPIO = 0, - GPIO1B4_LCDC_D15, - GPIO1B4_I2S_MCLK_M0, - GPIO1B4_GMAC_TXEN, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, - GPIO1B3_GPIO = 0, - GPIO1B3_LCDC_D16, - GPIO1B3_I2S_SCLK_M0, - GPIO1B3_GMAC_TXD1, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_LCDC_D17, - GPIO1B2_I2S_SDIO_M0, - GPIO1B2_GMAC_TXD0, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_LCDC_D9, - GPIO1B1_PWM7, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 3, - GPIO1B0_GPIO = 0, - GPIO1B0_LCDC_D8, - GPIO1B0_PWM6, -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C7_SHIFT = 14, - GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, - GPIO1C7_GPIO = 0, - GPIO1C7_CIF_D5, - GPIO1C7_I2S_SDIO2_M1, - - GPIO1C6_SHIFT = 12, - GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, - GPIO1C6_GPIO = 0, - GPIO1C6_CIF_D4, - GPIO1C6_I2S_LRCLKTX_M1, - - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, - GPIO1C5_GPIO = 0, - GPIO1C5_LCDC_CLK, - GPIO1C5_GMAC_CLK, - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, - GPIO1C4_GPIO = 0, - GPIO1C4_LCDC_HSYNC, - GPIO1C4_GMAC_MDC, - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, - GPIO1C3_GPIO = 0, - GPIO1C3_LCDC_VSYNC, - GPIO1C3_GMAC_MDIO, - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, - GPIO1C2_GPIO = 0, - GPIO1C2_LCDC_EN, - GPIO1C2_I2S_SDIO3_M0, - GPIO1C2_GMAC_RXER, - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, - GPIO1C1_GPIO = 0, - GPIO1C1_LCDC_D10, - GPIO1C1_I2S_SDI_M0, - GPIO1C1_PWM4, - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 3, - GPIO1C0_GPIO = 0, - GPIO1C0_LCDC_D11, - GPIO1C0_I2S_LRCLKRX_M0, -}; - -/* GRF_GPIO1D_OIMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, - GPIO1D7_GPIO = 0, - GPIO1D7_HDMI_CEC, - GPIO1D7_DSP_RTCK, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 1 << GPIO1D6_SHIFT, - GPIO1D6_GPIO = 0, - GPIO1D6_HDMI_HPD_M0, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, - GPIO1D5_GPIO = 0, - GPIO1D5_UART2_RTSN, - GPIO1D5_HDMI_SDA_M0, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, - GPIO1D4_GPIO = 0, - GPIO1D4_UART2_CTSN, - GPIO1D4_HDMI_SCL_M0, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_UART0_SOUT, - GPIO1D3_SPI_TXD_M0, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_UART0_SIN, - GPIO1D2_SPI_RXD_M0, - GPIO1D2_DSP_TDI, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, - GPIO1D1_GPIO = 0, - GPIO1D1_UART0_RTSN, - GPIO1D1_SPI_CSN0_M0, - GPIO1D1_DSP_TMS, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3, - GPIO1D0_GPIO = 0, - GPIO1D0_UART0_CTSN, - GPIO1D0_SPI_CLK_M0, - GPIO1D0_DSP_TCK, -}; - -/* GRF_GPIO2A_IOMUX */ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_FLASH_D7, - GPIO2A7_EMMC_D7, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_FLASH_D6, - GPIO2A6_EMMC_D6, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_FLASH_D5, - GPIO2A5_EMMC_D5, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_FLASH_D4, - GPIO2A4_EMMC_D4, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_FLASH_D3, - GPIO2A3_EMMC_D3, - GPIO2A3_SFC_HOLD_IO3, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_FLASH_D2, - GPIO2A2_EMMC_D2, - GPIO2A2_SFC_WP_IO2, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_FLASH_D1, - GPIO2A1_EMMC_D1, - GPIO2A1_SFC_SO_IO1, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_FLASH_D0, - GPIO2A0_EMMC_D0, - GPIO2A0_SFC_SI_IO0, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, - GPIO2B7_GPIO = 0, - GPIO2B7_FLASH_CS1, - GPIO2B7_SFC_CLK, - - GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 1 << GPIO2B6_SHIFT, - GPIO2B6_GPIO = 0, - GPIO2B6_EMMC_CLKO, - - GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, - GPIO2B5_GPIO = 0, - GPIO2B5_FLASH_CS0, - - GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, - GPIO2B4_GPIO = 0, - GPIO2B4_FLASH_RDY, - GPIO2B4_EMMC_CMD, - GPIO2B4_SFC_CSN0, - - GPIO2B3_SHIFT = 6, - GPIO2B3_MASK = 1 << GPIO2B3_SHIFT, - GPIO2B3_GPIO = 0, - GPIO2B3_FLASH_RDN, - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, - GPIO2B2_GPIO = 0, - GPIO2B2_FLASH_WRN, - - GPIO2B1_SHIFT = 2, - GPIO2B1_MASK = 1 << GPIO2B1_SHIFT, - GPIO2B1_GPIO = 0, - GPIO2B1_FLASH_CLE, - - GPIO2B0_SHIFT = 0, - GPIO2B0_MASK = 1 << GPIO2B0_SHIFT, - GPIO2B0_GPIO = 0, - GPIO2B0_FLASH_ALE, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2D7_SHIFT = 14, - GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, - GPIO2D7_GPIO = 0, - GPIO2D7_SDIO_D0, - - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_SDIO_CMD, - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, - GPIO2D5_GPIO = 0, - GPIO2D5_SDIO_CLKO, - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, - GPIO2D4_GPIO = 0, - GPIO2D4_I2C1_SCL, - - GPIO2D3_SHIFT = 6, - GPIO2D3_MASK = 1 << GPIO2D3_SHIFT, - GPIO2D3_GPIO = 0, - GPIO2D3_I2C1_SDA, - - GPIO2D2_SHIFT = 4, - GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, - GPIO2D2_GPIO = 0, - GPIO2D2_UART2_SOUT_M0, - GPIO2D2_JTAG_TCK, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_UART2_SIN_M0, - GPIO2D1_JTAG_TMS, - GPIO2D1_DSP_TMS, - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = 3, - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_CTSN, - GPIO2D0_SPI_CLK_M0, - GPIO2D0_DSP_TCK, -}; - -/* GRF_GPIO3A_IOMUX */ -enum { - GPIO3A7_SHIFT = 14, - GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, - GPIO3A7_GPIO = 0, - - GPIO3A6_SHIFT = 12, - GPIO3A6_MASK = 1 << GPIO3A6_SHIFT, - GPIO3A6_GPIO = 0, - GPIO3A6_UART1_SOUT, - - GPIO3A5_SHIFT = 10, - GPIO3A5_MASK = 1 << GPIO3A5_SHIFT, - GPIO3A5_GPIO = 0, - GPIO3A5_UART1_SIN, - - GPIO3A4_SHIFT = 8, - GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, - GPIO3A4_GPIO = 0, - GPIO3A4_UART1_CTSN, - - GPIO3A3_SHIFT = 6, - GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, - GPIO3A3_GPIO = 0, - GPIO3A3_UART1_RTSN, - - GPIO3A2_SHIFT = 4, - GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, - GPIO3A2_GPIO = 0, - GPIO3A2_SDIO_D3, - - GPIO3A1_SHIFT = 2, - GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, - GPIO3A1_GPIO = 0, - GPIO3A1_SDIO_D2, - - GPIO3A0_SHIFT = 0, - GPIO3A0_MASK = 1, - GPIO3A0_GPIO = 0, - GPIO3A0_SDIO_D1, -}; - -/* GRF_GPIO3C_IOMUX */ -enum { - GPIO3C7_SHIFT = 14, - GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, - GPIO3C7_GPIO = 0, - GPIO3C7_CIF_CLKI, - - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, - GPIO3C6_GPIO = 0, - GPIO3C6_CIF_VSYNC, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, - GPIO3C5_GPIO = 0, - GPIO3C5_SDMMC_CMD, - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, - GPIO3C4_GPIO = 0, - GPIO3C4_SDMMC_CLKO, - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, - GPIO3C3_GPIO = 0, - GPIO3C3_SDMMC_D0, - GPIO3C3_UART2_SOUT_M1, - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, - GPIO3C2_GPIO = 0, - GPIO3C2_SDMMC_D1, - GPIO3C2_UART2_SIN_M1, - - GPIOC1_SHIFT = 2, - GPIOC1_MASK = 1 << GPIOC1_SHIFT, - GPIOC1_GPIO = 0, - GPIOC1_SDMMC_D2, - - GPIOC0_SHIFT = 0, - GPIOC0_MASK = 1, - GPIO3C0_GPIO = 0, - GPIO3C0_SDMMC_D3, -}; - -static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id) -{ - switch (uart_id) { - case PERIPH_ID_UART0: - rk_clrsetreg(&grf->gpio3a_iomux, - GPIO3A6_MASK | GPIO3A5_MASK, - GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT | - GPIO3A5_UART1_SIN << GPIO3A5_SHIFT); - break; - case PERIPH_ID_UART1: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK | - GPIO1D0_MASK, - GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT | - GPIO1D2_UART0_SIN << GPIO1D2_SHIFT | - GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT | - GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT); - break; - case PERIPH_ID_UART2: - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D2_MASK | GPIO2D1_MASK, - GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | - GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); - break; - } -} - -static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func) -{ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK | - GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK, - GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT | - GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT | - GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT | - GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT | - GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT | - GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT); - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C5_MASK | GPIO1C4_MASK | - GPIO1C3_MASK | GPIO1C2_MASK, - GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT | - GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT | - GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT | - GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT); - writel(0xffff57f5, &grf->gpio1b_drv); -} - -static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf) -{ - rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK | - GPIO2A1_MASK | GPIO2A0_MASK, - GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT | - GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT | - GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT | - GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT); - rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK, - GPIO2B7_SFC_CLK << GPIO2B7_SHIFT | - GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT); -} - -static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags) -{ - struct rv1108_pinctrl_priv *priv = dev_get_priv(dev); - - switch (func) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - pinctrl_rv1108_uart_config(priv->grf, func); - break; - case PERIPH_ID_GMAC: - pinctrl_rv1108_gmac_config(priv->grf, func); - case PERIPH_ID_SFC: - pinctrl_rv1108_sfc_config(priv->grf); - default: - return -EINVAL; - } - - return 0; -} - -static int rv1108_pinctrl_get_periph_id(struct udevice *dev, - struct udevice *periph) -{ - u32 cell[3]; - int ret; - - ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); - if (ret < 0) - return -EINVAL; - - switch (cell[1]) { - case 11: - return PERIPH_ID_SDCARD; - case 13: - return PERIPH_ID_EMMC; - case 19: - return PERIPH_ID_GMAC; - case 30: - return PERIPH_ID_I2C0; - case 31: - return PERIPH_ID_I2C1; - case 32: - return PERIPH_ID_I2C2; - case 39: - return PERIPH_ID_PWM0; - case 44: - return PERIPH_ID_UART0; - case 45: - return PERIPH_ID_UART1; - case 46: - return PERIPH_ID_UART2; - case 56: - return PERIPH_ID_SFC; - } - - return -ENOENT; -} - -static int rv1108_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) -{ - int func; - - func = rv1108_pinctrl_get_periph_id(dev, periph); - if (func < 0) - return func; - - return rv1108_pinctrl_request(dev, func, 0); -} - -static struct pinctrl_ops rv1108_pinctrl_ops = { - .set_state_simple = rv1108_pinctrl_set_state_simple, - .request = rv1108_pinctrl_request, - .get_periph_id = rv1108_pinctrl_get_periph_id, -}; - -static int rv1108_pinctrl_probe(struct udevice *dev) -{ - struct rv1108_pinctrl_priv *priv = dev_get_priv(dev); - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - - return 0; -} - -static const struct udevice_id rv1108_pinctrl_ids[] = { - {.compatible = "rockchip,rv1108-pinctrl" }, - { } -}; - -U_BOOT_DRIVER(pinctrl_rv1108) = { - .name = "pinctrl_rv1108", - .id = UCLASS_PINCTRL, - .of_match = rv1108_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv), - .ops = &rv1108_pinctrl_ops, - .bind = dm_scan_fdt_dev, - .probe = rv1108_pinctrl_probe, -}; diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index c0d97cca33..22e379681d 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -21,6 +21,15 @@ config I2S I2S. It calls either of the two supported codecs (no use is made of driver model at present). +config I2S_ROCKCHIP + bool "Enable I2S support for Rockchip SoCs" + depends on I2S + help + Rockchip SoCs support an I2S interface for sending audio data to an + audio codec. This option enables support for this, using one of the + available audio codec drivers. This driver does not make use of + DMA, but writes each word directly to the hardware. + config I2S_SAMSUNG bool "Enable I2C support for Samsung SoCs" depends on SOUND diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 1de4346ec7..d0bf51bab6 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_SOUND) += i2s-uclass.o obj-$(CONFIG_SOUND) += sound-uclass.o obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o +obj-$(CONFIG_I2S_ROCKCHIP) += rockchip_i2s.o rockchip_sound.o obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o diff --git a/drivers/sound/rockchip_i2s.c b/drivers/sound/rockchip_i2s.c new file mode 100644 index 0000000000..e5df8ca0d2 --- /dev/null +++ b/drivers/sound/rockchip_i2s.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Copyright 2014 Rockchip Electronics Co., Ltd. + * Taken from dc i2s/rockchip.c + */ + +#define LOG_CATEGORY UCLASS_I2S + +#include <common.h> +#include <dm.h> +#include <i2s.h> +#include <sound.h> +#include <asm/io.h> + +struct rk_i2s_regs { + u32 txcr; /* I2S_TXCR, 0x00 */ + u32 rxcr; /* I2S_RXCR, 0x04 */ + u32 ckr; /* I2S_CKR, 0x08 */ + u32 fifolr; /* I2S_FIFOLR, 0x0C */ + u32 dmacr; /* I2S_DMACR, 0x10 */ + u32 intcr; /* I2S_INTCR, 0x14 */ + u32 intsr; /* I2S_INTSR, 0x18 */ + u32 xfer; /* I2S_XFER, 0x1C */ + u32 clr; /* I2S_CLR, 0x20 */ + u32 txdr; /* I2S_TXDR, 0x24 */ + u32 rxdr; /* I2S_RXDR, 0x28 */ +}; + +enum { + /* I2S_XFER */ + I2S_RX_TRAN_BIT = BIT(1), + I2S_TX_TRAN_BIT = BIT(0), + I2S_TRAN_MASK = 3 << 0, + + /* I2S_TXCKR */ + I2S_MCLK_DIV_SHIFT = 16, + I2S_MCLK_DIV_MASK = (0xff << I2S_MCLK_DIV_SHIFT), + + I2S_RX_SCLK_DIV_SHIFT = 8, + I2S_RX_SCLK_DIV_MASK = 0xff << I2S_RX_SCLK_DIV_SHIFT, + I2S_TX_SCLK_DIV_SHIFT = 0, + I2S_TX_SCLK_DIV_MASK = 0xff << I2S_TX_SCLK_DIV_SHIFT, + + I2S_DATA_WIDTH_SHIFT = 0, + I2S_DATA_WIDTH_MASK = 0x1f << I2S_DATA_WIDTH_SHIFT, +}; + +static int rockchip_i2s_init(struct i2s_uc_priv *priv) +{ + struct rk_i2s_regs *regs = (struct rk_i2s_regs *)priv->base_address; + u32 bps = priv->bitspersample; + u32 lrf = priv->rfs; + u32 chn = priv->channels; + u32 mode = 0; + + clrbits_le32(®s->xfer, I2S_TX_TRAN_BIT); + mode = readl(®s->txcr) & ~0x1f; + switch (priv->bitspersample) { + case 16: + case 24: + mode |= (priv->bitspersample - 1) << I2S_DATA_WIDTH_SHIFT; + break; + default: + log_err("Invalid sample size input %d\n", priv->bitspersample); + return -EINVAL; + } + writel(mode, ®s->txcr); + + mode = readl(®s->ckr) & ~I2S_MCLK_DIV_MASK; + mode |= (lrf / (bps * chn) - 1) << I2S_MCLK_DIV_SHIFT; + + mode &= ~I2S_TX_SCLK_DIV_MASK; + mode |= (priv->bitspersample * priv->channels - 1) << + I2S_TX_SCLK_DIV_SHIFT; + writel(mode, ®s->ckr); + + return 0; +} + +static int i2s_send_data(struct rk_i2s_regs *regs, u32 *data, uint length) +{ + for (int i = 0; i < min(32u, length); i++) + writel(*data++, ®s->txdr); + + length -= min(32u, length); + + /* enable both tx and rx */ + setbits_le32(®s->xfer, I2S_TRAN_MASK); + while (length) { + if ((readl(®s->fifolr) & 0x3f) < 0x20) { + writel(*data++, ®s->txdr); + length--; + } + } + while (readl(®s->fifolr) & 0x3f) + /* wait until FIFO empty */; + clrbits_le32(®s->xfer, I2S_TRAN_MASK); + writel(0, ®s->clr); + + return 0; +} + +static int rockchip_i2s_tx_data(struct udevice *dev, void *data, uint data_size) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + struct rk_i2s_regs *regs = (struct rk_i2s_regs *)priv->base_address; + + return i2s_send_data(regs, data, data_size / sizeof(u32)); +} + +static int rockchip_i2s_probe(struct udevice *dev) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + ulong base; + + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) { + log_debug("Missing i2s base\n"); + return -EINVAL; + } + priv->base_address = base; + priv->id = 1; + priv->audio_pll_clk = 4800000; + priv->samplingrate = 48000; + priv->bitspersample = 16; + priv->channels = 2; + priv->rfs = 256; + priv->bfs = 32; + + return rockchip_i2s_init(priv); +} + +static const struct i2s_ops rockchip_i2s_ops = { + .tx_data = rockchip_i2s_tx_data, +}; + +static const struct udevice_id rockchip_i2s_ids[] = { + { .compatible = "rockchip,rk3288-i2s" }, + { } +}; + +U_BOOT_DRIVER(rockchip_i2s) = { + .name = "rockchip_i2s", + .id = UCLASS_I2S, + .of_match = rockchip_i2s_ids, + .probe = rockchip_i2s_probe, + .ops = &rockchip_i2s_ops, +}; diff --git a/drivers/sound/rockchip_sound.c b/drivers/sound/rockchip_sound.c new file mode 100644 index 0000000000..e7fb9fb164 --- /dev/null +++ b/drivers/sound/rockchip_sound.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google, LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY UCLASS_SOUND + +#include <common.h> +#include <audio_codec.h> +#include <clk.h> +#include <dm.h> +#include <i2s.h> +#include <misc.h> +#include <sound.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> + +static int rockchip_sound_setup(struct udevice *dev) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s); + int ret; + + if (uc_priv->setup_done) + return -EALREADY; + ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id, + i2c_priv->samplingrate, + i2c_priv->samplingrate * i2c_priv->rfs, + i2c_priv->bitspersample, + i2c_priv->channels); + if (ret) + return ret; + uc_priv->setup_done = true; + + return 0; +} + +static int rockchip_sound_play(struct udevice *dev, void *data, uint data_size) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + + return i2s_tx_data(uc_priv->i2s, data, data_size); +} + +static int rockchip_sound_probe(struct udevice *dev) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct ofnode_phandle_args args; + struct udevice *pinctrl; + struct clk clk; + ofnode node; + int ret; + + node = ofnode_find_subnode(dev_ofnode(dev), "cpu"); + if (!ofnode_valid(node)) { + log_debug("Failed to find /cpu subnode\n"); + return -EINVAL; + } + ret = ofnode_parse_phandle_with_args(node, "sound-dai", + "#sound-dai-cells", 0, 0, &args); + if (ret) { + log_debug("Cannot find i2s phandle: %d\n", ret); + return ret; + } + ret = uclass_get_device_by_ofnode(UCLASS_I2S, args.node, &uc_priv->i2s); + if (ret) { + log_debug("Cannot find i2s: %d\n", ret); + return ret; + } + + node = ofnode_find_subnode(dev_ofnode(dev), "codec"); + if (!ofnode_valid(node)) { + log_debug("Failed to find /codec subnode\n"); + return -EINVAL; + } + ret = ofnode_parse_phandle_with_args(node, "sound-dai", + "#sound-dai-cells", 0, 0, &args); + if (ret) { + log_debug("Cannot find codec phandle: %d\n", ret); + return ret; + } + ret = uclass_get_device_by_ofnode(UCLASS_AUDIO_CODEC, args.node, + &uc_priv->codec); + if (ret) { + log_debug("Cannot find audio codec: %d\n", ret); + return ret; + } + ret = clk_get_by_index(uc_priv->i2s, 1, &clk); + if (ret) { + log_debug("Cannot find clock: %d\n", ret); + return ret; + } + ret = clk_set_rate(&clk, 12288000); + if (ret < 0) { + log_debug("Cannot find clock: %d\n", ret); + return ret; + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + ret = pinctrl_request(pinctrl, PERIPH_ID_I2S, 0); + if (ret) { + debug("%s: Cannot select I2C pinctrl\n", __func__); + return ret; + } + + log_debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name, + uc_priv->codec->name, uc_priv->i2s->name); + + return 0; +} + +static const struct sound_ops rockchip_sound_ops = { + .setup = rockchip_sound_setup, + .play = rockchip_sound_play, +}; + +static const struct udevice_id rockchip_sound_ids[] = { + { .compatible = "rockchip,audio-max98090-jerry" }, + { } +}; + +U_BOOT_DRIVER(rockchip_sound) = { + .name = "rockchip_sound", + .id = UCLASS_SOUND, + .of_match = rockchip_sound_ids, + .probe = rockchip_sound_probe, + .ops = &rockchip_sound_ops, +}; diff --git a/include/configs/gru.h b/include/configs/gru.h new file mode 100644 index 0000000000..a0d27b6d51 --- /dev/null +++ b/include/configs/gru.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 9a4da395f9..b977b1faa7 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -49,11 +49,16 @@ "kernel_addr_r=0x02080000\0" \ "ramdisk_addr_r=0x04000000\0" +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + #include <config_distro_bootcmd.h> #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ BOOTENV #endif diff --git a/include/spl_gpio.h b/include/spl_gpio.h new file mode 100644 index 0000000000..e410e62914 --- /dev/null +++ b/include/spl_gpio.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Simple GPIO access from SPL. This only supports a single GPIO space, + * typically the SoC GPIO banks. + * + * Copyright 2018 Google LLC + */ + +#ifndef __SPL_GPIO_H +#define __SPL_GPIO_H + +#include <asm/gpio.h> + +/* + * The functions listed here should be implemented in the SoC GPIO driver. + * They correspond to the normal GPIO API (asm-generic/gpio.h). The GPIO + * number is encoded in an unsigned int by an SoC-specific means. Pull + * values are also SoC-specific. + * + * This API should only be used in TPL/SPL where GPIO access is needed but + * driver model is not available (yet) or adds too much overhead. + * + * The caller must supply the GPIO register base since this information is + * often specific to a particular SoC generation. This allows the GPIO + * code to be fairly generic. + * + * Only a single implementation of each of these functions can be provided. + * + * The 'gpio' value can include both a bank and a GPIO number, if desired. The + * encoding is SoC-specific. + */ + +/** + * spl_gpio_set_pull() - Set the pull up/down state of a GPIO + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @pull: Pull value (SoC-specific) + * @return return 0 if OK, -ve on error + */ +int spl_gpio_set_pull(void *regs, uint gpio, int pull); + +/** + * spl_gpio_output() - Set a GPIO as an output + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @value: 0 to set the output low, 1 to set it high + * @return return 0 if OK, -ve on error + */ +int spl_gpio_output(void *regs, uint gpio, int value); + +/** + * spl_gpio_input() - Set a GPIO as an input + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @return return 0 if OK, -ve on error + */ +int spl_gpio_input(void *regs, uint gpio); + +#endif /* __SPL_GPIO_H */ diff --git a/lib/display_options.c b/lib/display_options.c index 32849821f4..af1802ef99 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -174,7 +174,9 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, x = lb.us[i] = *(volatile uint16_t *)data; else x = lb.uc[i] = *(volatile uint8_t *)data; -#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA +#if defined(CONFIG_SPL_BUILD) + printf(" %x", (uint)x); +#elif defined(CONFIG_SYS_SUPPORT_64BIT_DATA) printf(" %0*llx", width * 2, (long long)x); #else printf(" %0*x", width * 2, x); |