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authorEugene O'Brien <eugene.obrien@advantechamt.com>2008-04-11 10:00:35 -0400
committerStefan Roese <sr@denx.de>2008-04-11 16:27:58 +0200
commit5b2052e5f5fcce5dbd4d2750a29c0e45bce806e7 (patch)
tree9506f054b9ba24b028edcc73826f5f62a6b1d3ad
parent64e541f4c1b413dd84c7e409f5c2bf328db2ac13 (diff)
ppc4xx: Fix power mgt definitions for PPC440
Corrected DCR addresses of PPC440EP power management registers. Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
-rw-r--r--include/ppc440.h9
1 files changed, 1 insertions, 8 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index 642d1ded762..bb39ad63175 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1731,17 +1731,10 @@
#else
#define CNTRL_DCR_BASE 0x0b0
#endif
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
-#else
-#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
-#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
-#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
-#endif
#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */