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authorTom Rini <trini@konsulko.com>2022-01-30 17:12:34 -0500
committerTom Rini <trini@konsulko.com>2022-01-30 17:12:34 -0500
commite267665a7420bddbfd5833573fdfc9d0930ff515 (patch)
treedd92172de357d0843012dcdc5a1a363ad31bffb9
parentc7d042f315d89ab2f0122920829f18a8f8897a05 (diff)
parent50d5c6428fc280c095b0edd1a612b3661b5db77d (diff)
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
a bit delayed, the first batch of the sunxi pull request for this cycle. This is mostly collecting some patches that were lying around for a while, plus some recent fixes. Nothing too exciting at this point, but of course they should be merged nevertheless. There is the much bigger F1C100s SoC support coming up, which I hope to be able to send in the next few days, along with the removal of sunxi's lowlevel_init usage. Compile tested for all 159 sunxi boards, plus briefly tested on BananaPi M1, OrangePi Zero, Pine64 and Pine-H64.
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h6
-rw-r--r--arch/arm/mach-sunxi/Kconfig10
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h616.c4
-rw-r--r--arch/arm/mach-sunxi/pinmux.c32
-rw-r--r--board/sunxi/board.c17
-rw-r--r--board/sunxi/dram_sun4i_auto.c2
-rw-r--r--board/sunxi/dram_sun5i_auto.c2
-rw-r--r--drivers/gpio/sunxi_gpio.c62
-rw-r--r--drivers/i2c/mvtwsi.c1
-rw-r--r--drivers/mmc/sunxi_mmc.c8
-rw-r--r--drivers/spi/spi-sunxi.c3
-rw-r--r--include/axp152.h2
-rw-r--r--include/axp209.h3
-rw-r--r--include/axp221.h3
-rw-r--r--include/axp305.h3
-rw-r--r--include/axp809.h3
-rw-r--r--include/axp818.h3
-rw-r--r--tools/sunxi_egon.c9
18 files changed, 104 insertions, 69 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f3ab1aea0e..106605adf5 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -226,8 +226,10 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
-int sunxi_gpio_set_drv(u32 pin, u32 val);
-int sunxi_gpio_set_pull(u32 pin, u32 val);
+void sunxi_gpio_set_drv(u32 pin, u32 val);
+void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val);
+void sunxi_gpio_set_pull(u32 pin, u32 val);
+void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
int sunxi_name_to_gpio(const char *name);
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 2c18cf02d1..d7f9a03152 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -785,6 +785,16 @@ config AXP_GPIO
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
+config AXP_DISABLE_BOOT_ON_POWERON
+ bool "Disable device boot on power plug-in"
+ depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+ default n
+ ---help---
+ Say Y here to prevent the device from booting up because of a plug-in
+ event. When set, the device will boot into the SPL briefly to
+ determine why it was powered on, and if it was determined because of
+ a plug-in event instead of a button press event it will shut back off.
+
config VIDEO_SUNXI
bool "Enable graphical uboot console on HDMI, LCD or VGA"
depends on !MACH_SUN8I_A83T
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index acdfb3ceef..83e8abc2f8 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para)
}
}
- setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
}
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);
@@ -720,7 +720,7 @@ static bool mctl_phy_init(struct dram_para *para)
writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
- if (IS_ENABLED(DRAM_ODT_EN))
+ if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
mctl_phy_configure_odt();
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa);
diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
index 642483f06c..c95fcee9f6 100644
--- a/arch/arm/mach-sunxi/pinmux.c
+++ b/arch/arm/mach-sunxi/pinmux.c
@@ -14,7 +14,7 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
u32 index = GPIO_CFG_INDEX(bank_offset);
u32 offset = GPIO_CFG_OFFSET(bank_offset);
- clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
+ clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
}
void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
@@ -31,7 +31,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
u32 offset = GPIO_CFG_OFFSET(bank_offset);
u32 cfg;
- cfg = readl(&pio->cfg[0] + index);
+ cfg = readl(&pio->cfg[index]);
cfg >>= offset;
return cfg & 0xf;
@@ -45,26 +45,34 @@ int sunxi_gpio_get_cfgpin(u32 pin)
return sunxi_gpio_get_cfgbank(pio, pin);
}
-int sunxi_gpio_set_drv(u32 pin, u32 val)
+void sunxi_gpio_set_drv(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_DRV_INDEX(pin);
- u32 offset = GPIO_DRV_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
- clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
+ sunxi_gpio_set_drv_bank(pio, pin, val);
+}
+
+void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
+{
+ u32 index = GPIO_DRV_INDEX(bank_offset);
+ u32 offset = GPIO_DRV_OFFSET(bank_offset);
- return 0;
+ clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
}
-int sunxi_gpio_set_pull(u32 pin, u32 val)
+void sunxi_gpio_set_pull(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_PULL_INDEX(pin);
- u32 offset = GPIO_PULL_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
- clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
+ sunxi_gpio_set_pull_bank(pio, pin, val);
+}
+
+void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+{
+ u32 index = GPIO_PULL_INDEX(bank_offset);
+ u32 offset = GPIO_PULL_OFFSET(bank_offset);
- return 0;
+ clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset);
}
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2790a0f9e8..91463009b0 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -28,6 +28,7 @@
#include <asm/arch/dram.h>
#include <asm/arch/mmc.h>
#include <asm/arch/prcm.h>
+#include <asm/arch/pmic_bus.h>
#include <asm/arch/spl.h>
#include <asm/global_data.h>
#include <linux/delay.h>
@@ -602,6 +603,16 @@ void sunxi_board_init(void)
defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
power_failed = axp_init();
+ if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
+ u8 boot_reason;
+
+ pmic_bus_read(AXP_POWER_STATUS, &boot_reason);
+ if (boot_reason & AXP_POWER_STATUS_ALDO_IN) {
+ printf("Power on by plug-in, shutting down.\n");
+ pmic_bus_write(0x32, BIT(7));
+ }
+ }
+
#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
defined CONFIG_AXP818_POWER
power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
@@ -912,10 +923,12 @@ int ft_board_setup(void *blob, struct bd_info *bd)
int __maybe_unused r;
/*
- * Call setup_environment again in case the boot fdt has
- * ethernet aliases the u-boot copy does not have.
+ * Call setup_environment and fdt_fixup_ethernet again
+ * in case the boot fdt has ethernet aliases the u-boot
+ * copy does not have.
*/
setup_environment(blob);
+ fdt_fixup_ethernet(blob);
bluetooth_dt_fixup(blob);
diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c
index e8bbee4ee5..547d1c0cb4 100644
--- a/board/sunxi/dram_sun4i_auto.c
+++ b/board/sunxi/dram_sun4i_auto.c
@@ -4,7 +4,7 @@
static struct dram_para dram_para = {
.clock = CONFIG_DRAM_CLK,
- .type = 3,
+ .type = DRAM_MEMORY_TYPE_DDR3,
.rank_num = 1,
.density = 0,
.io_width = 0,
diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c
index a5f4f8b743..517506ccc4 100644
--- a/board/sunxi/dram_sun5i_auto.c
+++ b/board/sunxi/dram_sun5i_auto.c
@@ -7,7 +7,7 @@
static struct dram_para dram_para = {
.clock = CONFIG_DRAM_CLK,
.mbus_clock = CONFIG_DRAM_MBUS_CLK,
- .type = 3,
+ .type = DRAM_MEMORY_TYPE_DDR3,
.rank_num = 1,
.density = 0,
.io_width = 0,
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index caefb1447c..6c3c10862c 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -139,27 +139,6 @@ int sunxi_name_to_gpio(const char *name)
return ret ? ret : gpio;
}
-static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
-{
- struct sunxi_gpio_plat *plat = dev_get_plat(dev);
-
- sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
-
- return 0;
-}
-
-static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
- int value)
-{
- struct sunxi_gpio_plat *plat = dev_get_plat(dev);
- u32 num = GPIO_NUM(offset);
-
- sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
- clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
-
- return 0;
-}
-
static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct sunxi_gpio_plat *plat = dev_get_plat(dev);
@@ -172,16 +151,6 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
return dat & 0x1;
}
-static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
- int value)
-{
- struct sunxi_gpio_plat *plat = dev_get_plat(dev);
- u32 num = GPIO_NUM(offset);
-
- clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
- return 0;
-}
-
static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct sunxi_gpio_plat *plat = dev_get_plat(dev);
@@ -205,18 +174,41 @@ static int sunxi_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
if (ret)
return ret;
desc->offset = args->args[1];
- desc->flags = args->args[2] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+ desc->flags = gpio_flags_xlate(args->args[2]);
+
+ return 0;
+}
+
+static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset,
+ ulong flags)
+{
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
+
+ if (flags & GPIOD_IS_OUT) {
+ u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
+ u32 num = GPIO_NUM(offset);
+
+ clrsetbits_le32(&plat->regs->dat, 1 << num, value << num);
+ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
+ } else if (flags & GPIOD_IS_IN) {
+ u32 pull = 0;
+
+ if (flags & GPIOD_PULL_UP)
+ pull = 1;
+ else if (flags & GPIOD_PULL_DOWN)
+ pull = 2;
+ sunxi_gpio_set_pull_bank(plat->regs, offset, pull);
+ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
+ }
return 0;
}
static const struct dm_gpio_ops gpio_sunxi_ops = {
- .direction_input = sunxi_gpio_direction_input,
- .direction_output = sunxi_gpio_direction_output,
.get_value = sunxi_gpio_get_value,
- .set_value = sunxi_gpio_set_value,
.get_function = sunxi_gpio_get_function,
.xlate = sunxi_gpio_xlate,
+ .set_flags = sunxi_gpio_set_flags,
};
/**
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index bad4b1484f..f48a4f25aa 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -900,6 +900,7 @@ static const struct dm_i2c_ops mvtwsi_i2c_ops = {
static const struct udevice_id mvtwsi_i2c_ids[] = {
{ .compatible = "marvell,mv64xxx-i2c", },
{ .compatible = "marvell,mv78230-i2c", },
+ { .compatible = "allwinner,sun4i-a10-i2c", },
{ .compatible = "allwinner,sun6i-a31-i2c", },
{ /* sentinel */ }
};
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4bf8a9b92c..1bb7b6d0e9 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -702,12 +702,8 @@ static int sunxi_mmc_probe(struct udevice *dev)
return ret;
/* This GPIO is optional */
- if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
- GPIOD_IS_IN)) {
- int cd_pin = gpio_get_number(&priv->cd_gpio);
-
- sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
- }
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN | GPIOD_PULL_UP);
upriv->mmc = &plat->mmc;
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index bc2f544e86..d62355ec6f 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -249,7 +249,8 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
if (pin < 0)
break;
- if (IS_ENABLED(CONFIG_MACH_SUN50I))
+ if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
+ IS_ENABLED(CONFIG_SUN50I_GEN_H6))
sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
else
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
diff --git a/include/axp152.h b/include/axp152.h
index 10d845fec4..bac6526a36 100644
--- a/include/axp152.h
+++ b/include/axp152.h
@@ -16,6 +16,8 @@ enum axp152_reg {
/* For axp_gpio.c */
#ifdef CONFIG_AXP152_POWER
+#define AXP_POWER_STATUS 0x00
+#define AXP_POWER_STATUS_ALDO_IN BIT(0)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x91
#define AXP_GPIO2_CTRL 0x92
diff --git a/include/axp209.h b/include/axp209.h
index 30399a8d62..414f88a32c 100644
--- a/include/axp209.h
+++ b/include/axp209.h
@@ -76,7 +76,8 @@ enum axp209_reg {
/* For axp_gpio.c */
#ifdef CONFIG_AXP209_POWER
#define AXP_POWER_STATUS 0x00
-#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
+#define AXP_POWER_STATUS_ALDO_IN BIT(0)
+#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO2_CTRL 0x93
diff --git a/include/axp221.h b/include/axp221.h
index a02e9b4f64..8dfcc5b5a2 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -52,7 +52,8 @@
/* For axp_gpio.c */
#ifdef CONFIG_AXP221_POWER
#define AXP_POWER_STATUS 0x00
-#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_POWER_STATUS_ALDO_IN BIT(0)
+#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f
diff --git a/include/axp305.h b/include/axp305.h
index 225c5040a3..0a42bc6804 100644
--- a/include/axp305.h
+++ b/include/axp305.h
@@ -15,3 +15,6 @@ enum axp305_reg {
#define AXP305_OUTPUT_CTRL1_DCDCD_EN (1 << 3)
#define AXP305_POWEROFF (1 << 7)
+
+#define AXP_POWER_STATUS 0x00
+#define AXP_POWER_STATUS_ALDO_IN BIT(0)
diff --git a/include/axp809.h b/include/axp809.h
index 430dbef622..8082e402e2 100644
--- a/include/axp809.h
+++ b/include/axp809.h
@@ -46,7 +46,8 @@
/* For axp_gpio.c */
#ifdef CONFIG_AXP809_POWER
#define AXP_POWER_STATUS 0x00
-#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_POWER_STATUS_ALDO_IN BIT(0)
+#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f
diff --git a/include/axp818.h b/include/axp818.h
index 8bac6b67ca..8ac517a2bf 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -60,7 +60,8 @@
/* For axp_gpio.c */
#ifdef CONFIG_AXP818_POWER
#define AXP_POWER_STATUS 0x00
-#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_POWER_STATUS_ALDO_IN BIT(0)
+#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
index a5299eb6a1..d1398c07fb 100644
--- a/tools/sunxi_egon.c
+++ b/tools/sunxi_egon.c
@@ -10,9 +10,10 @@
/*
* NAND requires 8K padding. SD/eMMC gets away with 512 bytes,
- * but let's use the larger padding to cover both.
+ * but let's use the larger padding by default to cover both.
*/
#define PAD_SIZE 8192
+#define PAD_SIZE_MIN 512
static int egon_check_params(struct image_tool_params *params)
{
@@ -114,10 +115,12 @@ static int egon_check_image_type(uint8_t type)
static int egon_vrec_header(struct image_tool_params *params,
struct image_type_params *tparams)
{
+ int pad_size = ALIGN(params->bl_len ?: PAD_SIZE, PAD_SIZE_MIN);
+
tparams->hdr = calloc(sizeof(struct boot_file_head), 1);
- /* Return padding to 8K blocks. */
- return ALIGN(params->file_size, PAD_SIZE) - params->file_size;
+ /* Return padding to complete blocks. */
+ return ALIGN(params->file_size, pad_size) - params->file_size;
}
U_BOOT_IMAGE_TYPE(