MLK-23574-49 mx7ulp_val: Add 10x10 and 14x14 validation board support

Porting the iMX7ULP 10x10 validation board and 14x14 validation board codes
from v2019.04 u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ec3686f915d0abcc3b1e8f06f288ebf4b249366a)
(cherry picked from commit fd016db05902e9dfe30bac2ca808fe29369e2fa9)
(cherry picked from commit f0ae5a8270206fc25b876e8279fca118ace0940e)

13 files changed, 1325 insertions, 0 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 545dd9dfa0..cac053df3b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -894,6 +894,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 	imx7d-smegw01.dtb
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
+	imx7ulp-10x10-val.dtb \
+	imx7ulp-14x14-val.dtb \
 	imx7ulp-evk.dtb \
 	imx7ulp-evk-emmc.dtb \
 	imx7ulp-evk-qspi.dtb
diff --git a/arch/arm/dts/imx7ulp-10x10-val.dts b/arch/arm/dts/imx7ulp-10x10-val.dts
new file mode 100644
index 0000000000..47a4b56c04
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-10x10-val.dts
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP 10x10 val";
+	compatible = "fsl,imx7ulp-10x10-val", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x40A60000,115200";
+		stdout-path = &lpuart6;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&iomuxc1 {
+	pinctrl-names = "default";
+
+	imx7ulp-10x10-val {
+		pinctrl_lpuart6: lpuart6grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTE11__LPUART6_RX	0x400
+				IMX7ULP_PAD_PTE10__LPUART6_TX	0x400
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTE3__SDHC1_CMD	0x843
+				IMX7ULP_PAD_PTE2__SDHC1_CLK	0x843
+				IMX7ULP_PAD_PTE4__SDHC1_D3	0x843
+				IMX7ULP_PAD_PTE5__SDHC1_D2	0x843
+				IMX7ULP_PAD_PTE0__SDHC1_D1	0x843
+				IMX7ULP_PAD_PTE1__SDHC1_D0	0x843
+			>;
+		};
+
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				IMX7ULP_PAD_PTB14__QSPIA_SS1_B   0x43 /* SS1 */
+				IMX7ULP_PAD_PTB8__QSPIA_SS0_B   0x43 /* SS0 */
+				IMX7ULP_PAD_PTB15__QSPIA_SCLK   0x43 /* SCLK */
+				IMX7ULP_PAD_PTB16__QSPIA_DATA3  0x43 /* D3 */
+				IMX7ULP_PAD_PTB17__QSPIA_DATA2  0x43 /* D2 */
+				IMX7ULP_PAD_PTB18__QSPIA_DATA1  0x43 /* D1 */
+				IMX7ULP_PAD_PTB19__QSPIA_DATA0  0x43 /* D0 */
+				IMX7ULP_PAD_PTB5__PTB5 0x20003
+			>;
+		};
+	};
+};
+
+&lpuart6 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart6>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	non-removable;
+	status = "okay";
+};
+
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+
+	flash0: n25q512ax3@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q512ax3", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+	};
+};
diff --git a/arch/arm/dts/imx7ulp-14x14-val.dts b/arch/arm/dts/imx7ulp-14x14-val.dts
new file mode 100644
index 0000000000..0b392cf71c
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-14x14-val.dts
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP 14x14 val";
+	compatible = "fsl,imx7ulp-14x14-val", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&iomuxc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7ulp-14x14-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				IMX7ULP_PAD_PTC10__PTC10	0x30100
+				IMX7ULP_PAD_PTC1__PTC1		0x20100
+			>;
+		};
+
+		pinctrl_lpuart4: lpuart4grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTC3__LPUART4_RX	0x400
+				IMX7ULP_PAD_PTC2__LPUART4_TX	0x400
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTE3__SDHC1_CMD	0x843
+				IMX7ULP_PAD_PTE2__SDHC1_CLK	0x843
+				IMX7ULP_PAD_PTE4__SDHC1_D3	0x843
+				IMX7ULP_PAD_PTE5__SDHC1_D2	0x843
+				IMX7ULP_PAD_PTE0__SDHC1_D1	0x843
+				IMX7ULP_PAD_PTE1__SDHC1_D0	0x843
+			>;
+		};
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				IMX7ULP_PAD_PTB8__QSPIA_SS0_B   0x43 /* SS0 */
+				IMX7ULP_PAD_PTB15__QSPIA_SCLK   0x43 /* SCLK */
+				IMX7ULP_PAD_PTB9__QSPIA_DQS     0x43 /* DQS */
+				IMX7ULP_PAD_PTB16__QSPIA_DATA3  0x43 /* D3 */
+				IMX7ULP_PAD_PTB17__QSPIA_DATA2  0x43 /* D2 */
+				IMX7ULP_PAD_PTB18__QSPIA_DATA1  0x43 /* D1 */
+				IMX7ULP_PAD_PTB19__QSPIA_DATA0  0x43 /* D0 */
+				IMX7ULP_PAD_PTB12__PTB12 0x20003
+			>;
+		};
+	};
+};
+
+&lpuart4 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	non-removable;
+	status = "okay";
+};
+
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,mt35xu512aba", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 6f6499a7fa..d0ee60e3ba 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -42,6 +42,16 @@ config TARGET_MX7ULP_COM
 	select SPL_SERIAL_SUPPORT if SPL
 	select SUPPORT_SPL
 
+config TARGET_MX7ULP_10X10_VAL
+	bool "Support mx7ulp 10x10 validation board"
+	select SYS_ARCH_TIMER
+	select MX7ULP
+
+config TARGET_MX7ULP_14X14_VAL
+	bool "Support mx7ulp 14x14 validation board"
+	select SYS_ARCH_TIMER
+	select MX7ULP
+
 config TARGET_MX7ULP_EVK
 	bool "Support mx7ulp EVK board"
 	select MX7ULP
@@ -52,6 +62,7 @@ config TARGET_MX7ULP_EVK
 endchoice
 
 source "board/ea/mx7ulp_com/Kconfig"
+source "board/freescale/mx7ulp_val/Kconfig"
 source "board/freescale/mx7ulp_evk/Kconfig"
 
 endif
diff --git a/board/freescale/mx7ulp_val/Kconfig b/board/freescale/mx7ulp_val/Kconfig
new file mode 100644
index 0000000000..b68cb6f259
--- /dev/null
+++ b/board/freescale/mx7ulp_val/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_10X10_VAL || TARGET_MX7ULP_14X14_VAL
+
+config SYS_BOARD
+	default "mx7ulp_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_val"
+
+endif
diff --git a/board/freescale/mx7ulp_val/Makefile b/board/freescale/mx7ulp_val/Makefile
new file mode 100644
index 0000000000..ce82e631c8
--- /dev/null
+++ b/board/freescale/mx7ulp_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_val.o
diff --git a/board/freescale/mx7ulp_val/imximage.cfg b/board/freescale/mx7ulp_val/imximage.cfg
new file mode 100644
index 0000000000..d0cd033aa4
--- /dev/null
+++ b/board/freescale/mx7ulp_val/imximage.cfg
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_val/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00e0 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000000
+DATA 4   0x403E0514 0x00000001
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808019
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00e0 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x39373939
+DATA 4   0x40AB0850 0x2F313D36
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x424642F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DA
+DATA 4   0x40AB0018 0x00211718
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000004F
+DATA 4   0x40AB0000 0x84190000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x83018030
+DATA 4   0x40AB001C 0x01038030
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310003
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_val/imximage_lpddr2.cfg b/board/freescale/mx7ulp_val/imximage_lpddr2.cfg
new file mode 100644
index 0000000000..7393ff363e
--- /dev/null
+++ b/board/freescale/mx7ulp_val/imximage_lpddr2.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_val/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00e0 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000000
+DATA 4   0x403E0514 0x00000001
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808019
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00e0 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x0000018C
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x40404040
+DATA 4   0x40AB0850 0x40404040
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x292C42F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB0018 0x00211708
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3110000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x04028038
+DATA 4   0x40AB001C 0x82018030
+DATA 4   0x40AB001C 0x82018038
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x01038038
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB0404 0x00011006
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_val/mx7ulp_val.c b/board/freescale/mx7ulp_val/mx7ulp_val.c
new file mode 100644
index 0000000000..d1e03a2018
--- /dev/null
+++ b/board/freescale/mx7ulp_val/mx7ulp_val.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+
+#define GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE)
+
+#define OTG_ID_GPIO_PAD_CTRL	(PAD_CTL_IBE_ENABLE)
+#define OTG_PWR_GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE)
+
+#define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+
+#define QSPI_PAD_CTRL0	(PAD_CTL_PUS_UP | PAD_CTL_DSE \
+	| PAD_CTL_OBE_ENABLE)
+
+
+int dram_init(void)
+{
+    gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 validation, depends on rework*/
+static iomux_cfg_t const lpuart6_pads[] = {
+    MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+    MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#else
+static iomux_cfg_t const lpuart4_pads[] = {
+    MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+    MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+static void setup_iomux_uart(void)
+{
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+	mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart6_pads));
+#else
+    mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads));
+#endif
+}
+
+#ifdef CONFIG_USB_EHCI_MX7
+
+static iomux_cfg_t const usb_otg1_pads[] = {
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+	MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL),  /* gpio for otgid */
+	MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL),  /* gpio for power en */
+#else
+	/*Need rework for ID and PWR_EN pins on 14x14 ARM2*/
+	MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL),  /* gpio for otgid */
+	MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL),  /* gpio for power en */
+#endif
+};
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+#define OTG0_ID_GPIO	IMX_GPIO_NR(3, 0)
+#define OTG0_PWR_EN		IMX_GPIO_NR(3, 1)
+#else
+#define OTG0_ID_GPIO	IMX_GPIO_NR(3, 18)
+#define OTG0_PWR_EN		IMX_GPIO_NR(1, 31)
+#endif
+static void setup_usb(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads,
+						 ARRAY_SIZE(usb_otg1_pads));
+
+	gpio_request(OTG0_ID_GPIO, "otg_id");
+	gpio_direction_input(OTG0_ID_GPIO);
+}
+
+/*Needs to override the ehci power if controlled by GPIO */
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		if (on)
+			gpio_direction_output(OTG0_PWR_EN, 1);
+		else
+			gpio_direction_output(OTG0_PWR_EN, 0);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	int ret = 0;
+
+	if (port == 0) {
+		ret = gpio_get_value(OTG0_ID_GPIO);
+
+		if (ret)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_HOST;
+}
+
+#endif
+
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define QSPI_RST_GPIO	IMX_GPIO_NR(2, 5)
+#else
+/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB9__QSPIA_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define QSPI_RST_GPIO	IMX_GPIO_NR(2, 12)
+
+#endif
+int board_qspi_init(void)
+{
+	u32 val;
+	mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+	/* enable clock */
+	val = readl(PCC1_RBASE + 0x94);
+
+	if (!(val & 0x20000000)) {
+		writel(0x03000003, (PCC1_RBASE + 0x94));
+		writel(0x43000003, (PCC1_RBASE + 0x94));
+	}
+
+	/* Enable QSPI as a wakeup source on B0 */
+	if (soc_rev() >= CHIP_REV_2_0)
+		setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL);
+
+	gpio_request(QSPI_RST_GPIO, "qspi_reset");
+	gpio_direction_output(QSPI_RST_GPIO, 0);
+	mdelay(10);
+	gpio_direction_output(QSPI_RST_GPIO, 1);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_USB_EHCI_MX7
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+    return 0;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+	printf("Board: i.MX7ULP 10x10 Validation board\n");
+#else
+	printf("Board: i.MX7ULP 14x14 Validation board\n");
+#endif
+	return 0;
+}
diff --git a/board/freescale/mx7ulp_val/plugin.S b/board/freescale/mx7ulp_val/plugin.S
new file mode 100644
index 0000000000..554ee8fe82
--- /dev/null
+++ b/board/freescale/mx7ulp_val/plugin.S
@@ -0,0 +1,352 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.macro imx7ulp_ddr_freq_decrease
+	ldr r2, =0x403f0000
+	ldr r3, =0x00000000
+	str r3, [r2, #0xe0]
+
+	ldr r2, =0x403e0000
+	ldr r3, =0x01000020
+	str r3, [r2, #0x40]
+	ldr r3, =0x01000000
+	str r3, [r2, #0x500]
+
+	ldr r3, =0x80808080
+	str r3, [r2, #0x50c]
+	ldr r3, =0x00160002
+	str r3, [r2, #0x508]
+	ldr r3, =0x00000000
+	str r3, [r2, #0x510]
+	ldr r3, =0x00000001
+	str r3, [r2, #0x514]
+	ldr r3, =0x00000001
+	str r3, [r2, #0x500]
+
+	ldr r3, =0x01000000
+wait1:
+	ldr r4, [r2, #0x500]
+	and r4, r3
+	cmp r4, r3
+	bne wait1
+
+	ldr r3, =0x80808019
+	str r3, [r2, #0x50c]
+
+	ldr r3, =0x00000040
+wait2:
+	ldr r4, [r2, #0x50c]
+	and r4, r3
+	cmp r4, r3
+	bne wait2
+
+	ldr r3, =0x00000001
+	str r3, [r2, #0x30]
+	ldr r3, =0x11000020
+	str r3, [r2, #0x40]
+
+	ldr r2, =0x403f0000
+	ldr r3, =0x42000000
+	str r3, [r2, #0xe0]
+
+.endm
+
+.macro imx7ulp_arm2_lpddr3_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x39373939
+	str r1, [r0, #0x848]
+	ldr r1, =0x2F313D36
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x424642F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DA
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211718
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x40]
+	ldr r1, =0x84190000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1310003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+.macro imx7ulp_arm2_lpddr2_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x40404040
+	str r1, [r0, #0x848]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x292C42F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211708
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000003F
+	str r1, [r0, #0x40]
+	ldr r1, =0xC3110000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x00008018
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+
+.macro imx7ulp_clock_gating
+.endm
+
+.macro imx7ulp_qos_setting
+.endm
+
+.macro imx7ulp_ddr_setting
+#if defined (CONFIG_TARGET_MX7ULP_10X10_VAL)
+	imx7ulp_arm2_lpddr2_setting
+#else
+	imx7ulp_arm2_lpddr3_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7ulp_plugin.S>
diff --git a/configs/mx7ulp_10x10_val_defconfig b/configs/mx7ulp_10x10_val_defconfig
new file mode 100644
index 0000000000..f434e220a1
--- /dev/null
+++ b/configs/mx7ulp_10x10_val_defconfig
@@ -0,0 +1,82 @@
+CONFIG_IMX_CONFIG="board/freescale/mx7ulp_val/imximage_lpddr2.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x9E000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7ULP_10X10_VAL=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-10x10-val"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-10x10-val.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
diff --git a/configs/mx7ulp_14x14_val_defconfig b/configs/mx7ulp_14x14_val_defconfig
new file mode 100644
index 0000000000..a96e4a3ab7
--- /dev/null
+++ b/configs/mx7ulp_14x14_val_defconfig
@@ -0,0 +1,82 @@
+CONFIG_IMX_CONFIG="board/freescale/mx7ulp_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x7E000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7ULP_14X14_VAL=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-14x14-val"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-14x14-val.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
diff --git a/include/configs/mx7ulp_val.h b/include/configs/mx7ulp_val.h
new file mode 100644
index 0000000000..33b88cee10
--- /dev/null
+++ b/include/configs/mx7ulp_val.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Configuration settings for the Freescale i.MX7ULP Validation board.
+ */
+
+#ifndef __MX7ULP_VAL_CONFIG_H
+#define __MX7ULP_VAL_CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_SYS_BOOTM_LEN		0x1000000
+
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR		 WDG1_RBASE
+
+#define CONFIG_SERIAL_TAG
+
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
+
+/* UART */
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+#define LPUART_BASE     LPUART6_RBASE
+#else
+#define LPUART_BASE     LPUART4_RBASE
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		256
+
+/* Physical Memory Map */
+
+#define PHYS_SDRAM			0x60000000ul
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+#define PHYS_SDRAM_SIZE			    SZ_1G   /*LPDDR2 1G*/
+#else
+#define PHYS_SDRAM_SIZE			    SZ_512M
+#endif
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT  \
+	"initrd_addr=0x66800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"sd_dev=1\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttyLP0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x63000000\0" \
+	"boot_fdt=try\0" \
+	"earlycon=lpuart32,0x402D0000\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	SZ_256K
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#endif	/* __CONFIG_H */