CHROMIUM: refactor GPIO interface

BUG=chromium-os:17424
TEST=boot on Seaboard

Change-Id: I9b1f42801eedfba5e7f4e85a5b3ac1e1c106b6bf
Reviewed-on: http://gerrit.chromium.org/gerrit/3998
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>

8 files changed, 160 insertions, 177 deletions

diff --git a/board/nvidia/chromeos/Makefile b/board/nvidia/chromeos/Makefile
index 29da6fd817..daf13f3f5c 100644
--- a/board/nvidia/chromeos/Makefile
+++ b/board/nvidia/chromeos/Makefile
@@ -3,32 +3,6 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# * Redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer.
-# * Redistributions in binary form must reproduce the above
-# copyright notice, this list of conditions and the following disclaimer
-# in the documentation and/or other materials provided with the
-# distribution.
-# * Neither the name of Google Inc. nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
 # Alternatively, this software may be distributed under the terms of the
 # GNU General Public License ("GPL") version 2 as published by the Free
 # Software Foundation.
@@ -38,7 +12,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libchromeos_hardware_interface.a
 
-COBJS-$(CONFIG_CHROMEOS) += gpio.o
+COBJS-$(CONFIG_CHROMEOS) += cros_gpio.o
 COBJS-$(CONFIG_CHROMEOS) += power_management.o
 
 COBJS-$(CONFIG_CHROMEOS_ONESTOP) += onestop_board_specific.o
diff --git a/board/nvidia/chromeos/cros_gpio.c b/board/nvidia/chromeos/cros_gpio.c
new file mode 100644
index 0000000000..f158c5602b
--- /dev/null
+++ b/board/nvidia/chromeos/cros_gpio.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+/* Implementation of per-board GPIO accessor functions */
+
+#include <common.h>
+#include <fdt_decode.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/tegra2.h>
+#include <chromeos/common.h>
+#include <chromeos/cros_gpio.h>
+
+#define PREFIX "cros_gpio: "
+
+int cros_gpio_fetch(enum cros_gpio_index index, const void *fdt,
+		cros_gpio_t *gpio)
+{
+	const char const *port[3] = {
+		"gpio_port_write_protect_switch",
+		"gpio_port_recovery_switch",
+		"gpio_port_developer_switch"
+	};
+	const int const default_port[3] = {
+		GPIO_PH3,
+		GPIO_PH0,
+		GPIO_PV0
+	};
+	const char const *polarity[3] = {
+		"polarity_write_protect_switch",
+		"polarity_recovery_switch",
+		"polarity_developer_switch",
+	};
+	int p;
+
+	if (index < 0 || index >= CROS_GPIO_MAX_GPIO) {
+		VBDEBUG(PREFIX "index out of range: %d\n", index);
+		return -1;
+	}
+
+	gpio->index = index;
+
+	gpio->port = fdt_decode_get_config_int(fdt,
+			port[index], default_port[index]);
+
+	gpio_direction_input(gpio->port);
+
+	gpio->polarity = fdt_decode_get_config_int(fdt,
+			polarity[index], CROS_GPIO_ACTIVE_HIGH);
+
+	p = (gpio->polarity == CROS_GPIO_ACTIVE_HIGH) ? 0 : 1;
+	gpio->value = p ^ gpio_get_value(gpio->port);
+
+	return 0;
+}
+
+int cros_gpio_dump(cros_gpio_t *gpio)
+{
+	const char const *name[3] = {
+		"wpsw", "recsw", "devsw"
+	};
+	int index = gpio->index;
+
+	if (index < 0 || index >= CROS_GPIO_MAX_GPIO) {
+		VBDEBUG(PREFIX "index out of range: %d\n", index);
+		return -1;
+	}
+
+	VBDEBUG(PREFIX "%-6s: port=%3d, polarity=%d, value=%d\n",
+			name[gpio->index],
+			gpio->port, gpio->polarity, gpio->value);
+	return 0;
+}
diff --git a/board/nvidia/chromeos/gpio.c b/board/nvidia/chromeos/gpio.c
deleted file mode 100644
index 44d6b3840e..0000000000
--- a/board/nvidia/chromeos/gpio.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-/* Implementation of per-board GPIO accessor functions */
-
-#include <common.h>
-#include <fdt_decode.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/tegra2.h>
-#include <chromeos/common.h>
-#include <chromeos/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct {
-	int wpsw, recsw, devsw;
-} gpio_port;
-
-static void init_gpio_port(void)
-{
-	gpio_port.wpsw = fdt_decode_get_config_int(gd->blob,
-			"gpio_port_write_protect_switch", GPIO_PH3);
-	gpio_port.recsw = fdt_decode_get_config_int(gd->blob,
-			"gpio_port_recovery_switch", GPIO_PH0);
-	gpio_port.devsw = fdt_decode_get_config_int(gd->blob,
-			"gpio_port_developer_switch", GPIO_PV0);
-}
-
-static int read_gpio(enum polarity polarity, int gpio)
-{
-	int pol = (polarity == GPIO_ACTIVE_HIGH) ? 0 : 1;
-	gpio_direction_input(gpio);
-	return pol ^ gpio_get_value(gpio);
-}
-
-int is_firmware_write_protect_gpio_asserted(enum polarity polarity)
-{
-	if (!gpio_port.wpsw)
-		init_gpio_port();
-	return read_gpio(polarity, GPIO_PH3);
-}
-
-int is_recovery_mode_gpio_asserted(enum polarity polarity)
-{
-	if (!gpio_port.wpsw)
-		init_gpio_port();
-	return read_gpio(polarity, GPIO_PH0);
-}
-
-int is_developer_mode_gpio_asserted(enum polarity polarity)
-{
-	if (!gpio_port.wpsw)
-		init_gpio_port();
-	return read_gpio(polarity, GPIO_PV0);
-}
diff --git a/common/cmd_cros_onestop_firmware.c b/common/cmd_cros_onestop_firmware.c
index 6566c265c2..d484860427 100644
--- a/common/cmd_cros_onestop_firmware.c
+++ b/common/cmd_cros_onestop_firmware.c
@@ -18,7 +18,7 @@
 #include <chromeos/fdt_decode.h>
 #include <chromeos/firmware_storage.h>
 #include <chromeos/gbb_bmpblk.h>
-#include <chromeos/gpio.h>
+#include <chromeos/cros_gpio.h>
 #include <chromeos/load_kernel_helper.h>
 #include <chromeos/onestop.h>
 #include <chromeos/os_storage.h>
@@ -123,38 +123,21 @@ static uint32_t init_internal_state_bottom_half(firmware_storage_t *file,
 		crossystem_data_t *cdata, int *dev_mode, VbNvContext *nvcxt)
 {
 	char frid[ID_LEN];
-	int write_protect_sw, recovery_sw, developer_sw;
-	int polarity_write_protect_sw, polarity_recovery_sw,
-	    polarity_developer_sw;
+	cros_gpio_t wpsw, recsw, devsw;
 	uint32_t reason = VBNV_RECOVERY_NOT_REQUESTED;
 
-	/* load gpio polarity */
-	polarity_write_protect_sw = fdt_decode_get_config_int(fdt,
-			"polarity_write_protect_switch", GPIO_ACTIVE_HIGH);
-	polarity_recovery_sw = fdt_decode_get_config_int(fdt,
-			"polarity_recovery_switch", GPIO_ACTIVE_HIGH);
-	polarity_developer_sw = fdt_decode_get_config_int(fdt,
-			"polarity_developer_switch", GPIO_ACTIVE_HIGH);
-
-	VBDEBUG(PREFIX "polarity:\n");
-	VBDEBUG(PREFIX "- wpsw:  %d\n", polarity_write_protect_sw);
-	VBDEBUG(PREFIX "- recsw: %d\n", polarity_recovery_sw);
-	VBDEBUG(PREFIX "- devsw: %d\n", polarity_developer_sw);
-
-	/* fetch gpios at once */
-	write_protect_sw = is_firmware_write_protect_gpio_asserted(
-			polarity_write_protect_sw);
-	recovery_sw = is_recovery_mode_gpio_asserted(
-			polarity_recovery_sw);
-	developer_sw = is_developer_mode_gpio_asserted(
-			polarity_developer_sw);
-
-	VBDEBUG(PREFIX "gpio value:\n");
-	VBDEBUG(PREFIX "- wpsw:  %d\n", write_protect_sw);
-	VBDEBUG(PREFIX "- recsw: %d\n", recovery_sw);
-	VBDEBUG(PREFIX "- devsw: %d\n", developer_sw);
-
-	if (developer_sw) {
+	if (cros_gpio_fetch(CROS_GPIO_WPSW, fdt, &wpsw) ||
+			cros_gpio_fetch(CROS_GPIO_RECSW, fdt, &recsw) ||
+			cros_gpio_fetch(CROS_GPIO_DEVSW, fdt, &devsw)) {
+		VBDEBUG(PREFIX "failed to fetch gpio\n");
+		reason = VBNV_RECOVERY_RO_UNSPECIFIED;
+	}
+
+	cros_gpio_dump(&wpsw);
+	cros_gpio_dump(&recsw);
+	cros_gpio_dump(&devsw);
+
+	if (devsw.value) {
 		_state.boot_flags |= BOOT_FLAG_DEVELOPER;
 		_state.boot_flags |= BOOT_FLAG_DEV_FIRMWARE;
 		*dev_mode = 1;
@@ -169,13 +152,13 @@ static uint32_t init_internal_state_bottom_half(firmware_storage_t *file,
 		reason = VBNV_RECOVERY_RO_SHARED_DATA;
 	}
 
-	if (crossystem_data_init(cdata, fdt, frid, fmap->readonly.fmap.offset,
+	if (crossystem_data_init(cdata, frid, fmap->readonly.fmap.offset,
 				_state.gbb_data, nvcxt->raw,
-				write_protect_sw, recovery_sw, developer_sw)) {
+				&wpsw, &recsw, &devsw)) {
 		VBDEBUG(PREFIX "init crossystem data fail\n");
 		reason = VBNV_RECOVERY_RO_UNSPECIFIED;
 	}
-	if (recovery_sw) {
+	if (recsw.value) {
 		_state.boot_flags |= BOOT_FLAG_RECOVERY;
 		reason = VBNV_RECOVERY_RO_MANUAL;
 	}
diff --git a/include/chromeos/cros_gpio.h b/include/chromeos/cros_gpio.h
new file mode 100644
index 0000000000..95129d5b2b
--- /dev/null
+++ b/include/chromeos/cros_gpio.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+/* GPIO interface for Chrome OS verified boot */
+
+#ifndef CROS_GPIO_H__
+#define CROS_GPIO_H__
+
+enum cros_gpio_index {
+	CROS_GPIO_WPSW = 0,
+	CROS_GPIO_RECSW,
+	CROS_GPIO_DEVSW,
+
+	CROS_GPIO_MAX_GPIO
+};
+
+enum cros_gpio_polarity {
+	CROS_GPIO_ACTIVE_LOW	= 0,
+	CROS_GPIO_ACTIVE_HIGH	= 1
+};
+
+typedef struct {
+	enum cros_gpio_index index;
+	int port;
+	int polarity;
+	int value;
+} cros_gpio_t;
+
+int cros_gpio_fetch(enum cros_gpio_index index, const void *fdt,
+		cros_gpio_t *gpio);
+
+int cros_gpio_dump(cros_gpio_t *gpio);
+
+#endif /* CROS_GPIO_H__ */
diff --git a/include/chromeos/crossystem_data.h b/include/chromeos/crossystem_data.h
index 9a5ac31ba8..08805fc953 100644
--- a/include/chromeos/crossystem_data.h
+++ b/include/chromeos/crossystem_data.h
@@ -11,6 +11,7 @@
 #ifndef __CHROMEOS_CROSSYSTEM_DATA_H__
 #define __CHROMEOS_CROSSYSTEM_DATA_H__
 
+#include <chromeos/cros_gpio.h>
 #include <vboot_nvstorage.h>
 #include <vboot_struct.h>
 
@@ -58,19 +59,18 @@ typedef struct {
  * - The recovery reason is default to VBNV_RECOVERY_NOT_REQUESTED.
  *
  * @param cdata is the data blob shared with crossystem
- * @param fdt points to a device tree
  * @param frid r/o firmware id; a zero-terminated string shorter than ID_LEN
  * @param fmap_data is the address of fmap in firmware
  * @param gbb_data points to gbb blob
  * @param nvcxt_raw points to the VbNvContext raw data
- * @param write_protect_sw stores the value of write protect gpio
- * @param recovery_sw stores the value of recovery mode gpio
- * @param developer_sw stores the value of developer mode gpio
+ * @param wpsw stores the value of write protect gpio
+ * @param recsw stores the value of recovery mode gpio
+ * @param devsw stores the value of developer mode gpio
  * @return 0 if it succeeds; non-zero if it fails
  */
-int crossystem_data_init(crossystem_data_t *cdata, void *fdt, char *frid,
+int crossystem_data_init(crossystem_data_t *cdata, char *frid,
 		uint32_t fmap_data, void *gbb_data, void *nvcxt_raw,
-		int write_protect_sw, int recovery_sw, int developer_sw);
+		cros_gpio_t *wpsw, cros_gpio_t *recsw, cros_gpio_t *devsw);
 
 /**
  * This sets rewritable firmware id. It should only be called in non-recovery
diff --git a/include/chromeos/gpio.h b/include/chromeos/gpio.h
deleted file mode 100644
index 6424c514ba..0000000000
--- a/include/chromeos/gpio.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-/* GPIO interface for Chrome OS verified boot */
-
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-enum polarity {
-	GPIO_ACTIVE_LOW		= 0,
-	GPIO_ACTIVE_HIGH	= 1
-};
-
-/* GPIO accessor functions: returns 0 if false, nonzero if true */
-int is_firmware_write_protect_gpio_asserted(enum polarity polarity);
-int is_recovery_mode_gpio_asserted(enum polarity polarity);
-int is_developer_mode_gpio_asserted(enum polarity polarity);
-
-#endif /* __GPIO_H__ */
diff --git a/lib/chromeos/crossystem_data.c b/lib/chromeos/crossystem_data.c
index 8dc4240fee..e12ef62ad9 100644
--- a/lib/chromeos/crossystem_data.c
+++ b/lib/chromeos/crossystem_data.c
@@ -28,9 +28,9 @@ enum {
 	CHSW_WRITE_PROTECT_DISABLED	= 0x200
 };
 
-int crossystem_data_init(crossystem_data_t *cdata, void *fdt, char *frid,
+int crossystem_data_init(crossystem_data_t *cdata, char *frid,
 		uint32_t fmap_data, void *gbb_data, void *nvcxt_raw,
-		int write_protect_sw, int recovery_sw, int developer_sw)
+		cros_gpio_t *wpsw, cros_gpio_t *recsw, cros_gpio_t *devsw)
 {
 	GoogleBinaryBlockHeader *gbbh = (GoogleBinaryBlockHeader *)gbb_data;
 
@@ -43,11 +43,11 @@ int crossystem_data_init(crossystem_data_t *cdata, void *fdt, char *frid,
 	strcpy(cdata->signature, "CHROMEOS");
 	cdata->version = SHARED_MEM_VERSION;
 
-	if (recovery_sw)
+	if (recsw->value)
 		cdata->chsw |= CHSW_RECOVERY_BUTTON_PRESSED;
-	if (developer_sw)
+	if (devsw->value)
 		cdata->chsw |= CHSW_DEVELOPER_MODE_ENABLED;
-	if (!write_protect_sw)
+	if (!wpsw->value)
 		cdata->chsw |= CHSW_WRITE_PROTECT_DISABLED;
 
 	strncpy(cdata->frid, frid, ID_LEN);
@@ -60,23 +60,17 @@ int crossystem_data_init(crossystem_data_t *cdata, void *fdt, char *frid,
 	/* recovery reason is default to VBNV_RECOVERY_NOT_REQUESTED */
 	cdata->binf[4] = VBNV_RECOVERY_NOT_REQUESTED;
 
-	cdata->write_protect_sw = write_protect_sw;
-	cdata->recovery_sw = recovery_sw;
-	cdata->developer_sw = developer_sw;
-
-	cdata->gpio_port_write_protect_sw = fdt_decode_get_config_int(fdt,
-			"gpio_port_write_protect_switch", -1);
-	cdata->gpio_port_recovery_sw = fdt_decode_get_config_int(fdt,
-			"gpio_port_recovery_switch", -1);
-	cdata->gpio_port_developer_sw = fdt_decode_get_config_int(fdt,
-			"gpio_port_developer_switch", -1);
-
-	cdata->polarity_write_protect_sw = fdt_decode_get_config_int(fdt,
-			"polarity_write_protect_switch", -1);
-	cdata->polarity_recovery_sw = fdt_decode_get_config_int(fdt,
-			"polarity_recovery_switch", -1);
-	cdata->polarity_developer_sw = fdt_decode_get_config_int(fdt,
-			"polarity_developer_switch", -1);
+	cdata->gpio_port_write_protect_sw = wpsw->port;
+	cdata->gpio_port_recovery_sw = recsw->port;
+	cdata->gpio_port_developer_sw = devsw->port;
+
+	cdata->polarity_write_protect_sw = wpsw->polarity;
+	cdata->polarity_recovery_sw = recsw->polarity;
+	cdata->polarity_developer_sw = devsw->polarity;
+
+	cdata->write_protect_sw = wpsw->value;
+	cdata->recovery_sw = recsw->value;
+	cdata->developer_sw = devsw->value;
 
 	cdata->vbnv[0] = 0;
 	cdata->vbnv[1] = VBNV_BLOCK_SIZE;