diff options
| author | Frank Li <Frank.Li@nxp.com> | 2020-02-12 15:55:45 -0600 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-04-06 18:03:31 +0800 |
| commit | 2cc7388c3a2f4d0028471f5ddf25ae9ee2aab19b (patch) | |
| tree | bc2887784bc21d62516c88d20178a614961343d3 | |
| parent | fa14e43a8f4e80fdd0baba3413337c7000aa5ed2 (diff) | |
MLK-23311-2: 8DXL enable second usb controller
USB OH clock is default enabled by SCFW because it shared
between two USB controller.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
(cherry picked from commit 7a8ec829d4410c51550ad7a589645595042ba541)
(cherry picked from commit c0041c43f554a778c27d7574b3d58fb76ace6d48)
(cherry picked from commit a4fdd6210a081fd391ae574efe94cacef6c1ddcd)
(cherry picked from commit ea3731bf3d99bbcaa95c25775d7dfb651a8a8cb6)
| -rw-r--r-- | arch/arm/dts/fsl-imx8dxl.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-imx8/imx-regs.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8/clock.c | 2 | ||||
| -rw-r--r-- | drivers/clk/imx/clk-imx8qxp.c | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx8qxp-clock.h | 3 |
5 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm/dts/fsl-imx8dxl.dtsi b/arch/arm/dts/fsl-imx8dxl.dtsi index 20f0ed8c058..3c1d7acbe4a 100644 --- a/arch/arm/dts/fsl-imx8dxl.dtsi +++ b/arch/arm/dts/fsl-imx8dxl.dtsi @@ -1107,7 +1107,7 @@ usbphy2: usbphy@0x5b110000 { compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x0 0x5b110000 0x0 0x1000>; - clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; + clocks = <&clk IMX8DXL_USB2_PHY2_IPG_CLK>; power-domains = <&pd_conn_usbotg1_phy>; }; @@ -1130,7 +1130,7 @@ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc1 0>; - clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -1146,7 +1146,7 @@ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc2 0>; - clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index c543e7d1ba0..3638e58388d 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -53,6 +53,7 @@ #define USB_BASE_ADDR 0x5b0d0000 #define USB_PHY0_BASE_ADDR 0x5b100000 +#define USB_PHY1_BASE_ADDR 0x5b110000 #define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 645225e4c25..d63f6e864e9 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -214,7 +214,9 @@ void init_clk_gpmi_nand(void) void enable_usboh3_clk(unsigned char enable) { +#if !defined(CONFIG_IMX8DXL) lpcg_all_clock_on(USB_2_LPCG); +#endif return; } diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 63401b466f9..c1c8da3230d 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -144,14 +144,20 @@ static struct imx8_lpcg_clks imx8qxp_lpcg_clks[] = { CLK_5( IMX8QXP_LSIO_FSPI0_HCLK, "FSPI0_HCLK", 0x10, FSPI_0_LPCG, IMX8QXP_LSIO_MEM_CLK ), CLK_5( IMX8QXP_LSIO_FSPI0_CLK, "FSPI0_CLK", 0, FSPI_0_LPCG, IMX8QXP_LSIO_FSPI0_DIV ), +#if !defined(CONFIG_IMX8DXL) CLK_5( IMX8QXP_USB2_OH_AHB_CLK, "USB2_OH_AHB", 24, USB_2_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ), CLK_5( IMX8QXP_USB2_OH_IPG_S_CLK, "USB2_OH_IPG_S", 16, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), CLK_5( IMX8QXP_USB2_OH_IPG_S_PL301_CLK, "USB2_OH_IPG_S_PL301", 20, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), +#endif CLK_5( IMX8QXP_USB2_PHY_IPG_CLK, "USB2_PHY_IPG", 28, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), CLK_5( IMX8QXP_USB3_IPG_CLK, "USB3_IPG", 16, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), CLK_5( IMX8QXP_USB3_CORE_PCLK, "USB3_CORE", 20, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), CLK_5( IMX8QXP_USB3_PHY_CLK, "USB3_PHY", 24, USB_3_LPCG, IMX8QXP_USB3_IPG_CLK ), + +#if defined(CONFIG_IMX8DXL) + CLK_5( IMX8DXL_USB2_PHY2_IPG_CLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), +#endif CLK_5( IMX8QXP_USB3_ACLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QXP_USB3_ACLK_DIV ), CLK_5( IMX8QXP_USB3_BUS_CLK, "USB3_BUS", 0, USB_3_LPCG, IMX8QXP_USB3_BUS_DIV ), CLK_5( IMX8QXP_USB3_LPM_CLK, "USB3_LPM", 4, USB_3_LPCG, IMX8QXP_USB3_LPM_DIV ), diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h index fb563e26d13..d67a7742cff 100644 --- a/include/dt-bindings/clock/imx8qxp-clock.h +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -590,5 +590,6 @@ #define IMX8DXL_EQOS_PTP_CLK_S 541 #define IMX8DXL_EQOS_PTP_CLK 542 -#define IMX8QXP_CLK_END 543 +#define IMX8DXL_USB2_PHY2_IPG_CLK 543 +#define IMX8DXL_CLK_END 544 #endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ |