ENGR00230437: mx6: epdc: EPDC I/O setup after V3p3 is enable

EPDC will be used when splash screen is shown, EPDC io setup is done
before 3V3 digitial power, which cause critical chip burn-out for all
platforms.

To follow the E-Ink specification, setup EPDC I/O after V3p3 is enable.

Signed-off-by: Fugang Duan  <B38611@freescale.com>

4 files changed, 380 insertions, 243 deletions

diff --git a/board/freescale/mx6q_arm2/mx6q_arm2.c b/board/freescale/mx6q_arm2/mx6q_arm2.c
index 490cb687ae..45388ee40f 100644
--- a/board/freescale/mx6q_arm2/mx6q_arm2.c
+++ b/board/freescale/mx6q_arm2/mx6q_arm2.c
@@ -809,7 +809,7 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_MXC_EPDC
 #ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
+int setup_splash_img(void)
 {
 #ifdef CONFIG_SPLASH_IS_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
@@ -847,6 +847,8 @@ int setup_splash_img()
 
 	return (n == blk_cnt) ? 0 : -1;
 #endif
+
+	return 0;
 }
 #endif
 
@@ -881,7 +883,7 @@ struct epdc_timing_params panel_timings = {
 	.num_ce = 1,
 };
 
-static void setup_epdc_power()
+static void setup_epdc_power(void)
 {
 	unsigned int reg;
 
@@ -913,73 +915,13 @@ static void setup_epdc_power()
 	writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
 }
 
-unsigned int g_pgood_1, g_pgood_2, g_pgood_3;
-void epdc_power_on()
-{
-	unsigned int reg;
-
-	g_pgood_1 = readl(GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 20);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Set PMIC Wakeup to high - enable Display power */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 20);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	g_pgood_2 = readl(GPIO2_BASE_ADDR + GPIO_DR);
-		udelay(1000000);
-	g_pgood_3 = readl(GPIO2_BASE_ADDR + GPIO_DR);
-return;
-	/* Wait for PWRGOOD == 1 */
-	while (1) {
-		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-		if (!(reg & (1 << 21)))
-			break;
-
-		udelay(100);
-	}
-
-	/* Enable VCOM */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 17);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-
-	udelay(500);
-}
-
-void  epdc_power_off()
-{
-	unsigned int reg;
-	/* Set PMIC Wakeup to low - disable Display power */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 20);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	/* Disable VCOM */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 17);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 20);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-}
-
-int setup_waveform_file()
+int setup_waveform_file(void)
 {
 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
 	ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
 	ulong size = CONFIG_WAVEFORM_FILE_SIZE;
 	ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
-	char *s = NULL;
 	struct mmc *mmc = find_mmc_device(mmc_dev);
 	uint blk_start, blk_cnt, n;
 
@@ -1006,10 +948,8 @@ int setup_waveform_file()
 #endif
 }
 
-static void setup_epdc()
+static void epdc_enable_pins(void)
 {
-	unsigned int reg;
-
 	/* epdc iomux settings */
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A16__EPDC_SDDO_0);
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA10__EPDC_SDDO_1);
@@ -1031,6 +971,36 @@ static void setup_epdc()
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA4__EPDC_SDCE_0);
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA5__EPDC_SDCE_1);
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA6__EPDC_SDCE_2);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO */
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A16__GPIO_2_22);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA10__GPIO_3_10);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA12__GPIO_3_12);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA11__GPIO_3_11);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_LBA__GPIO_2_27);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_EB2__GPIO_2_30);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_CS0__GPIO_2_23);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_RW__GPIO_2_26);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A21__GPIO_2_17);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A22__GPIO_2_16);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A23__GPIO_6_6);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A24__GPIO_5_4);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D31__GPIO_3_31);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D27__GPIO_3_27);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA1__GPIO_3_1);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_EB1__GPIO_2_29);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA2__GPIO_3_2);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA4__GPIO_3_4);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA5__GPIO_3_5);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA6__GPIO_3_6);
+}
+
+static void setup_epdc(void)
+{
+	unsigned int reg;
 
 	/*** epdc Maxim PMIC settings ***/
 
@@ -1093,6 +1063,64 @@ static void setup_epdc()
 	/* Assign fb_base */
 	gd->fb_base = CONFIG_FB_BASE;
 }
+
+void epdc_power_on()
+{
+	unsigned int reg;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 20);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 20);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+		if (!(reg & (1 << 21)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 17);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+
+	udelay(500);
+}
+
+void  epdc_power_off()
+{
+	unsigned int reg;
+	/* Set PMIC Wakeup to low - disable Display power */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 20);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	/* Disable VCOM */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 17);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 20);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+}
 #endif
 
 /* For DDR mode operation, provide target delay parameter for each SD port.
diff --git a/board/freescale/mx6q_sabresd/mx6q_sabresd.c b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
index 7be4d26dff..1b898daa15 100644
--- a/board/freescale/mx6q_sabresd/mx6q_sabresd.c
+++ b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
@@ -1108,7 +1108,7 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_MXC_EPDC
 #ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
+int setup_splash_img(void)
 {
 #ifdef CONFIG_SPLASH_IS_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
@@ -1146,6 +1146,8 @@ int setup_splash_img()
 
 	return (n == blk_cnt) ? 0 : -1;
 #endif
+
+	return 0;
 }
 #endif
 
@@ -1180,7 +1182,7 @@ struct epdc_timing_params panel_timings = {
 	.num_ce = 1,
 };
 
-static void setup_epdc_power()
+static void setup_epdc_power(void)
 {
 	unsigned int reg;
 
@@ -1212,66 +1214,13 @@ static void setup_epdc_power()
 	writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
 }
 
-void epdc_power_on()
-{
-	unsigned int reg;
-
-	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 20);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Set PMIC Wakeup to high - enable Display power */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 20);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	/* Wait for PWRGOOD == 1 */
-	while (1) {
-		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-		if (!(reg & (1 << 21)))
-			break;
-
-		udelay(100);
-	}
-
-	/* Enable VCOM */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 17);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-
-	udelay(500);
-}
-
-void  epdc_power_off()
-{
-	unsigned int reg;
-	/* Set PMIC Wakeup to low - disable Display power */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 20);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	/* Disable VCOM */
-	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 17);
-	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
-	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 20);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-}
-
-int setup_waveform_file()
+int setup_waveform_file(void)
 {
 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
 	ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
 	ulong size = CONFIG_WAVEFORM_FILE_SIZE;
 	ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
-	char *s = NULL;
 	struct mmc *mmc = find_mmc_device(mmc_dev);
 	uint blk_start, blk_cnt, n;
 
@@ -1298,10 +1247,8 @@ int setup_waveform_file()
 #endif
 }
 
-static void setup_epdc()
+static void epdc_enable_pins(void)
 {
-	unsigned int reg;
-
 	/* epdc iomux settings */
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A16__EPDC_SDDO_0);
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA10__EPDC_SDDO_1);
@@ -1323,6 +1270,36 @@ static void setup_epdc()
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA4__EPDC_SDCE_0);
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA5__EPDC_SDCE_1);
 	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA6__EPDC_SDCE_2);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO */
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A16__GPIO_2_22);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA10__GPIO_3_10);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA12__GPIO_3_12);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA11__GPIO_3_11);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_LBA__GPIO_2_27);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_EB2__GPIO_2_30);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_CS0__GPIO_2_23);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_RW__GPIO_2_26);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A21__GPIO_2_17);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A22__GPIO_2_16);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A23__GPIO_6_6);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A24__GPIO_5_4);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D31__GPIO_3_31);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D27__GPIO_3_27);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA1__GPIO_3_1);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_EB1__GPIO_2_29);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA2__GPIO_3_2);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA4__GPIO_3_4);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA5__GPIO_3_5);
+	mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA6__GPIO_3_6);
+}
+
+static void setup_epdc(void)
+{
+	unsigned int reg;
 
 	/*** epdc Maxim PMIC settings ***/
 
@@ -1385,6 +1362,64 @@ static void setup_epdc()
 	/* Assign fb_base */
 	gd->fb_base = CONFIG_FB_BASE;
 }
+
+void epdc_power_on()
+{
+	unsigned int reg;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 20);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 20);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+		if (!(reg & (1 << 21)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 17);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+
+	udelay(500);
+}
+
+void  epdc_power_off()
+{
+	unsigned int reg;
+	/* Set PMIC Wakeup to low - disable Display power */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 20);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	/* Disable VCOM */
+	reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 17);
+	writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 20);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+}
 #endif
 
 /* For DDR mode operation, provide target delay parameter for each SD port.
diff --git a/board/freescale/mx6sl_arm2/mx6sl_arm2.c b/board/freescale/mx6sl_arm2/mx6sl_arm2.c
index ad6f47fe22..0772c090d2 100644
--- a/board/freescale/mx6sl_arm2/mx6sl_arm2.c
+++ b/board/freescale/mx6sl_arm2/mx6sl_arm2.c
@@ -253,7 +253,7 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_MXC_EPDC
 #ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
+int setup_splash_img(void)
 {
 #ifdef CONFIG_SPLASH_IS_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
@@ -291,6 +291,8 @@ int setup_splash_img()
 
 	return (n == blk_cnt) ? 0 : -1;
 #endif
+
+	return 0;
 }
 #endif
 
@@ -325,7 +327,7 @@ struct epdc_timing_params panel_timings = {
 	.num_ce = 1,
 };
 
-static void setup_epdc_power()
+static void setup_epdc_power(void)
 {
 	unsigned int reg;
 
@@ -357,66 +359,13 @@ static void setup_epdc_power()
 	writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
 }
 
-void epdc_power_on()
-{
-	unsigned int reg;
-
-	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 7);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Set PMIC Wakeup to high - enable Display power */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 14);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Wait for PWRGOOD == 1 */
-	while (1) {
-		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-		if (!(reg & (1 << 13)))
-			break;
-
-		udelay(100);
-	}
-
-	/* Enable VCOM */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 3);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-
-	udelay(500);
-}
-
-void  epdc_power_off()
-{
-	unsigned int reg;
-	/* Set PMIC Wakeup to low - disable Display power */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 14);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Disable VCOM */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 3);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 7);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-}
-
-int setup_waveform_file()
+int setup_waveform_file(void)
 {
 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
 	ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
 	ulong size = CONFIG_WAVEFORM_FILE_SIZE;
 	ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
-	char *s = NULL;
 	struct mmc *mmc = find_mmc_device(mmc_dev);
 	uint blk_start, blk_cnt, n;
 
@@ -443,10 +392,8 @@ int setup_waveform_file()
 #endif
 }
 
-static void setup_epdc()
+static void epdc_enable_pins(void)
 {
-	unsigned int reg;
-
 	/* epdc iomux settings */
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D0__EPDC_SDDO_0);
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D1__EPDC_SDDO_1);
@@ -468,6 +415,36 @@ static void setup_epdc()
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE_0);
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE_1);
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE_2);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D0__GPIO_1_7);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D1__GPIO_1_8);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D2__GPIO_1_9);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D3__GPIO_1_10);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D4__GPIO_1_11);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D5__GPIO_1_12);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D6__GPIO_1_13);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D7__GPIO_1_14);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDCLK__GPIO_1_31);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDSP__GPIO_2_2);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDOE__GPIO_2_0);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDRL__GPIO_2_1);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCLK__GPIO_1_23);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDOE__GPIO_1_25);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDLE__GPIO_1_24);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDSHR__GPIO_1_26);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_BDR0__GPIO_2_5);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE0__GPIO_1_27);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE1__GPIO_1_28);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE2__GPIO_1_29);
+}
+
+static void setup_epdc(void)
+{
+	unsigned int reg;
 
 	/*** epdc Maxim PMIC settings ***/
 
@@ -529,6 +506,64 @@ static void setup_epdc()
 	/* Assign fb_base */
 	gd->fb_base = CONFIG_FB_BASE;
 }
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 7);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 14);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+		if (!(reg & (1 << 13)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 3);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+
+	udelay(500);
+}
+
+void  epdc_power_off(void)
+{
+	unsigned int reg;
+	/* Set PMIC Wakeup to low - disable Display power */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 14);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	/* Disable VCOM */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 3);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 7);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+}
 #endif
 
 /* For DDR mode operation, provide target delay parameter for each SD port.
@@ -965,6 +1000,8 @@ static int setup_pmic_voltages(void)
 		printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
 
 	}
+
+	return 0;
 }
 #endif
 
diff --git a/board/freescale/mx6sl_evk/mx6sl_evk.c b/board/freescale/mx6sl_evk/mx6sl_evk.c
index 87ef68ec78..d53677f24d 100644
--- a/board/freescale/mx6sl_evk/mx6sl_evk.c
+++ b/board/freescale/mx6sl_evk/mx6sl_evk.c
@@ -244,7 +244,7 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_MXC_EPDC
 #ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
+int setup_splash_img(void)
 {
 #ifdef CONFIG_SPLASH_IS_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
@@ -281,6 +281,8 @@ int setup_splash_img()
 
 	return (n == blk_cnt) ? 0 : -1;
 #endif
+
+	return 0;
 }
 #endif
 
@@ -315,7 +317,7 @@ struct epdc_timing_params panel_timings = {
 	.num_ce = 1,
 };
 
-static void setup_epdc_power()
+static void setup_epdc_power(void)
 {
 	unsigned int reg;
 
@@ -347,66 +349,13 @@ static void setup_epdc_power()
 	writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
 }
 
-void epdc_power_on()
-{
-	unsigned int reg;
-
-	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 7);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Set PMIC Wakeup to high - enable Display power */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 14);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Wait for PWRGOOD == 1 */
-	while (1) {
-		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-		if (!(reg & (1 << 13)))
-			break;
-
-		udelay(100);
-	}
-
-	/* Enable VCOM */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 3);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-
-	udelay(500);
-}
-
-void epdc_power_off()
-{
-	unsigned int reg;
-	/* Set PMIC Wakeup to low - disable Display power */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 14);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Disable VCOM */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 3);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
-	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
-	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
-	reg &= ~(1 << 7);
-	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-}
-
-int setup_waveform_file()
+int setup_waveform_file(void)
 {
 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC
 	int mmc_dev = get_mmc_env_devno();
 	ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
 	ulong size = CONFIG_WAVEFORM_FILE_SIZE;
 	ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
-	char *s = NULL;
 	struct mmc *mmc = find_mmc_device(mmc_dev);
 	uint blk_start, blk_cnt, n;
 
@@ -432,10 +381,8 @@ int setup_waveform_file()
 #endif
 }
 
-static void setup_epdc()
+static void epdc_enable_pins(void)
 {
-	unsigned int reg;
-
 	/* epdc iomux settings */
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D0__EPDC_SDDO_0);
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D1__EPDC_SDDO_1);
@@ -457,6 +404,36 @@ static void setup_epdc()
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE_0);
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE_1);
 	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE_2);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D0__GPIO_1_7);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D1__GPIO_1_8);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D2__GPIO_1_9);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D3__GPIO_1_10);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D4__GPIO_1_11);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D5__GPIO_1_12);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D6__GPIO_1_13);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_D7__GPIO_1_14);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDCLK__GPIO_1_31);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDSP__GPIO_2_2);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDOE__GPIO_2_0);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_GDRL__GPIO_2_1);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCLK__GPIO_1_23);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDOE__GPIO_1_25);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDLE__GPIO_1_24);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDSHR__GPIO_1_26);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_BDR0__GPIO_2_5);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE0__GPIO_1_27);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE1__GPIO_1_28);
+	mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_SDCE2__GPIO_1_29);
+}
+
+static void setup_epdc(void)
+{
+	unsigned int reg;
 
 	/*** epdc Maxim PMIC settings ***/
 
@@ -518,6 +495,64 @@ static void setup_epdc()
 	/* Assign fb_base */
 	gd->fb_base = CONFIG_FB_BASE;
 }
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 7);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 14);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+		if (!(reg & (1 << 13)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 3);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	unsigned int reg;
+	/* Set PMIC Wakeup to low - disable Display power */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 14);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	/* Disable VCOM */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 3);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+	reg &= ~(1 << 7);
+	writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+}
 #endif
 
 /* For DDR mode operation, provide target delay parameter for each SD port.
@@ -960,6 +995,8 @@ static int setup_pmic_voltages(void)
 		printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
 
 	}
+
+	return 0;
 }
 #endif