diff options
| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2009-10-07 15:47:44 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-07 15:47:44 -0400 |
| commit | 6edfaa93203b8fd6caff435f8ae00080d46fcaea (patch) | |
| tree | 29a08953fe44a88d0adb3dddf953be1312379e4c | |
| parent | 7fd9bbc747fdfd038281d9d3d080c8b484b425cd (diff) | |
u-boot-2009.03-p2020rdb-Support-of-P1-P2-processors-v2
Adds support for P20x0 processors of QorIQ series.
The processors are Low end and Ultra Low End products in QorIQ series.
All are e500 based with small variations.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
| -rw-r--r-- | cpu/mpc85xx/Makefile | 5 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 8 | ||||
| -rw-r--r-- | drivers/misc/fsl_law.c | 6 | ||||
| -rw-r--r-- | include/asm-ppc/global_data.h | 5 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 8 |
5 files changed, 29 insertions, 3 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 99d88a888d..d86fa8f720 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -1,4 +1,5 @@ # +# Copyright (C) 2009 Freescale Semiconductor, Inc. All Rights Reserved. # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -49,6 +50,10 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_P1020) += ddr-gen3.o +COBJS-$(CONFIG_P1021) += ddr-gen3.o +COBJS-$(CONFIG_P1011) += ddr-gen3.o +COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 177e35856b..87d80edf90 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -65,6 +65,14 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8572, 8572_E, 2, 64), CPU_TYPE_ENTRY(P2020, P2020, 2, 64), CPU_TYPE_ENTRY(P2020, P2020_E, 2, 64), + CPU_TYPE_ENTRY(P1020, P1020, 2, 32), + CPU_TYPE_ENTRY(P1020, P1020_E, 2, 32), + CPU_TYPE_ENTRY(P1021, P1021, 2, 32), + CPU_TYPE_ENTRY(P1021, P1021_E, 2, 32), + CPU_TYPE_ENTRY(P1011, P1011_E, 1, 32), + CPU_TYPE_ENTRY(P1011, P1011_E, 1, 32), + CPU_TYPE_ENTRY(P1012, P1012, 1, 32), + CPU_TYPE_ENTRY(P1012, P1012_E, 1, 32), }; struct cpu_type *identify_cpu(u32 ver) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 58340c16bd..4738793abf 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -39,7 +39,9 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ - defined(CONFIG_P2020) + defined(CONFIG_P2020) || \ + defined(CONFIG_P1020) || defined(CONFIG_P1021) || \ + defined(CONFIG_P1011) || defined(CONFIG_P1012) #define FSL_HW_NUM_LAWS 12 #else #error FSL_HW_NUM_LAWS not defined for this platform diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index bf4911b3b7..5d03670523 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -88,7 +88,10 @@ typedef struct global_data { u32 mem_sec_clk; #endif /* CONFIG_MPC8360 */ #endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536) +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536) \ + || defined(CONFIG_P2020) \ + || defined(CONFIG_P1020) || defined(CONFIG_P1021) \ + || defined(CONFIG_P1011) || defined(CONFIG_P1012) u32 sdhc_clk; #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 062d42d899..ed10b98cf6 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -959,6 +959,14 @@ #define SVR_8572_E 0x80E800 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P1020 0x80E400 +#define SVR_P1020_E 0x80EC00 +#define SVR_P1021 0x80E401 +#define SVR_P1021_E 0x80EC01 +#define SVR_P1011 0x80E500 +#define SVR_P1011_E 0x80ED00 +#define SVR_P1012 0x80E501 +#define SVR_P1012_E 0x80ED01 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 |