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authorTom Rini <trini@konsulko.com>2018-12-21 13:38:09 -0500
committerTom Rini <trini@konsulko.com>2018-12-21 13:38:09 -0500
commit562a63e86bc7b308a328a7bbdf0db237855c39a8 (patch)
tree4a43bc9ed8e360e64bf130224c599e866af18194
parent5c676780e116dc79c1819d6c49a2aa53e1053e04 (diff)
parent7a147220c6459aeb7c6b6f7afe4330dcce077c9b (diff)
Merge git://git.denx.de/u-boot-marvell
- Fix breakage in helios4: Change U-Boot offset on SPI Flash - Enable CONFIG_BLK for db-88f6820-amc
-rw-r--r--arch/arm/mach-mvebu/cpu.c6
-rw-r--r--configs/db-88f6820-amc_defconfig3
-rw-r--r--include/configs/helios4.h2
3 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index aa1be8ebab..919d05c88c 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -283,10 +283,8 @@ int print_cpuinfo(void)
* and sets the correct windows sizes and base addresses accordingly.
*
* These values are set in the scratch registers by the Marvell
- * DDR3 training code, which is executed by the BootROM before the
- * main payload (U-Boot) is executed. This training code is currently
- * only available in the Marvell U-Boot version. It needs to be
- * ported to mainline U-Boot SPL at some point.
+ * DDR3 training code, which is executed by the SPL before the
+ * main payload (U-Boot) is executed.
*/
static void update_sdram_window_sizes(void)
{
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index dd58198a54..9068a58406 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -43,6 +43,9 @@ CONFIG_EFI_PARTITION=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BLK=y
+# CONFIG_SPL_BLK is not set
+# CONFIG_BLOCK_CACHE is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index 3157225f06..4e98f19a40 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -118,7 +118,7 @@
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif