diff options
Diffstat (limited to 'recipes-kernel')
-rw-r--r-- | recipes-kernel/linux/linux-toradex-mainline-4.9/0001-drm-tegra-add-tiling-FB-modifiers.patch | 128 | ||||
-rw-r--r-- | recipes-kernel/linux/linux-toradex-mainline_4.9.bb | 1 |
2 files changed, 129 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-drm-tegra-add-tiling-FB-modifiers.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-drm-tegra-add-tiling-FB-modifiers.patch new file mode 100644 index 0000000..48a560b --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-drm-tegra-add-tiling-FB-modifiers.patch @@ -0,0 +1,128 @@ +From 779ca8b35effc59faeeb24ed20a61f95035928fd Mon Sep 17 00:00:00 2001 +From: Alexandre Courbot <acourbot@nvidia.com> +Date: Fri, 16 Sep 2016 23:46:31 +0900 +Subject: [PATCH] drm/tegra: add tiling FB modifiers + +Add FB modifiers to allow user-space to specify that a surface is in one +of the two tiling formats supported by Tegra chips, and add support in +the tegradrm driver to handle them properly. This is necessary for the +display controller to directly display buffers generated by the GPU. + +This feature is intended to replace the dedicated IOCTL enabled +by TEGRA_STAGING and to provide a non-staging alternative to that +solution. + +Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> +Acked-by: Daniel Vetter <daniel@ffwll.ch> +--- + drivers/gpu/drm/tegra/drm.c | 2 ++ + drivers/gpu/drm/tegra/fb.c | 23 +++++++++++++++++++--- + include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 67 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c +index b8be3ee..13a1524 100644 +--- a/drivers/gpu/drm/tegra/drm.c ++++ b/drivers/gpu/drm/tegra/drm.c +@@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) + drm->mode_config.max_width = 4096; + drm->mode_config.max_height = 4096; + ++ drm->mode_config.allow_fb_modifiers = true; ++ + drm->mode_config.funcs = &tegra_drm_mode_funcs; + + err = tegra_drm_fb_prepare(drm); +diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c +index e4a5ab0..3faf38a 100644 +--- a/drivers/gpu/drm/tegra/fb.c ++++ b/drivers/gpu/drm/tegra/fb.c +@@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, + struct tegra_bo_tiling *tiling) + { + struct tegra_fb *fb = to_tegra_fb(framebuffer); +- +- /* TODO: handle YUV formats? */ +- *tiling = fb->planes[0]->tiling; ++ uint64_t modifier = fb->base.modifier; ++ ++ switch (fourcc_mod_tegra_mod(modifier)) { ++ case NV_FORMAT_MOD_TEGRA_TILED: ++ tiling->mode = TEGRA_BO_TILING_MODE_TILED; ++ tiling->value = 0; ++ break; ++ ++ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): ++ tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; ++ tiling->value = fourcc_mod_tegra_param(modifier); ++ if (tiling->value > 5) ++ return -EINVAL; ++ break; ++ ++ default: ++ /* TODO: handle YUV formats? */ ++ *tiling = fb->planes[0]->tiling; ++ break; ++ } + + return 0; + } +diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h +index a5890bf..967dfab 100644 +--- a/include/uapi/drm/drm_fourcc.h ++++ b/include/uapi/drm/drm_fourcc.h +@@ -233,6 +233,51 @@ extern "C" { + */ + #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) + ++ ++/* NVIDIA Tegra frame buffer modifiers */ ++ ++/* ++ * Some modifiers take parameters, for example the number of vertical GOBs in ++ * a block. Reserve the lower 32 bits for parameters ++ */ ++#define __fourcc_mod_tegra_mode_shift 32 ++#define fourcc_mod_tegra_code(val, params) \ ++ fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) ++#define fourcc_mod_tegra_mod(m) \ ++ (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) ++#define fourcc_mod_tegra_param(m) \ ++ (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) ++ ++/* ++ * Tegra Tiled Layout, used by Tegra 2, 3 and 4. ++ * ++ * Pixels are arranged in simple tiles of 16 x 16 bytes. ++ */ ++#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) ++ ++/* ++ * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 ++ * ++ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked ++ * vertically by a power of 2 (1 to 32 GOBs) to form a block. ++ * ++ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. ++ * ++ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. ++ * Valid values are: ++ * ++ * 0 == ONE_GOB ++ * 1 == TWO_GOBS ++ * 2 == FOUR_GOBS ++ * 3 == EIGHT_GOBS ++ * 4 == SIXTEEN_GOBS ++ * 5 == THIRTYTWO_GOBS ++ * ++ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format ++ * in full detail. ++ */ ++#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) ++ + #if defined(__cplusplus) + } + #endif +-- +2.9.3 + diff --git a/recipes-kernel/linux/linux-toradex-mainline_4.9.bb b/recipes-kernel/linux/linux-toradex-mainline_4.9.bb index 1d6ad91..f0ff5fe 100644 --- a/recipes-kernel/linux/linux-toradex-mainline_4.9.bb +++ b/recipes-kernel/linux/linux-toradex-mainline_4.9.bb @@ -27,6 +27,7 @@ SRC_URI = "https://cdn.kernel.org/pub/linux/kernel/v4.x/linux-${PV}.tar.xz \ file://0002-igb-integrate-tools-only-device-support.patch \ file://0003-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch \ file://0004-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch \ + file://0001-drm-tegra-add-tiling-FB-modifiers.patch \ " COMPATIBLE_MACHINE = "(apalis-tk1-mainline|apalis-t30-mainline)" |