[
    {
	"PublicDescription": "lpddr4 mek board bandwidth usage",
	"BriefDescription": "imx8qm: percentage of bandwidth usage for ddr0",
	"MetricName": "imx8qm-ddr0-bandwidth-usage",
	"MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)",
	"MetricGroup": "i.MX8QM_DDR_MON",
	"ScaleUnit": "1e2%",
	"SocName": "i.MX8QM"
    },
    {
	"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
	"BriefDescription": "imx8qm: bytes of all masters read from ddr0",
	"MetricName": "imx8qm-ddr0-all-r",
	"MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4",
	"MetricGroup": "i.MX8QM_DDR_MON",
	"SocName": "i.MX8QM"
    },
    {
	"PublicDescription": "Calculate bytes all masters wirte to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
	"BriefDescription": "imx8qm: bytes of all masters write to ddr0",
	"MetricName": "imx8qm-ddr0-all-w",
	"MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4",
	"MetricGroup": "i.MX8QM_DDR_MON",
	"SocName": "i.MX8QM"
    },
    {
	"PublicDescription": "lpddr4 mek board bandwidth usage",
	"BriefDescription": "imx8qm: percentage of bandwidth usage for ddr1",
	"MetricName": "imx8qm-ddr1-bandwidth-usage",
	"MetricExpr": "(( imx8_ddr1\\/read\\-cycles\\/ + imx8_ddr1\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)",
	"MetricGroup": "i.MX8QM_DDR_MON",
	"ScaleUnit": "1e2%",
	"SocName": "i.MX8QM"
    },
    {
	"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
	"BriefDescription": "imx8qm: bytes of all masters read from ddr1",
	"MetricName": "imx8qm-ddr1-all-r",
	"MetricExpr": "imx8_ddr1\\/read\\-cycles\\/ * 4 * 4",
	"MetricGroup": "i.MX8QM_DDR_MON",
	"SocName": "i.MX8QM"
    },
    {
	"PublicDescription": "Calculate bytes all masters wirte to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
	"BriefDescription": "imx8qm: bytes of all masters write to ddr1",
	"MetricName": "imx8qm-ddr1-all-w",
	"MetricExpr": "imx8_ddr1\\/write\\-cycles\\/ * 4 * 4",
	"MetricGroup": "i.MX8QM_DDR_MON",
	"SocName": "i.MX8QM"
    }
]