From 7bf8839d96911891af925b031bb54f80fcdba1f0 Mon Sep 17 00:00:00 2001 From: Seongho Joo Date: Mon, 19 Dec 2011 16:28:04 +0900 Subject: asoc: tegra: modify stepreset on dam src table set step value from 0 to 1 by the spec, with 0 it showed glitch. Bug 909514 Change-Id: Iebb0896592076fac5ffe71cec0806140228851d9 Reviewed-on: http://git-master/r/70960 Reviewed-by: Simone Willett Tested-by: Simone Willett --- sound/soc/tegra/tegra30_dam.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/tegra/tegra30_dam.c b/sound/soc/tegra/tegra30_dam.c index 2230748c9e73..4ac81266e7cf 100644 --- a/sound/soc/tegra/tegra30_dam.c +++ b/sound/soc/tegra/tegra30_dam.c @@ -45,7 +45,7 @@ enum { struct tegra30_dam_src_step_table step_table[] = { { 8000, 44100, 80 }, - { 8000, 48000, 0 }, + { 8000, 48000, 1 }, { 16000, 44100, 160 }, { 16000, 48000, 1 }, { 44100, 8000, 441 }, -- cgit v1.2.3