From 1c69524c2e5b83e52a098ebdeb4a8b52169f6a03 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Wed, 30 Jan 2008 13:30:39 +0100 Subject: x86: clear IO_APIC before enabing apic error vector. 4 socket quad core, 8 socket quad core will do apic ID lifting for BSP. But io-apic regs for ExtINT still use 0 as dest. so when we enable apic error vector in BSP, we will get one APIC error. CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 512K (64 bytes/line) CPU 0/4 -> Node 0 CPU: Physical Processor ID: 1 CPU: Processor Core ID: 0 SMP alternatives: switching to UP code ACPI: Core revision 20070126 enabled ExtINT on CPU#0 ESR value after enabling vector: 00000000, after 0000000c APIC error on CPU0: 0c(08) ENABLING IO-APIC IRQs Synchronizing Arb IDs. So move enable_IO_APIC from setup_IO_APIC into setup_local_APIC and call it before enabling the ACPI error vector. [ tglx: arch/x86 adaptation ] Signed-off-by: Yinghai Lu Signed-off-by: Andi Kleen Signed-off-by: Ingo Molnar Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic_64.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/x86/kernel/apic_64.c') diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c index 915808bd8a2a..994298bf4921 100644 --- a/arch/x86/kernel/apic_64.c +++ b/arch/x86/kernel/apic_64.c @@ -774,6 +774,13 @@ void __cpuinit setup_local_APIC(void) value = APIC_DM_NMI | APIC_LVT_MASKED; apic_write(APIC_LVT1, value); + /* + * Now enable IO-APICs, actually call clear_IO_APIC + * We need clear_IO_APIC before enabling vector on BP + */ + if (!smp_processor_id() && !skip_ioapic_setup && nr_ioapics) + enable_IO_APIC(); + { unsigned oldvalue; maxlvt = lapic_get_maxlvt(); -- cgit v1.2.3