From c881cbc033c80d92d1bb7a0446735561a46e1f9c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sat, 10 Nov 2007 20:18:18 +0900 Subject: sh: Don't reference UBC code in CPU init on sh64. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/init.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/sh/kernel/cpu/init.c') diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index c217c4bf0085..f37f1c031631 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -21,8 +21,10 @@ #include #include #include -#include #include +#ifdef CONFIG_SUPERH32 +#include +#endif /* * Generic wrapper for command line arguments to disable on-chip @@ -273,7 +275,10 @@ asmlinkage void __cpuinit sh_cpu_init(void) * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. * we wake it up and hope that all is well. */ +#ifdef CONFIG_SUPERH32 if (raw_smp_processor_id() == 0) ubc_wakeup(); +#endif + speculative_execution_init(); } -- cgit v1.2.3 From 27a511c6f37c05c5cf8fae9fe513f60d87af9158 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sat, 10 Nov 2007 20:25:28 +0900 Subject: sh: Disable initial cache flush on SH-5. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/init.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) (limited to 'arch/sh/kernel/cpu/init.c') diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index f37f1c031631..fd1688e6c61c 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -63,24 +63,11 @@ static void __init speculative_execution_init(void) /* * Generic first-level cache init */ +#ifdef CONFIG_SUPERH32 static void __init cache_init(void) { unsigned long ccr, flags; - /* First setup the rest of the I-cache info */ - current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - - current_cpu_data.icache.linesz; - - current_cpu_data.icache.way_size = current_cpu_data.icache.sets * - current_cpu_data.icache.linesz; - - /* And the D-cache too */ - current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - - current_cpu_data.dcache.linesz; - - current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * - current_cpu_data.dcache.linesz; - jump_to_P2(); ccr = ctrl_inl(CCR); @@ -160,6 +147,9 @@ static void __init cache_init(void) ctrl_outl(flags, CCR); back_to_P1(); } +#else +#define cache_init() do { } while (0) +#endif #ifdef CONFIG_SH_DSP static void __init release_dsp(void) @@ -230,6 +220,20 @@ asmlinkage void __cpuinit sh_cpu_init(void) if (current_cpu_data.type == CPU_SH_NONE) panic("Unknown CPU"); + /* First setup the rest of the I-cache info */ + current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - + current_cpu_data.icache.linesz; + + current_cpu_data.icache.way_size = current_cpu_data.icache.sets * + current_cpu_data.icache.linesz; + + /* And the D-cache too */ + current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - + current_cpu_data.dcache.linesz; + + current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; + /* Init the cache */ cache_init(); -- cgit v1.2.3 From cbaa118ecfd99fc5ed7adbd9c34a30e1c05e3c93 Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Fri, 30 Nov 2007 17:06:36 +0900 Subject: sh: Preparation for uncached jumps through PMB. Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/sh/kernel/cpu/init.c') diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index fd1688e6c61c..0f0c76a842e4 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -64,11 +64,11 @@ static void __init speculative_execution_init(void) * Generic first-level cache init */ #ifdef CONFIG_SUPERH32 -static void __init cache_init(void) +static void __uses_jump_to_uncached cache_init(void) { unsigned long ccr, flags; - jump_to_P2(); + jump_to_uncached(); ccr = ctrl_inl(CCR); /* @@ -145,7 +145,7 @@ static void __init cache_init(void) #endif ctrl_outl(flags, CCR); - back_to_P1(); + back_to_cached(); } #else #define cache_init() do { } while (0) -- cgit v1.2.3 From cd01204b82933754a7276838656420477f64d4b8 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 10 Dec 2007 15:50:28 +0900 Subject: sh: Encode L1/L2 cache shape in auxvt. This adds in the L1I/L1D/L2 cache shape support to their respective entries in the ELF auxvt, based on the Alpha implementation. We use this on the userspace libc side for calculating a tightly packed SHMLBA amongst other things. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/init.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) (limited to 'arch/sh/kernel/cpu/init.c') diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 0f0c76a842e4..80a31329ead9 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_SUPERH32 @@ -151,6 +153,27 @@ static void __uses_jump_to_uncached cache_init(void) #define cache_init() do { } while (0) #endif +#define CSHAPE(totalsize, linesize, assoc) \ + ((totalsize & ~0xff) | (linesize << 4) | assoc) + +#define CACHE_DESC_SHAPE(desc) \ + CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways) + +static void detect_cache_shape(void) +{ + l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); + + if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) + l1i_cache_shape = l1d_cache_shape; + else + l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); + + if (current_cpu_data.flags & CPU_HAS_L2_CACHE) + l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache); + else + l2_cache_shape = -1; /* No S-cache */ +} + #ifdef CONFIG_SH_DSP static void __init release_dsp(void) { @@ -237,11 +260,15 @@ asmlinkage void __cpuinit sh_cpu_init(void) /* Init the cache */ cache_init(); - if (raw_smp_processor_id() == 0) + if (raw_smp_processor_id() == 0) { shm_align_mask = max_t(unsigned long, current_cpu_data.dcache.way_size - 1, PAGE_SIZE - 1); + /* Boot CPU sets the cache shape */ + detect_cache_shape(); + } + /* Disable the FPU */ if (fpu_disabled) { printk("FPU Disabled\n"); -- cgit v1.2.3