From b80a32b9cc634adfa8eaef33ec981e7febf2ade2 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Tue, 26 Feb 2008 13:07:02 -0500 Subject: Update the i.MX31 Kernel to 2.6.23 This is the result of a brute-force attempt to update the kernel to 2.6.23. Now that we have a git tree, our effort will be a little nicer in the future. Signed-off-by: Justin Waters --- arch/mips/mm/Makefile | 3 +++ arch/mips/mm/c-r4k.c | 58 ++++++++++++++++++++++++++++++++++++++++++++-- arch/mips/mm/c-sb1.c | 4 ++-- arch/mips/mm/cache.c | 10 ++++++++ arch/mips/mm/dma-default.c | 2 +- arch/mips/mm/fault.c | 23 +++++++++--------- arch/mips/mm/init.c | 16 ++++++++++--- arch/mips/mm/pg-r4k.c | 2 +- arch/mips/mm/tlb-r4k.c | 23 +++++++++++++++++- arch/mips/mm/tlbex.c | 38 +++++++++++++++++++++++++----- 10 files changed, 151 insertions(+), 28 deletions(-) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 293697b15603..43e4810dcaa8 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o +obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o @@ -31,3 +32,5 @@ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index df04a315d830..bad571971bf6 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -335,6 +336,10 @@ static void r4k_flush_cache_all(void) static inline void local_r4k___flush_cache_all(void * args) { +#if defined(CONFIG_CPU_LOONGSON2) + r4k_blast_scache(); + return; +#endif r4k_blast_dcache(); r4k_blast_icache(); @@ -848,6 +853,24 @@ static void __init probe_pcache(void) c->options |= MIPS_CPU_PREFETCH; break; + case CPU_LOONGSON2: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + if (prid & 0x3) + c->icache.ways = 4; + else + c->icache.ways = 2; + c->icache.waybit = 0; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + if (prid & 0x3) + c->dcache.ways = 4; + else + c->dcache.ways = 2; + c->dcache.waybit = 0; + break; + default: if (!(config & MIPS_CONF_M)) panic("Don't know how to probe P-caches on this cpu."); @@ -963,6 +986,14 @@ static void __init probe_pcache(void) break; } +#ifdef CONFIG_CPU_LOONGSON2 + /* + * LOONGSON2 has 4 way icache, but when using indexed cache op, + * one op will act on all 4 ways + */ + c->icache.ways = 1; +#endif + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", @@ -980,7 +1011,6 @@ static void __init probe_pcache(void) */ static int __init probe_scache(void) { - extern unsigned long stext; unsigned long flags, addr, begin, end, pow2; unsigned int config = read_c0_config(); struct cpuinfo_mips *c = ¤t_cpu_data; @@ -989,7 +1019,7 @@ static int __init probe_scache(void) if (config & CONF_SC) return 0; - begin = (unsigned long) &stext; + begin = (unsigned long) &_stext; begin &= ~((4 * 1024 * 1024) - 1); end = begin + (4 * 1024 * 1024); @@ -1036,6 +1066,24 @@ static int __init probe_scache(void) return 1; } +#if defined(CONFIG_CPU_LOONGSON2) +static void __init loongson2_sc_init(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + scache_size = 512*1024; + c->scache.linesz = 32; + c->scache.ways = 4; + c->scache.waybit = 0; + c->scache.waysize = scache_size / (c->scache.ways); + c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); + pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", + scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + + c->options |= MIPS_CPU_INCLUSIVE_CACHES; +} +#endif + extern int r5k_sc_init(void); extern int rm7k_sc_init(void); extern int mips_sc_init(void); @@ -1085,6 +1133,12 @@ static void __init setup_scache(void) #endif return; +#if defined(CONFIG_CPU_LOONGSON2) + case CPU_LOONGSON2: + loongson2_sc_init(); + return; +#endif + default: if (c->isa_level == MIPS_CPU_ISA_M32R1 || c->isa_level == MIPS_CPU_ISA_M32R2 || diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index 9ea460b16bda..85ce2842d0da 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -272,7 +272,7 @@ void sb1_flush_cache_data_page(unsigned long) /* * Invalidate all caches on this CPU */ -static void __attribute_used__ local_sb1___flush_cache_all(void) +static void __used local_sb1___flush_cache_all(void) { __sb1_writeback_inv_dcache_all(); __sb1_flush_icache_all(); @@ -476,7 +476,7 @@ static __init void probe_cache_sizes(void) * memory management function pointers, as well as initialize * the caches and tlbs */ -void sb1_cache_init(void) +void __init sb1_cache_init(void) { extern char except_vec2_sb1; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index abf99b1eba13..81f925a9a731 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -6,6 +6,8 @@ * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2007 MIPS Technologies, Inc. */ +#include +#include #include #include #include @@ -164,3 +166,11 @@ void __init cpu_cache_init(void) panic(cache_panic); } + +int __weak __uncached_access(struct file *file, unsigned long addr) +{ + if (file->f_flags & O_SYNC) + return 1; + + return addr >= __pa(high_memory); +} diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 76903c727647..f60b3dc0fc62 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -35,7 +35,7 @@ static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr) static inline int cpu_is_noncoherent_r10000(struct device *dev) { return !plat_device_is_coherent(dev) && - (current_cpu_data.cputype == CPU_R10000 && + (current_cpu_data.cputype == CPU_R10000 || current_cpu_data.cputype == CPU_R12000); } diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 7ebea331edb8..521771b373de 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -39,6 +39,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, struct mm_struct *mm = tsk->mm; const int field = sizeof(unsigned long) * 2; siginfo_t info; + int fault; #if 0 printk("Cpu%d[%s:%d:%0*lx:%ld:%0*lx]\n", raw_smp_processor_id(), @@ -102,20 +103,18 @@ survive: * make sure we exit gracefully rather than endlessly redo * the fault. */ - switch (handle_mm_fault(mm, vma, address, write)) { - case VM_FAULT_MINOR: - tsk->min_flt++; - break; - case VM_FAULT_MAJOR: - tsk->maj_flt++; - break; - case VM_FAULT_SIGBUS: - goto do_sigbus; - case VM_FAULT_OOM: - goto out_of_memory; - default: + fault = handle_mm_fault(mm, vma, address, write); + if (unlikely(fault & VM_FAULT_ERROR)) { + if (fault & VM_FAULT_OOM) + goto out_of_memory; + else if (fault & VM_FAULT_SIGBUS) + goto do_sigbus; BUG(); } + if (fault & VM_FAULT_MAJOR) + tsk->maj_flt++; + else + tsk->min_flt++; up_read(&mm->mmap_sem); return; diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 4c80528deadd..5240432e6d1d 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -8,6 +8,7 @@ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. */ +#include #include #include #include @@ -26,6 +27,7 @@ #include #include +#include #include #include #include @@ -131,6 +133,8 @@ void *kmap_coherent(struct page *page, unsigned long addr) pte_t pte; int tlbidx; + BUG_ON(Page_dcache_dirty(page)); + inc_preempt_count(); idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); #ifdef CONFIG_MIPS_MT_SMTC @@ -207,7 +211,7 @@ void copy_user_highpage(struct page *to, struct page *from, void *vfrom, *vto; vto = kmap_atomic(to, KM_USER1); - if (cpu_has_dc_aliases) { + if (cpu_has_dc_aliases && !Page_dcache_dirty(from)) { vfrom = kmap_coherent(from, vaddr); copy_page(vto, vfrom); kunmap_coherent(); @@ -484,7 +488,7 @@ void free_initrd_mem(unsigned long start, unsigned long end) } #endif -void free_initmem(void) +void __init_refok free_initmem(void) { prom_free_prom_memory(); free_init_pages("unused kernel memory", @@ -498,7 +502,13 @@ unsigned long pgd_current[NR_CPUS]; * different layout ... */ #define __page_aligned(order) __attribute__((__aligned__(PAGE_SIZE<vm_flags & VM_EXEC) write_c0_diag(4); } + +#else + +#define FLUSH_ITLB +#define FLUSH_ITLB_VM(vma) + +#endif + void local_flush_tlb_all(void) { unsigned long flags; @@ -73,6 +89,7 @@ void local_flush_tlb_all(void) } tlbw_use_hazard(); write_c0_entryhi(old_ctx); + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -136,6 +153,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, } else { drop_mmu_context(mm, cpu); } + FLUSH_ITLB; EXIT_CRITICAL(flags); } } @@ -178,6 +196,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) } else { local_flush_tlb_all(); } + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -210,6 +229,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) finish: write_c0_entryhi(oldpid); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } } @@ -241,7 +261,7 @@ void local_flush_tlb_one(unsigned long page) tlbw_use_hazard(); } write_c0_entryhi(oldpid); - + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -293,6 +313,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) else tlb_write_indexed(); tlbw_use_hazard(); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index e7149290d1cb..6c425b052442 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -57,6 +57,21 @@ static __init int __maybe_unused r10000_llsc_war(void) return R10000_LLSC_WAR; } +/* + * Found by experiment: At least some revisions of the 4kc throw under + * some circumstances a machine check exception, triggered by invalid + * values in the index register. Delaying the tlbp instruction until + * after the next branch, plus adding an additional nop in front of + * tlbwi/tlbwr avoids the invalid index register values. Nobody knows + * why; it's not an issue caused by the core RTL. + * + */ +static __init int __attribute__((unused)) m4kc_tlbp_war(void) +{ + return (current_cpu_data.processor_id & 0xffff00) == + (PRID_COMP_MIPS | PRID_IMP_4KC); +} + /* * A little micro-assembler, intended for TLB refill handler * synthesizing. It is intentionally kept simple, does only support @@ -78,7 +93,7 @@ enum fields SET = 0x200 }; -#define OP_MASK 0x2f +#define OP_MASK 0x3f #define OP_SH 26 #define RS_MASK 0x1f #define RS_SH 21 @@ -92,7 +107,7 @@ enum fields #define IMM_SH 0 #define JIMM_MASK 0x3ffffff #define JIMM_SH 0 -#define FUNC_MASK 0x2f +#define FUNC_MASK 0x3f #define FUNC_SH 0 #define SET_MASK 0x7 #define SET_SH 0 @@ -893,6 +908,9 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_4KSC: case CPU_20KC: case CPU_25KF: + case CPU_LOONGSON2: + if (m4kc_tlbp_war()) + i_nop(p); tlbw(p); break; @@ -1276,7 +1294,8 @@ static void __init build_r4000_tlb_refill_handler(void) * need three, with the second nop'ed and the third being * unused. */ -#ifdef CONFIG_32BIT + /* Loongson2 ebase is different than r4k, we have more space */ +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) if ((p - tlb_handler) > 64) panic("TLB refill handler space exceeded"); #else @@ -1289,7 +1308,7 @@ static void __init build_r4000_tlb_refill_handler(void) /* * Now fold the handler in the TLB refill handler space. */ -#ifdef CONFIG_32BIT +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) f = final_handler; /* Simplest case, just copy the handler. */ copy_handler(relocs, labels, tlb_handler, p, f); @@ -1336,7 +1355,7 @@ static void __init build_r4000_tlb_refill_handler(void) final_len); f = final_handler; -#ifdef CONFIG_64BIT +#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2) if (final_len > 32) final_len = 64; else @@ -1703,7 +1722,8 @@ build_r4000_tlbchange_handler_head(u32 **p, struct label **l, l_smp_pgtable_change(l, *p); # endif iPTE_LW(p, l, pte, ptr); /* get even pte */ - build_tlb_probe_entry(p); + if (!m4kc_tlbp_war()) + build_tlb_probe_entry(p); } static void __init @@ -1745,6 +1765,8 @@ static void __init build_r4000_tlb_load_handler(void) build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); + if (m4kc_tlbp_war()) + build_tlb_probe_entry(&p); build_make_valid(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1779,6 +1801,8 @@ static void __init build_r4000_tlb_store_handler(void) build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); + if (m4kc_tlbp_war()) + build_tlb_probe_entry(&p); build_make_write(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1813,6 +1837,8 @@ static void __init build_r4000_tlb_modify_handler(void) build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); + if (m4kc_tlbp_war()) + build_tlb_probe_entry(&p); /* Present and writable bits set, set accessed and dirty bits. */ build_make_write(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); -- cgit v1.2.3