From 26150aa96d60298de669e3d81a5b7e132b653ce7 Mon Sep 17 00:00:00 2001 From: Jonathan Austin Date: Tue, 30 Aug 2016 17:24:34 +0100 Subject: ARM: 8602/1: factor out CSSELR/CCSIDR operations that use cp15 directly Currently we use raw cp15 operations to access the cache setup data. This patch abstracts the CSSELR and CCSIDR accessors out to a header so that the implementation for them can be switched out as we do with other cpu/cachetype operations. Signed-off-by: Jonathan Austin Signed-off-by: Vladimir Murzin Tested-by: Andras Szemzo Tested-by: Joachim Eastwood Tested-by: Alexandre TORGUE Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arm/kernel/setup.c') diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index aca999e17184..d7568808eb7b 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -290,12 +290,9 @@ static int cpu_has_aliasing_icache(unsigned int arch) /* arch specifies the register format */ switch (arch) { case CPU_ARCH_ARMv7: - asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR" - : /* No output operands */ - : "r" (1)); + set_csselr(CSSELR_ICACHE | CSSELR_L1); isb(); - asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR" - : "=r" (id_reg)); + id_reg = read_ccsidr(); line_size = 4 << ((id_reg & 0x7) + 2); num_sets = ((id_reg >> 13) & 0x7fff) + 1; aliasing_icache = (line_size * num_sets) > PAGE_SIZE; -- cgit v1.2.3