From 83dcec32f218b6bbe3114f4bb75b68833eef3934 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 20 Mar 2018 01:11:13 +0530 Subject: dt-bindings: Add vendor prefix for Bticino Added 'bticino' vendor prefix for Bticino International. Signed-off-by: Jagan Teki Signed-off-by: Simone CIANNI Signed-off-by: Raffaele RECALCATI Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b5f978a4cac6..402eccac46e0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -56,6 +56,7 @@ bosch Bosch Sensortec GmbH boundary Boundary Devices Inc. brcm Broadcom Corporation buffalo Buffalo, Inc. +bticino Bticino International calxeda Calxeda capella Capella Microsystems, Inc cascoda Cascoda, Ltd. -- cgit v1.2.3 From 7625f03be3177d63cc6e5763b0c2dfecc371ca95 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 27 Mar 2018 15:37:20 +0100 Subject: dt-bindings: arm: Document iW-RainboW-G23S single board computer Document the iW-RainboW-G23S single board computer device tree bindings, listing it as a supported board. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index d3d1df97834f..29093ba6c5d0 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -78,6 +78,8 @@ Boards: compatible = "renesas,h3ulcb", "renesas,r8a7795" - Henninger compatible = "renesas,henninger", "renesas,r8a7791" + - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) + compatible = "iwave,g23s", "renesas,r8a77470" - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745" - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) -- cgit v1.2.3 From 6fdc4f90b4950a7df1d314bdc53e25c1c4e70dc9 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 11 Apr 2018 18:35:51 +0900 Subject: dt-bindings: arm: Document R-Car E3 SoC DT bindings This patch adds device tree bindings documentation for Renesas R-Car E3 (r8a77990). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 29093ba6c5d0..e1a24708a284 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -45,6 +45,8 @@ SoCs: compatible = "renesas,r8a77970" - R-Car V3H (R8A77980) compatible = "renesas,r8a77980" + - R-Car E3 (R8A77990) + compatible = "renesas,r8a77990" - R-Car D3 (R8A77995) compatible = "renesas,r8a77995" -- cgit v1.2.3 From d2ba004b0341e63dc49f640ddd8e79c764ff16c8 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 11 Apr 2018 18:35:52 +0900 Subject: dt-bindings: arm: Document Renesas Ebisu board DT bindings This patch adds device tree bindings documentation for Renesas Ebisu board (RTP0RC77990SEB0010S). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index e1a24708a284..804f1d7c1f2b 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -69,6 +69,8 @@ Boards: compatible = "renesas,draak", "renesas,r8a77995" - Eagle (RTP0RC77970SEB0010S) compatible = "renesas,eagle", "renesas,r8a77970" + - Ebisu (RTP0RC77990SEB0010S) + compatible = "renesas,ebisu", "renesas,r8a77990" - Genmai (RTK772100BC00000BR) compatible = "renesas,genmai", "renesas,r7s72100" - GR-Peach (X28A-M01-E/F) -- cgit v1.2.3 From d3140a7961781e72f00eaad074212b96f07e695f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 18 Nov 2017 14:04:12 +0100 Subject: dt-binding: rng: Add interrupt property for BCM2835 As Sylvain Garrigues pointed out the BCM2835 RNG block has an interrupt. Also in preparation for Florian's upcoming patch series add this property to the binding. While we are at it fix the indenting of the example. Link: https://github.com/raspberrypi/linux/issues/2195 CC: Florian Fainelli Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/rng/brcm,bcm2835.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt index 627b29531a32..aaac7975f61c 100644 --- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt @@ -14,11 +14,16 @@ Optional properties: - clocks : phandle to clock-controller plus clock-specifier pair - clock-names : "ipsec" as a clock name +Optional properties: + +- interrupts: specify the interrupt for the RNG block + Example: rng { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + interrupts = <2 29>; }; rng@18033000 { -- cgit v1.2.3 From 9a209c6e952c71b00ee29dbf6cab0da766be7fe0 Mon Sep 17 00:00:00 2001 From: "kevans@FreeBSD.org" Date: Thu, 19 Apr 2018 09:11:03 -0500 Subject: ARM: dts: sunxi: Add sid for a83t Allwinner a83t has a 1 KB sid block with efuse for security rootkey and thermal calibration data, add node to describe it. a83t-sid is not currently supported by nvmem/sunxi-sid, but it is supported in an external driver for FreeBSD. Signed-off-by: Kyle Evans Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt index d69543701d5d..e319fe5e205a 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Should be one of the following: "allwinner,sun4i-a10-sid" "allwinner,sun7i-a20-sid" + "allwinner,sun8i-a83t-sid" "allwinner,sun8i-h3-sid" "allwinner,sun50i-a64-sid" -- cgit v1.2.3 From d4740560bc0318ae8fcbfb752ee9e3aefca7dc3f Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 15 Mar 2018 12:55:42 +0100 Subject: dt-bindings: clock: meson: update documentation with hhi syscon The HHI register region hosts more than just clocks and needs to accessed drivers other than the clock controller, such as the display driver. This register region should be managed by syscon. It is already the case on gxbb/gxl and it soon will be on axg. The clock controllers must use this system controller instead of directly mapping the registers. This changes the bindings of gxbb and axg's clock controllers. This is due to an initial 'incomplete' knowledge of these SoCs, which is why the meson bindings are unstable ATM. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- .../devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e2b377ed6f91..e950599566a9 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -10,9 +10,6 @@ Required Properties: "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. -- reg: physical base address of the clock controller and length of memory - mapped region. - - #clock-cells: should be 1. Each clock is assigned an identifier and client nodes can use this identifier @@ -20,13 +17,22 @@ to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be used in device tree sources. +Parent node should have the following properties : +- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or + "amlogic,meson-axg-hhi-sysctrl" +- reg: base address and size of the HHI system control register space. + Example: Clock controller node: - clkc: clock-controller@c883c000 { +sysctrl: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; - reg = <0x0 0xc883c000 0x0 0x3db>; }; +}; Example: UART controller node that consumes the clock generated by the clock controller: -- cgit v1.2.3 From 9db90175e0d02bf3a9e780c327b0b3ce6321140f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 21 Apr 2018 13:28:36 +0200 Subject: dt-bindings: bcm: Add Raspberry Pi 3 B+ This adds the root properties for the Raspberry Pi 3 B+ Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt Reviewed-by: Rob Herring Signed-off-by: Eric Anholt --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index 3e3efa046ac5..1e3e29a545e2 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -34,6 +34,10 @@ Raspberry Pi 3 Model B Required root node properties: compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; +Raspberry Pi 3 Model B+ +Required root node properties: +compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; + Raspberry Pi Compute Module Required root node properties: compatible = "raspberrypi,compute-module", "brcm,bcm2835"; -- cgit v1.2.3 From cce5819ba37c274f5242651fb8a260e3a00de557 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 9 Apr 2018 22:28:23 +0300 Subject: dt-bindings: arm: tegra: Remove duplicated Tegra30+ MC binding There are two bindings for the same Memory Controller. One of the bindings became obsolete long time ago and probably was left unnoticed, remove it for consistency. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra30-mc.txt | 18 ------------------ 1 file changed, 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt deleted file mode 100644 index bdf1a612422b..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt +++ /dev/null @@ -1,18 +0,0 @@ -NVIDIA Tegra30 MC(Memory Controller) - -Required properties: -- compatible : "nvidia,tegra30-mc" -- reg : Should contain 4 register ranges(address and length); see the - example below. Note that the MC registers are interleaved with the - SMMU registers, and hence must be represented as multiple ranges. -- interrupts : Should contain MC General interrupt. - -Example: - memory-controller { - compatible = "nvidia,tegra30-mc"; - reg = <0x7000f000 0x010 - 0x7000f03c 0x1b4 - 0x7000f200 0x028 - 0x7000f284 0x17c>; - interrupts = <0 77 0x04>; - }; -- cgit v1.2.3 From ca545e6c803d54a2dbffe783eb08ab177b3c4f0d Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 9 Apr 2018 22:28:24 +0300 Subject: dt-bindings: memory: tegra: Document #reset-cells property of the Tegra30 MC Memory Controller has a memory client "hot reset" functionality, which resets the DMA interface of a memory client. So MC is a reset controller in addition to IOMMU. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt index 14968b048cd3..a878b5908a4d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt @@ -12,6 +12,9 @@ Required properties: - clock-names: Must include the following entries: - mc: the module's clock input - interrupts: The interrupt outputs from the controller. +- #reset-cells : Should be 1. This cell represents memory client module ID. + The assignments may be found in header file + or in the TRM documentation. Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210: - #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines @@ -72,12 +75,14 @@ Example SoC include file: interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; sdhci@700b0000 { compatible = "nvidia,tegra124-sdhci"; ... iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; + resets = <&mc TEGRA124_MC_RESET_SDMMC1>; }; }; -- cgit v1.2.3 From 60eb8eff54f8b3ea388ee91b9ec652acb856fdf3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 9 Apr 2018 22:28:25 +0300 Subject: dt-bindings: arm: tegra: Document #reset-cells property of the Tegra20 MC Memory Controller has a memory client "hot reset" functionality, which resets the DMA interface of a memory client, so MC is a reset controller. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt index f9632bacbd04..7d60a50a4fa1 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt @@ -6,11 +6,21 @@ Required properties: example below. Note that the MC registers are interleaved with the GART registers, and hence must be represented as multiple ranges. - interrupts : Should contain MC General interrupt. +- #reset-cells : Should be 1. This cell represents memory client module ID. + The assignments may be found in header file + or in the TRM documentation. Example: - memory-controller@7000f000 { + mc: memory-controller@7000f000 { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; interrupts = <0 77 0x04>; + #reset-cells = <1>; + }; + + video-codec@6001a000 { + compatible = "nvidia,tegra20-vde"; + ... + resets = <&mc TEGRA20_MC_RESET_VDE>; }; -- cgit v1.2.3 From eb8f53b6d3125894e3d825976eb7e03150496362 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 27 Apr 2018 11:15:51 +0200 Subject: dt-bindings: Relocate Tegra20 memory controller bindings Move the device tree bindings for the Tegra20 memory controller to the same location as the Tegra30 (and later) memory controller bindings. Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra20-mc.txt | 26 ---------------------- .../memory-controllers/nvidia,tegra20-mc.txt | 26 ++++++++++++++++++++++ 2 files changed, 26 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt deleted file mode 100644 index 7d60a50a4fa1..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt +++ /dev/null @@ -1,26 +0,0 @@ -NVIDIA Tegra20 MC(Memory Controller) - -Required properties: -- compatible : "nvidia,tegra20-mc" -- reg : Should contain 2 register ranges(address and length); see the - example below. Note that the MC registers are interleaved with the - GART registers, and hence must be represented as multiple ranges. -- interrupts : Should contain MC General interrupt. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file - or in the TRM documentation. - -Example: - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc"; - reg = <0x7000f000 0x024 - 0x7000f03c 0x3c4>; - interrupts = <0 77 0x04>; - #reset-cells = <1>; - }; - - video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - ... - resets = <&mc TEGRA20_MC_RESET_VDE>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt new file mode 100644 index 000000000000..7d60a50a4fa1 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -0,0 +1,26 @@ +NVIDIA Tegra20 MC(Memory Controller) + +Required properties: +- compatible : "nvidia,tegra20-mc" +- reg : Should contain 2 register ranges(address and length); see the + example below. Note that the MC registers are interleaved with the + GART registers, and hence must be represented as multiple ranges. +- interrupts : Should contain MC General interrupt. +- #reset-cells : Should be 1. This cell represents memory client module ID. + The assignments may be found in header file + or in the TRM documentation. + +Example: + mc: memory-controller@7000f000 { + compatible = "nvidia,tegra20-mc"; + reg = <0x7000f000 0x024 + 0x7000f03c 0x3c4>; + interrupts = <0 77 0x04>; + #reset-cells = <1>; + }; + + video-codec@6001a000 { + compatible = "nvidia,tegra20-vde"; + ... + resets = <&mc TEGRA20_MC_RESET_VDE>; + }; -- cgit v1.2.3 From 519df0e05d2796805ee6d6e396423e60f3743b97 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 24 Apr 2018 07:54:42 +0200 Subject: dt-bindings: arm: consistently name r8a77965 as M3-N There is an inconsistency between the use of M3N and M3-N. This patch resolves this by consistently using the latter. Signed-off-by: Simon Horman Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 804f1d7c1f2b..0da876784dd5 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -114,7 +114,7 @@ Boards: compatible = "renesas,salvator-x", "renesas,r8a7795" - Salvator-X (RTP0RC7796SIPB0011S) compatible = "renesas,salvator-x", "renesas,r8a7796" - - Salvator-X (RTP0RC7796SIPB0011S (M3N)) + - Salvator-X (RTP0RC7796SIPB0011S (M3-N)) compatible = "renesas,salvator-x", "renesas,r8a77965" - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) compatible = "renesas,salvator-xs", "renesas,r8a7795" -- cgit v1.2.3 From 8c83315da1cf0843e036be6f6bd4dd99d580874a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 24 Apr 2018 22:32:30 +0200 Subject: ARM: dts: exynos: Remove Exynos5440 The Exynos5440 (quad-core A15 with GMAC, PCIe, SATA) was targeting server platforms but it did not make it to the market really. There are no development boards with it and probably there are no real products neither. The development for Exynos5440 ended in 2013 and since then the platform is in maintenance mode. Remove all Device Tree sources for Exynos5440, as first step of removal of the platform to simplify the code and drivers. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 14510b215480..bdadc3da9556 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -21,8 +21,6 @@ Required root node properties: - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board. - - "samsung,sd5v1" - for Exynos5440-based Samsung board. - - "samsung,ssdk5440" - for Exynos5440-based Samsung board. * Other companies Exynos SoC based * FriendlyARM -- cgit v1.2.3 From cfecb21109ab8de207670d4e7d8eaa3929cadd5c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 6 May 2018 11:21:14 +0200 Subject: dt-bindings: arm: amlogic: add support for the Meson8m2 SoC The Meson8m2 SoC is an updated version of the Meson8 SoC. Some of the peripherals are updated to be register-compatible with Meson8b. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index f747f47922c5..6c6642c69de3 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -25,6 +25,10 @@ Boards with the Amlogic Meson8b SoC shall have the following properties: Required root node property: compatible: "amlogic,meson8b"; +Boards with the Amlogic Meson8m2 SoC shall have the following properties: + Required root node property: + compatible: "amlogic,meson8m2"; + Boards with the Amlogic Meson GXBaby SoC shall have the following properties: Required root node property: compatible: "amlogic,meson-gxbb"; -- cgit v1.2.3 From c51fb2d458a6d62215c1ff6bbca8e5c876370e71 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 6 May 2018 11:21:15 +0200 Subject: dt-bindings: arm: amlogic: add support for the Tronsmart MXIII Plus Add the binding documentation for the Tronsmart MXIII Plus which is an Android TV box using the Amlogic S812 (Meson8m2) SoC. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 6c6642c69de3..69880560c0f0 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -58,6 +58,8 @@ Board compatible values (alphabetically, grouped by SoC): - "hardkernel,odroid-c1" (Meson8b) - "tronfy,mxq" (Meson8b) + - "tronsmart,mxiii-plus" (Meson8m2) + - "amlogic,p200" (Meson gxbb) - "amlogic,p201" (Meson gxbb) - "friendlyarm,nanopi-k2" (Meson gxbb) -- cgit v1.2.3 From 24d79d738b6fed977f44cae2ca277a49a7aa5f70 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 18 Dec 2017 17:39:01 +0000 Subject: dt-bindings: timer: renesas, cmt: Document r8a774[35] CMT support Document SoC specific compatible strings for r8a7743 and r8a7745. No driver change is needed as the fallback strings will activate the right code. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Acked-by: Daniel Lezcano Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index d740989eb569..b40add2d9bb4 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -22,6 +22,10 @@ Required Properties: - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4. - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4. + - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743. + - "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743. + - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745. + - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. @@ -31,10 +35,12 @@ Required Properties: - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. - - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2. - - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2. - These are fallbacks for r8a73a4 and all the R-Car Gen2 - entries listed above. + - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2 + and RZ/G1. + - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2 + and RZ/G1. + These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries + listed above. - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. -- cgit v1.2.3 From c92db4a4a4c6c176c34604e456d6d355803d9ada Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 10 May 2018 21:09:40 +0300 Subject: dt-bindings: arm: document Renesas V3HSK board bindings Document the V3H Starter Kit device tree bindings, listing it as a supported board. This allows to use checkpatch.pl to validate .dts files referring to the V3HSK board. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 0da876784dd5..593a7d82a1c8 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -130,6 +130,8 @@ Boards: compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) compatible = "renesas,stout", "renesas,r8a7790" + - V3HSK (Y-ASK-RCAR-V3H-WS10) + compatible = "renesas,v3hsk", "renesas,r8a77980" - V3MSK (Y-ASK-RCAR-V3M-WS10) compatible = "renesas,v3msk", "renesas,r8a77970" - Wheat (RTP0RC7792ASKB0000JE) -- cgit v1.2.3 From 07256d007582357ee6c91c6f9e0b055dbf6790cc Mon Sep 17 00:00:00 2001 From: Thierry Escande Date: Thu, 29 Mar 2018 21:15:23 +0200 Subject: dt-bindings: net: bluetooth: Add qualcomm-bluetooth Add binding document for serial bluetooth chips using Qualcomm protocol. Signed-off-by: Thierry Escande Reviewed-by: Rob Herring Signed-off-by: Andy Gross --- .../devicetree/bindings/net/qualcomm-bluetooth.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt b/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt new file mode 100644 index 000000000000..0ea18a53cc29 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt @@ -0,0 +1,30 @@ +Qualcomm Bluetooth Chips +--------------------- + +This documents the binding structure and common properties for serial +attached Qualcomm devices. + +Serial attached Qualcomm devices shall be a child node of the host UART +device the slave device is attached to. + +Required properties: + - compatible: should contain one of the following: + * "qcom,qca6174-bt" + +Optional properties: + - enable-gpios: gpio specifier used to enable chip + - clocks: clock provided to the controller (SUSCLK_32KHZ) + +Example: + +serial@7570000 { + label = "BT-UART"; + status = "okay"; + + bluetooth { + compatible = "qcom,qca6174-bt"; + + enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; + clocks = <&divclk4>; + }; +}; -- cgit v1.2.3 From e9b02415565b1f1fac4d393c7f06647fe4fadb56 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 30 Mar 2018 11:08:16 -0600 Subject: dt-bindings: soc: qcom: Add device tree binding for GENI SE Add device tree binding support for the QCOM GENI SE driver. Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Sagar Dharia Signed-off-by: Girish Mahadevan Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Andy Gross --- .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt new file mode 100644 index 000000000000..d330c73de9a2 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt @@ -0,0 +1,119 @@ +Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller + +Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper +is a programmable module for supporting a wide range of serial interfaces +like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial +Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP +Wrapper controller is modeled as a node with zero or more child nodes each +representing a serial engine. + +Required properties: +- compatible: Must be "qcom,geni-se-qup". +- reg: Must contain QUP register address and length. +- clock-names: Must contain "m-ahb" and "s-ahb". +- clocks: AHB clocks needed by the device. + +Required properties if child node exists: +- #address-cells: Must be <1> for Serial Engine Address +- #size-cells: Must be <1> for Serial Engine Address Size +- ranges: Must be present + +Properties for children: + +A GENI based QUP wrapper controller node can contain 0 or more child nodes +representing serial devices. These serial devices can be a QCOM UART, I2C +controller, SPI controller, or some combination of aforementioned devices. +Please refer below the child node definitions for the supported serial +interface protocols. + +Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller + +Required properties: +- compatible: Must be "qcom,geni-i2c". +- reg: Must contain QUP register address and length. +- interrupts: Must contain I2C interrupt. +- clock-names: Must contain "se". +- clocks: Serial engine core clock needed by the device. +- #address-cells: Must be <1> for I2C device address. +- #size-cells: Must be <0> as I2C addresses have no size component. + +Optional property: +- clock-frequency: Desired I2C bus clock frequency in Hz. + When missing default to 400000Hz. + +Child nodes should conform to I2C bus binding as described in i2c.txt. + +Qualcomm Technologies Inc. GENI Serial Engine based UART Controller + +Required properties: +- compatible: Must be "qcom,geni-debug-uart". +- reg: Must contain UART register location and length. +- interrupts: Must contain UART core interrupts. +- clock-names: Must contain "se". +- clocks: Serial engine core clock needed by the device. + +Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller + +Required properties: +- compatible: Must contain "qcom,geni-spi". +- reg: Must contain SPI register location and length. +- interrupts: Must contain SPI controller interrupts. +- clock-names: Must contain "se". +- clocks: Serial engine core clock needed by the device. +- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz. +- #address-cells: Must be <1> to define a chip select address on + the SPI bus. +- #size-cells: Must be <0>. + +SPI slave nodes must be children of the SPI master node and conform to SPI bus +binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. + +Example: + geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c0: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0xa94000 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_i2c_5_active>; + pinctrl-1 = <&qup_1_i2c_5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x7000>; + interrupts = ; + clock-names = "se"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_uart_3_active>; + pinctrl-1 = <&qup_1_uart_3_sleep>; + }; + + spi0: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0xa84000 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_spi_2_active>; + pinctrl-1 = <&qup_1_spi_2_sleep>; + spi-max-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <0>; + }; + } -- cgit v1.2.3 From 290fa8d708e08f419b37c7f18445dcf6de5b7e5c Mon Sep 17 00:00:00 2001 From: Mahesh Sivasubramanian Date: Tue, 10 Apr 2018 11:57:24 -0600 Subject: dt-bindings: introduce Command DB for QCOM SoCs Command DB provides information on shared resources like clocks, regulators etc., probed at boot by the remote subsytem and made available in shared memory. Cc: devicetree@vger.kernel.org Signed-off-by: Mahesh Sivasubramanian Signed-off-by: Lina Iyer Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Reviewed-by: Evan Green Signed-off-by: Andy Gross --- .../bindings/reserved-memory/qcom,cmd-db.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt b/Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt new file mode 100644 index 000000000000..68395530c0a5 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt @@ -0,0 +1,37 @@ +Command DB +--------- + +Command DB is a database that provides a mapping between resource key and the +resource address for a system resource managed by a remote processor. The data +is stored in a shared memory region and is loaded by the remote processor. + +Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for +controlling shared resources. Depending on the board configuration the shared +resource properties may change. These properties are dynamically probed by the +remote processor and made available in the shared memory. + +The bindings for Command DB is specified in the reserved-memory section in +devicetree. The devicetree representation of the command DB driver should be: + +Properties: +- compatible: + Usage: required + Value type: + Definition: Should be "qcom,cmd-db" + +- reg: + Usage: required + Value type: + Definition: The register address that points to the actual location of + the Command DB in memory. + +Example: + + reserved-memory { + [...] + reserved-memory@85fe0000 { + reg = <0x0 0x85fe0000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + }; -- cgit v1.2.3 From c808a10435dfb88c379699a2437e3bd8f08e966c Mon Sep 17 00:00:00 2001 From: Amithash Prasad Date: Mon, 26 Mar 2018 17:11:49 -0700 Subject: ARM: dts: aspeed: Add Portwell Neptune machine Initial introduction of Portwell Neptune family equipped with Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a ASPEED ast2500 BMC manufactured by Portwell. Specifically, This adds the neptune platform device tree file including the flash layout used by the neptune machines. Signed-off-by: Amithash Prasad Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b5f978a4cac6..17750cde43ce 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -278,6 +278,7 @@ pine64 Pine64 pixcir PIXCIR MICROELECTRONICS Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA +portwell Portwell Inc. poslab Poslab Technology Co., Ltd. powervr PowerVR (deprecated, use img) probox2 PROBOX2 (by W2COMP Co., Ltd.) -- cgit v1.2.3