From b17879f71c2eb4a10f5a63918819d9d572b23a9a Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Wed, 18 Jun 2008 08:34:39 +1000 Subject: [POWERPC] 4xx: Clear new TLB cache attribute bits in Data Storage vector A recent commit added support for the new 440x6 and 464 cores that have the added WL1, IL1I, IL1D, IL2I, and ILD2 bits for the caching attributes in the TLBs. The new bits were cleared in the finish_tlb_load function, however a similar bit of code was missed in the DataStorage interrupt vector. Signed-off-by: Josh Boyer Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/head_44x.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index c2b9dc4fce5d..22b5d2c459a3 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -368,7 +368,12 @@ interrupt_base: rlwimi r11,r13,0,26,31 /* Insert static perms */ - rlwinm r11,r11,0,20,15 /* Clear U0-U3 */ + /* + * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added + * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see + * include/asm-powerpc/pgtable-ppc32.h for details). + */ + rlwinm r11,r11,0,20,10 /* find the TLB index that caused the fault. It has to be here. */ tlbsx r10, 0, r10 -- cgit v1.2.3 From 65ba6cdc837af9b77354d03987354196ac4eb308 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 18 Jun 2008 16:40:35 +1000 Subject: [POWERPC] Clear sub-page HPTE present bits when demoting page size When we demote a slice from 64k to 4k, and we are about to insert an HPTE for a 4k subpage and we notice that there is an existing 64k HPTE, we first invalidate that HPTE before inserting the new 4k subpage HPTE. Since the bits that encode which hash bucket the old HPTE was in overlap with the bits that encode which of the 16 subpages have HPTEs, we need to clear out the subpage HPTE-present bits before starting to insert HPTEs for the 4k subpages. If we don't do that, we can erroneously think that a subpage already has an HPTE when it doesn't. That in itself wouldn't be such a problem except that when we go to update the HPTE that we think is present on machines with a hypervisor, the hypervisor can tell us that the HPTE we think is there is actually there even though it isn't, which can lead to a process getting stuck in a loop, continually faulting. The reason for the confusion is that the AVPN (abbreviated virtual page number) we are looking for in the HPTE for a 4k subpage can actually match the AVPN in a stale HPTE for another 64k page. For example, the HPTE for the 4k subpage at 0x84000f000 will be in the same hash bucket and have the same AVPN as the HPTE for the 64k page at 0x8400f0000. This fixes the code to clear out the subpage HPTE-present bits. Signed-off-by: Paul Mackerras --- arch/powerpc/mm/hash_low_64.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S index 21d248486479..70f4c833fa32 100644 --- a/arch/powerpc/mm/hash_low_64.S +++ b/arch/powerpc/mm/hash_low_64.S @@ -568,6 +568,10 @@ htab_inval_old_hpte: ld r7,STK_PARM(r9)(r1) /* ssize */ ld r8,STK_PARM(r8)(r1) /* local */ bl .flush_hash_page + /* Clear out _PAGE_HPTE_SUB bits in the new linux PTE */ + lis r0,_PAGE_HPTE_SUB@h + ori r0,r0,_PAGE_HPTE_SUB@l + andc r30,r30,r0 b htab_insert_pte htab_bail_ok: -- cgit v1.2.3