| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-09-07 | agp/intel: Fix cache control for Sandybridge | Zhenyu Wang | |
| Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC, so we need to extend the mask function to respect the new bits. And set cache control to always LLC only by default on Gen6. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> | |||
 |
index : linux-toradex.git | |
| Linux kernel for Apalis, Colibri and Verdin modules | Toradex |
| summaryrefslogtreecommitdiff |