Age | Commit message (Collapse) | Author |
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1. Remove command time out print statement, huge number of
these prints will cause device hang.
2. There is a sys fs interface to identify the number of
time out errors occured for an sdmmc device
Bug 1274359
Reviewed-on: http://git-master/r/232125
(cherry picked from commit 5d3ecf92c7ff03dca180776e245a94d2c3ee5e6c)
Change-Id: I428f4fc60b99142e782514f2f06f66759082de5b
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/233696
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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When DFS is enabled and tuning is run for multiple frequencies, ensure
that tuning settings/flags are maintained indenpendently for each
frequency.
Bug 1238045
Change-Id: Id4bde8d93c89b9e0188948fba37402f3251ff578
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/233344
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Enable tegra_sdhci_get_ro for t114, because we are using
wp gpio for sdmmc
Bug 1288218
Change-Id: I1e0922da98071cd1ec4d03e35c550c472ac60621
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/231443
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Boost emc, sclk clock to 150 MHz for sdmmc
Boosting emc and sclk helps in sdmmc kpi.
Bug 1276208
Bug 1294076
Reviewed-on: http://git-master/r/230090
(cherry picked from commit d916c03439b91bd68c5ad7f4ac2a0c64a29d417c)
Change-Id: I472e009b369fcaa87b3c44e2c49a86bf1d857b18
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/232083
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Removed runtime DPD configuration support from SD driver.
Bug 1191332
Change-Id: I389ca46a302e30556d2823709a46816a582c26e4
Reviewed-on: http://git-master/r/227045
(cherry picked from commit 9ab1ae335d969eeffe5fc6c7f57e4b0a383ce20c)
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/231644
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Set tuning override voltages using dvfs APIs rather than regulators.
During boot, if the minimum override voltage cannot be set, schedule
for retuning.
Bug 1246712
Change-Id: Ie467b4250107c9745d34859ec2a405aa42024186
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/212682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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sdhci RTPM get() is calling before tuning, so corresponding
sdhci RTPM put() should be issued after tuning as well.
Bug 1249832
Change-Id: I47fb448968db7ba889229e51366ace2f60ac1874
Reviewed-on: http://git-master/r/224915
(cherry picked from commit fdb087557256667e4303ae2d0f29b3d2dede1970)
Signed-off-by: rrajk <rrajk@nvidia.com>
Change-Id: Ifa0cc5b98a17177d11f17c6b7ead85ecd611edf8
Reviewed-on: http://git-master/r/228212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Trim value of 0 is also valid and needs to be set explicitly as the
default trim value after reset could be non-zero in some cases.
Bug 1156152
Change-Id: I19148189082368a2bb21450478bcfc566c2e43ca
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/225170
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Boost emc clock to 100 MHz
Enable sclk for sdmmc4 and set 80MHz
Bug 1262190
Change-Id: Ibb5725ab1a65e57da52250c679bce9f41b181db9
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/222371
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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devfreq_init should be called only if the host indicates support for
dynamic frequency scaling by setting MMC_CAP2_FREQ_SCALING flag.
Change-Id: Ifa6c78fba310cafb7644a1cdc8ed9c7fd1784b22
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/219841
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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set device min_freq to 0, It should not be f_min
Bug 1238045
Bug 1044607
Change-Id: Ifc10a4375953e52f6d414beff0ebc09057914d14
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/219437
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Calculate the desired frequencies for eMMC and SDIO if dynamic
frequency scaling is enabled. The algorithm determines the
frequency based on the active and idle loads measured at periodic
intervals.
The dfs stats are exposed through sysfs and the polling interval
and active load threshold values are set as user configurable
options.
Bug 1238045
Bug 1044607
Change-Id: Ic1509b07320608a53c85a2dcee533a3b0b2a9e97
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/219368
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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If CONFIG_MMC_FREQ_SCALING is enabled, register for device frequency
scaling.
Bug 1044607
Change-Id: I6633f61ad3fc2dcd4c468954906b23ce0a3545fe
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/214993
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Execute tuning for multiple frequencies to save the
best tap values at each frequency
Bug 1238045
Bug 1044607
Change-Id: Ia8a74d9a63d73f10470c9675de868f5652cfbb8d
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/208822
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
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Reduced severity of the message informing usage of 512 bytes block size
from pr_warning to pr_info.
Bug 1166542
Change-Id: Ibc49bfad7eb5d70e2baff76af68f0462371489e8
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/195402
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Added the functions to be used for determining the device frequency
when mmc frequency is enabled. An optional callback is added to be
used by the platform drivers for custom algorithms.
Bug 1238045
Bug 1044607
Change-Id: I6ef56ec4dbdf35da4deef1a09536b9f77a1b7a47
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/213619
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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If CONFIG_MMC_FREQ_SCALING is enabled, register for device frequency
scaling.
Bug 1238045
Change-Id: I11bb807a4658246b18fa41b4e59c63271c5c00f0
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/213013
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Added support for dynamic frequency scaling of SD,MMC,SDIO devices.
The device is registered with devfreq framework after enumeration if
CONFIG_MMC_FREQ_SCALING is enabled.
MMC frequency governor is added to dynamically scale the frequency.
The governor doesn't use central polling but schedules a work to poll
the status of the device periodically. Optional callbacks are provided
to have custom algorithms for determining the frequency.
Bug 1238045
Bug 1044607
Change-Id: Ic7f5669c784afa759ad52bf8373011838a76c01c
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/213012
GVS: Gerrit_Virtual_Submit
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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If there is a gap between xfer mode and command register writes, tegra SDMMC
controller can sometimes issue a spurious command before the CMD register is
written. To avoid this, these two registers need to be written together in a
single write operation.
Bug 1263858
Change-Id: I78563dd06e3a601fe0574ddd4b9efcb99459af6b
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/215050
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
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Retry if frequency tuning fails for any tap value. Consider the tap
value as passing if tuning retry is a success.
Bug 1167519
Change-Id: I4bf121ddd5f70134cdc376ca41d37eda82c61ffd
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/212042
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
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Bug 1222606
Bug 1242658
Change-Id: I1f6aeab31d42d953fe73cecacb7a3d117054090c
Signed-off-by: Ken Chang <kenc@nvidia.com>
(cherry picked from commit b00f8fbe8a3ce474d6f64a9aed9ef7f592ea8e77)
Reviewed-on: http://git-master/r/208324
Reviewed-on: http://git-master/r/213886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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In SDR50 mode, it is not required to set the
controller clk to double the requested clk for the platforms
other than T30.
Bug 1249696
Change-Id: I8fc8ec31c3bf99ff604cbcc4eb24f14525c9f6b0
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/209578
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Set clk rate to default clk rate before selecting pll_c
as a clk parent in order to avoid the dvfs failures triggered
during the set parent process.
Change-Id: I9e2af72820689b9e0ea64a612f287ac67f3e5a73
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/208067
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Explicitly Enable FEEDBACK INPUT_IO_CLk for sdmmc
Bug 1239457
Bug 1252268
Change-Id: Ib8de546b6630c7a12c31a90fd9a2465ea604c564
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/202921
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
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It's unnecessary to call HPI enable twice. Remove 1st copy for
code clean-up.
Bug 1251431
Change-Id: I891c9c4f6110e41864edc291d71a9c6a99112641
Signed-off-by: Roger Hsieh <rhsieh@nvidia.com>
Reviewed-on: http://git-master/r/210266
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Enable packed command support for eMMC4.5 devices
Bug 1242730
Change-Id: I6c68c5477cd20b49230ac04f17351de8ff4a3b1d
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/203327
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Enable MMC_CAP_CMD23 for SDMMC
Bug 1242730
Change-Id: Idda40647870dc198ce7105e32d60406404674437
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/206245
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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This reverts commit 24312e84e15f2ead4d372b8678b56349fab27988.
Bug 947965
Bug 1194300
Change-Id: Icf54d83ccb4a92d78bc613117c75344c2979f214
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/194664
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Enable cache control for eMMC4.5 devices.
Bug 1247699
Bug 1238635
Change-Id: Id0ede63599e8c3713fc2b95f0741cbcd1e7086bc
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/203326
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Bug 1241780
Change-Id: I1dd88a0a463fa90908a4a4bfe749fa526eba3689
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/205283
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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This patch supports packed write command of eMMC4.5 devices. Several
writes can be grouped in packed command and all data of the individual
commands can be sent in a single transfer on the bus. Large amounts of
data in one transfer rather than several data of small size are
effective for eMMC write internally. As a result, packed command help
write throughput be improved. The following tables show the results
of packed write.
Type A:
test none | packed
iozone 25.8 | 31
tiotest 27.6 | 31.2
lmdd 31.2 | 35.4
Type B:
test none | packed
iozone 44.1 | 51.1
tiotest 47.9 | 52.5
lmdd 51.6 | 59.2
Type C:
test none | packed
iozone 19.5 | 32
tiotest 19.9 | 34.5
lmdd 22.8 | 40.7
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Reviewed-by: Maya Erez <merez@codeaurora.org>
Reviewed-by: Namjae Jeon <linkinjeon@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit ce39f9d17c14e56ea6772aa84393e6e0cc8499c4)
Bug 1242730
Change-Id: I634389c3daefe7f10c3f8ef0a373f7520923e6c1
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/206219
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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This patch adds packed command feature of eMMC4.5. The maximum number
for packing read (or write) is offered and exception event relevant to
packed command which is used for error handling is enabled. If host
wants to use this feature, MMC_CAP2_PACKED_CMD should be set.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit abd9ac144947d9a604beb763339e2f77ce8bec79)
Bug 1242730
Change-Id: I739489b759f1b3d58e544307c2bed8572c091323
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/206218
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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This patch adds support for large sector size of 4KB by disabling
emulation. This patch passes eMMC DATA_SECTOR_SIZE as the logical
block size during mmc_blk_alloc_req.
In order to use this patch for 4KB sector size, ensure that
USE_NATIVE_SECTOR is enabled, partition table is 4KB sector size
aligned and file system block and sector size are 4KB multiples.
Signed-off-by: Saugata Das <saugata.das@linaro.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit a5075eb94837edde6833fd5e0277fc2370cf8b39)
Bug 1242730
Change-Id: Ie99b9c44dcdd84238e1d518caeac0800e697d2ce
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/206931
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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It's not necessary to start a new request while error handling if
the card was removed.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit 7a81902fa52f2b6f5037e167f74ebb5a41cfc7d1)
Bug 1242730
Change-Id: Ia585664bc4125af9b0f121237f79ed3e5d45c910
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/206930
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Packed command implementation is available in Upstream.
Use Upstream Packed comamnd code.
Bug 1242730
This reverts commit fa3a748000b65ad4854a95761b6067f89f1c4c61.
Change-Id: I807d6911aa20e9fe1664686bf43811bec7d274f5
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/206215
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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move postreset code to reset exit.
Bug 1239457
Change-Id: Icb5f2f3f0dbf8c7d89c3eca7e7df13b71d2db1ce
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/207014
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Added EDP support for eMMC/micro SD
Bug 1160688
Change-Id: Ia333cfb59b555526344bf884c14797f899d02558
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/202566
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Bug 1243631
Change-Id: I915826047b2e20f0ad0a7d75df295c6cbf6e5b0a
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Added data and cmd error prints to debug the system.
Change-Id: Ia98abecc51373cfe1674b074db413187e460786e
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/204140
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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commit ef4d0888bb7e1b963880f086575081c3d39cad2d upstream.
When commit 95a2482 (mmc: sdhci-esdhc-imx: add basic imx6q usdhc
support) works around host version issue on imx6q, it gets the
register address fixup "reg ^= 2" lost for imx25/35/51/53 esdhc.
Thus, the controller version on these SoCs is wrongly identified
as v1 while it's actually v2.
Add the address fixup back and take a different approach to correct
imx6q host version, so that the host version read gets back to work
for all SoCs.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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If "caps2" host capabilities does not indicate support for MMC
HS200, don't allow clock speeds >52MHz. Currently, for MMC, the
clock speed is set to the lesser of the max speed the eMMC module
supports (card->ext_csd.hs_max_dtr) or the max base clock of the
host controller (host->f_max based on BASE_CLK_FREQ in the host
CAPS register). This means that a host controller that doesn't
support HS200 mode but has a base clock of 100MHz and an eMMC module
that supports HS200 speeds will end up using a 100MHz clock.
Signed-off-by: Al Cooper <alcooperx@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit ccb52a00fd3fdea428e29816cbacb0a78090d474)
Change-Id: I2967fcc733b7178bdf54d6f75f65bdff253fc1cc
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/202051
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Current implementation decides the card type exclusively. Even though
eMMC device can support both HS200 and DDR mode, card type will be
set only for HS200. If the host doesn't support HS200 but has DDR
capability, then DDR mode can't be selected.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit 96cf5f02aee8bbeff38824b18b9ec583d687f846)
Change-Id: Id2b9095f8ffe59c520850acd40681a9ef15c3ff9
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/202050
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Set MMC_CAP2_HS200 to enable HS200 mode support.
Increase sdmmc4 base clock frequency of T114 chip to 208MHz.
Bug 1225343
Change-Id: Ica171c8fe093f0c0ab35b4c46c2dcebaecf25134
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/196484
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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For devices that are powered on across suspend, restore the tuned
tap value during resume. In other cases, set the default tap value.
Bug 1237695
Change-Id: I38ba01931267d7e6c79b32a4855b4bb60a1ce003
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/201752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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choose either pll_c or pll_p as the clk source for sdmmc in order to
set a frequency as close as possible to desired clock rate.
Bug 1167519
Change-Id: Ic37b36864762e5abbcc8076e0ca853a0010d30ae
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/196487
Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Adding option to disable all the UHS modes - SDR12, SDR25, SDR50,
DDR50, SDR104, HS200.
Bug 1189241
Change-Id: I673cf5c819cb4c2ec0525f6e47b493ad1a4b7112
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/199931
Reviewed-by: Rama Kandhala <rkandhala@nvidia.com>
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Fix SD Hot Plug Support in LP State, Card detect
tasklet is scheduled to detect sd card.
Bug 1204527
Change-Id: I688a8a4d64eeb880a542cf859eaba48878f66e35
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/192720
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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This reverts commit 69d0daebd926623453c5753c0a5a979811afecab.
Bug 1216065
Bug 1219868
Change-Id: Ia4a2d9c73b05590e120246aa78c7443ee1b67ad0
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/192924
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Tuning and tap value calculation algorithm for high
frequencies(> 82MHz).
Bug 1167519
Change-Id: Iab3b95a573a4c0636ea89522ec51243375469fd5
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/194797
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Adding frequency tuning solution for frequencies
below 82MHz in SDR104 and HS200 mode.
Bug 1189241
Bug 1181574
Change-Id: Iec55f36de850060c71a13b5dd42d815e573c1f1b
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/192114
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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