summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2018-11-06drm/i915/icl: Define Plane Input CSC Coefficient RegistersUma Shankar
2018-11-02drm/i915/fia: FIA registers offset implementation.Anusha Srivatsa
2018-11-02drm/i915: also group device info array helper macros with othersJani Nikula
2018-11-02drm/i915: reorder and reindent the register choosing helper wrappersJani Nikula
2018-11-02drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()Jani Nikula
2018-11-02drm/i915: remove palette_offsets from device info in favor of _PICK()Jani Nikula
2018-11-01drm/i915/icl: Fix DSS_CTL register namesAnusha Srivatsa
2018-11-01drm/i915/icl: WaAllowUMDToModifySamplerModeOscar Mateo
2018-11-01drm/i915/icl: Add WaEnable32PlaneModeRadhakrishna Sripada
2018-11-01drm/i915/icl: Add DSS_CTL RegistersAnusha Srivatsa
2018-11-01drm/i915/icl: Add DSI packet payload/header registersMadhav Chauhan
2018-10-31drm/i915/icl: Fix the macros for DFLEXDPMLE register bitsManasi Navare
2018-10-31drm/i915/dsc: Add slice_row_per_frame in DSC PPS programmingAnusha Srivatsa
2018-10-31drm/i915/icl: Define DSI timeout registersMadhav Chauhan
2018-10-29drm/i915: Move VIDEO_DIP_CTL definitions to their right place.Dhinakaran Pandiyan
2018-10-29drm/i915: Fix VIDEO_DIP_CTL bit shiftsDhinakaran Pandiyan
2018-10-29drm/i915: Define Intel HDCP2.2 registersRamalingam C
2018-10-24drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.Maarten Lankhorst
2018-10-24drm/i915/gen11: Program the chroma upsampler for HDR planes.Maarten Lankhorst
2018-10-24drm/i915/gen11: Program the scalers correctly for planar formats, v3.Maarten Lankhorst
2018-10-23drm/i915/perf: add a parameter to control the size of OA bufferLionel Landwerlin
2018-10-22drm/i915/icl: Define DSI panel programming registersMadhav Chauhan
2018-10-22drm/i915/icl: Define TRANS_CONF register for DSIMadhav Chauhan
2018-10-22drm/i915/icl: Define DSI transcoder timing registersMadhav Chauhan
2018-10-22drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registersMadhav Chauhan
2018-10-22drm/i915/icl: Define TRANS_DSI_FUNC_CONF registerMadhav Chauhan
2018-10-22drm/i915/icl: Add macros for MMIO of DSI transcoder registersMadhav Chauhan
2018-10-16drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar
2018-10-16drm/i915/icl: Introduce new macros to get combophy registersLucas De Marchi
2018-10-16drm/i915/icl: Combine all port/combophy macros at one placeMahesh Kumar
2018-10-16drm/i915/icl: apply Display WA #1178 to fix type C donglesLucas De Marchi
2018-10-15drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCONShashank Sharma
2018-10-09drm/i915/icl:Add Wa_1606682166Anuj Phogat
2018-10-09drm/i915/icl: Add Wa_1406609255Radhakrishna Sripada
2018-10-05drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICLJosé Roberto de Souza
2018-10-02drm/i915: Add plane alpha blending support, v2.Maarten Lankhorst
2018-09-26drm/i915/icl: Define TA_TIMING_PARAM registersMadhav Chauhan
2018-09-26drm/i915/icl: Define data/clock lanes dphy timing registersMadhav Chauhan
2018-09-21drm/i915: Clean up scaler setup, v2.Maarten Lankhorst
2018-09-13drm/i915/skl+: Decode memory bandwidth and parametersMahesh Kumar
2018-09-13drm/i915/bxt: Decode memory bandwidth and parametersMahesh Kumar
2018-09-11drm/i915/icl: Define T_INIT_MASTER registersMadhav Chauhan
2018-09-04drm/i915/icl: Fix context RPCS programmingTvrtko Ursulin
2018-08-28drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engineManasi Navare
2018-08-24drm/i915/icl: implement the tc/legacy HPD {dis,}connect flowsPaulo Zanoni
2018-08-22drm/i915: Rename PLANE_CTL_DECOMPRESSION_ENABLEDhinakaran Pandiyan
2018-08-20drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLLManasi Navare
2018-08-20drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separa...Manasi Navare
2018-08-16drm/i915: remove confusing GPIO vs PCH_GPIOLucas De Marchi
2018-08-16drm/i915: make PCH_GMBUS* definitions private to gvtLucas De Marchi
generated by cgit v1.2.3 (git 2.0.4) at 2024-10-09 08:33:37 +0000