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path: root/drivers/clk/imx
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2022-05-20Revert "clk: imx7d: Remove audio_mclk_root_clk"Philippe Schenker
This reverts commit b576488fa3b5715a1ef3eafc0b1c1d3514345613. As it uses to break audio on i.MX 7 based modules. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2022-05-19Merge remote-tracking branch 'gh-fslc/5.4-2.3.x-imx' into toradex_5.4-2.3.x-imxPhilippe Schenker
2022-05-19Merge tag 'v5.4.193' into update-to-2.3.7__5.4-2.3.x-imxPhilippe Schenker
This is the 5.4.193 stable release Conflicts: arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts drivers/edac/synopsys_edac.c drivers/mmc/host/sdhci-esdhc-imx.c drivers/mmc/host/sdhci.c drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c sound/soc/codecs/msm8916-wcd-analog.c
2022-05-18LF-4020: clk: imx8qxp: Fix elcdif_pll clockRobert Chiras
Move the elcdif_pll clock initialization before the lcd_clk, since the elcdif_clk needs to be initialized ahead of lcd_clk, being its parent. This change fixes issues with the LCD clocks during suspend/resume. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Suggested-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Acked-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> (cherry picked from commit 0668a88908ccc841081b0509d80e0b4f6b5f9a78)
2022-04-15clk: imx7d: Remove audio_mclk_root_clkAbel Vesa
[ Upstream commit eccac77ede3946c90143447cdc785dc16aec4b24 ] The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790), but according to the reference manual, there is no such gate. The CCGR121 belongs to ECSPI2 and it is not shared. Fixes: 8f6d8094b215b57 ("ARM: imx: add imx7d clk tree support") Reported-by: David Wolfe <david.wolfe@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220127141052.1900174-2-abel.vesa@nxp.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-01-27clk: imx8mn: Fix imx8mn_clko1_selsAdam Ford
[ Upstream commit 570727e9acfac1c2330a01dd5e1272e9c3acec08 ] When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fact that the source select for sys_pll1_80m was incorrectly pointing to m7_alt_pll_clk, which doesn't yet exist. According to Rev 3 of the TRM, The imx8mn_clko1_sels also incorrectly references an osc_27m which does not exist, nor does an entry for source select bits 010b. Fix both by inserting a dummy clock into the missing space in the table and renaming the incorrectly name clock with dummy. Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20211117133202.775633-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-11-26clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller
[ Upstream commit 2f9d61869640f732599ec36b984c2b5c46067519 ] The csi_sel mux register is located in the CCM register base and not the CCM_ANALOG register base. So move it to the correct position in code. Otherwise changing the parent of the csi clock can lead to a complete system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely modified. Also remove the SET_RATE_PARENT flag since one possible supply for the csi_sel mux is the system PLL which we don't want to modify. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-1-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-11-10imx7d: set CLK_IS_CRITICAL flag for M4Ming Liu
Set 'CLK_IS_CRITICAL' flag for IMX7D_PLL_SYS_MAIN_240M_CLK so as to let M4 work when some drivers suspend. Related-to: ELB-4064 Signed-off-by: Ming Liu <liu.ming50@gmail.com>
2021-07-15LF-2692: clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg
Since CPU clocks are managed by CPUFREQ, do not enable runtime PM otherwise rpm gets out of status as cpufreq also manages clock states. Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> (cherry picked from commit e28b1ba00636c81fdd607379dc1cec23059c0918) (cherry picked from commit 813a21285eca606aca805f1ac3aabe09e9f4e346)
2021-07-15clk: imx: add mux ops for i.MX8M composite clkPeng Fan
The CORE/BUS root slice has following design, simplied graph: The difference is core not have pre_div block. A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7]. It support target(smart) interface and normal interface. Target interface is exported for programmer easy to configure ccm root. Normal interface is also exported, but we not use it in our driver, because it will introduce more complexity compared with target interface. The normal interface simplified as below: SEL_A GA +--+ +-+ | +->+ +------+ CLK[0-7]--->+ | +-+ | | | | +----v---+ +----+ | +--+ |pre_diva+----> | +---------+ | +--------+ |mux +--+post_div | | +--+ |pre_divb+--->+ | +---------+ | | | +----^---+ +----+ +--->+ | +-+ | | +->+ +------+ +--+ +-+ SEL_B GB The mux in the upper pic is not the target interface MUX, target interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7], you are actually writing SEL_A or SEL_B depends on the internal counter which will also control the internal "mux". The target interface simplified as below which is used by Linux Kernel: CLK[0-7]--->MUX-->Gate-->pre_div-->post_div A requirement of the Target Interface's software is that the target clock source is active, it means when setting SEL_A, the current input clk to SEL_A must be active, same to SEL_B. We touch target interface, but hardware logic actually also need configure normal interface. There will be system hang, when doing the following steps: The initial state: SEL_A/SEL_B are both sourcing from clk0, the internal counter choose SEL_A. 1. switch mux from clk0 to clk1 The hardware logic will choose SEL_B and configure SEL_B to clk1. SEL_A no changed. 2. gate off clk0 Disable clk0, then the input to SEL_A is off. 3. swtich from clk1 to clk2 The hardware logic will choose SEL_A and configure SEL_A to clk2, however the current SEL_A input clk0 is off, the system hang. The solution to fix the issue is in step 1, write twice to target interface MUX, it will make SEL_A/SEL_B both sources from clk1, then no need to care about the state of clk0. And finally system performs well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2021-07-13LF-2692: clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg
Since CPU clocks are managed by CPUFREQ, do not enable runtime PM otherwise rpm gets out of status as cpufreq also manages clock states. Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> (cherry picked from commit e28b1ba00636c81fdd607379dc1cec23059c0918) (cherry picked from commit 813a21285eca606aca805f1ac3aabe09e9f4e346)
2021-07-13clk: imx: add mux ops for i.MX8M composite clkPeng Fan
The CORE/BUS root slice has following design, simplied graph: The difference is core not have pre_div block. A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7]. It support target(smart) interface and normal interface. Target interface is exported for programmer easy to configure ccm root. Normal interface is also exported, but we not use it in our driver, because it will introduce more complexity compared with target interface. The normal interface simplified as below: SEL_A GA +--+ +-+ | +->+ +------+ CLK[0-7]--->+ | +-+ | | | | +----v---+ +----+ | +--+ |pre_diva+----> | +---------+ | +--------+ |mux +--+post_div | | +--+ |pre_divb+--->+ | +---------+ | | | +----^---+ +----+ +--->+ | +-+ | | +->+ +------+ +--+ +-+ SEL_B GB The mux in the upper pic is not the target interface MUX, target interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7], you are actually writing SEL_A or SEL_B depends on the internal counter which will also control the internal "mux". The target interface simplified as below which is used by Linux Kernel: CLK[0-7]--->MUX-->Gate-->pre_div-->post_div A requirement of the Target Interface's software is that the target clock source is active, it means when setting SEL_A, the current input clk to SEL_A must be active, same to SEL_B. We touch target interface, but hardware logic actually also need configure normal interface. There will be system hang, when doing the following steps: The initial state: SEL_A/SEL_B are both sourcing from clk0, the internal counter choose SEL_A. 1. switch mux from clk0 to clk1 The hardware logic will choose SEL_B and configure SEL_B to clk1. SEL_A no changed. 2. gate off clk0 Disable clk0, then the input to SEL_A is off. 3. swtich from clk1 to clk2 The hardware logic will choose SEL_A and configure SEL_A to clk2, however the current SEL_A input clk0 is off, the system hang. The solution to fix the issue is in step 1, write twice to target interface MUX, it will make SEL_A/SEL_B both sources from clk1, then no need to care about the state of clk0. And finally system performs well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2021-05-05Merge commit '28910e01c43d9735f06fddbeaa42df3e112d1b3e' into ↵Marcel Ziswiler
toradex_5.4-2.3.x-imx This basically contains NXP BSP Patch L5.4.70_2.3.2 plus kernel.org v5.4.115 from https://github.com/Freescale/linux-fslc/tree/5.4-2.3.x-imx. Related-to: ELB-3958 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2021-04-27MLK-25333-3 clk: imx8mq: correct one pcie1 ctrl clock selRichard Zhu
Correct one of the imx8mq_pcie1_ctrl_sels, from "sys2_pll_250m" to "sys2_pll_333m". Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 6c34e907db3da694a63dbd44668189f769e686fe) (cherry picked from commit 6c2415175e7bc5cfa8c5e197854b2915c8850c9c) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-04-27MLK-25333-2 clk: imx8mm: remove the parent setting in clock driverRichard Zhu
Since the parent clock setting had been done in dts node. Remove the codes from clock driver. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit b4dd057204f0ba55e5ceea670b475204096e4f6c) (cherry picked from commit f619aad478e3f32c90d7f0293a81ee00f054363e) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-04-27MLK-25915-2 clk: imx: imx8m: correct the pcie aux selsRichard Zhu
The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock, otherwise the sys2_pll_500m. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 0af1467f5c58229c8220d54d38ce9b6152361387) (cherry picked from commit 885518850911ae44a351d15a9c12b6d12c431616) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-04-27MLK-25282-2 clk: imx8mp: remove the pcie phy clockRichard Zhu
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. Remove it from clock driver to clean up codes. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jason Liu <jason.hui.liu@nxp.com> (cherry picked from commit 631360d6ba454aa9180325d73c12523a45946a51) (cherry picked from commit 24e3536f4fdaf173f5c9009619df15b44dd5d7e9) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-01-27clk: clk-imx8qxp: add adc1Philippe Schenker
seems NXP forgot about adc1, add it. Related-to: ELB-2970 Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2021-01-27Revert "MLK-18724-3 clk: imx7d: remove IMX7D_NAND_USDHC_BUS_ROOT_CLK out ↵Marcel Ziswiler
from clks_init_on[]" This reverts commit 04b647fe39e7b1f2ccbcde2e9eccc596b5f2b9da. This fixes eMMC on sdhci3 being defunct just erroring out with -110. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Philippe Schenker <philippe.schenker@toradex.com> (cherry picked from commit 9e64fdc748a31d5dea78f5e66dd3fa3f4c0a935b) Conflicts: drivers/clk/imx/clk-imx7d.c Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-01-27ARM: imx: clk: do not force clock frequency of M4Stefan Agner
Let the M4 handle the clock frequency by itself. We also don't need to take care to make sure clocks stay on, the per domain CCM clock gate control registers can be used to let the CCM know that the M4 runs on that PLL: CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun); Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 98adbbaef78b8a401350a0bf27c3ddc1881ec34d) (cherry picked from commit 00f48e55013560f69b32925c5101e4fcec8fdeb6) Conflicts: drivers/clk/imx/clk-imx7d.c Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-01-27ARM: imx: fix clock for i.MX 7 when Cortex-M4 is runningStefan Agner
Commit b0149f1c7c ("MLK-11620 ARM: imx: single SOC config/compile support") ifdef'd clock functionality for SoloX only if Cortex-M4 is running. However, i.MX 7 also provides a Cortex-M4, hence the true branch in those if statements have been taken. Since the whole block was ifdef'd, the functions were rendered useless for i.MX 7. Fix this by just doing the same thing as if Cortex-M4 is not running. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 7b20ca6cdb752ac4770c2c11e9500b7c1d8bc395) (cherry picked from commit bcdfec99c4d8aee54a5bc1ea706f0fcf4f48523d) (cherry picked from commit 7b8e210373ae86188a1d7e525ef68192cf42f283)
2021-01-11Merge tag 'v5.4.73' into 5.4-2.3.x-imxAndrey Zhizhikin
This is the 5.4.73 stable release Conflicts: - arch/arm/boot/dts/imx6sl.dtsi: Commit [a1767c90194e2] in NXP tree is now covered with commit [5c4c2f437cead] from upstream. - drivers/gpu/drm/mxsfb/mxsfb_drv.c: Resolve merge hunk for patch [ed8b90d303cf0] from upstream - drivers/media/i2c/ov5640.c: Patch [aa4bb8b8838ff] in NXP tree is now covered by patches [79ec0578c7e0a] and [b2f8546056b35] from upstream. Changes from NXP patch [99aa4c8c18984] are covered in upstream version as well. - drivers/net/ethernet/freescale/fec_main.c: Fix merge fuzz for patch [9e70485b40c83] from upstream. - drivers/usb/cdns3/gadget.c: Keep NXP version of the file, upstream version is not compatible. - drivers/usb/dwc3/core.c: - drivers/usb/dwc3/core.h: Fix merge fuzz of patch [08045050c6bd2] together wth NXP patch [b30e41dc1e494] - sound/soc/fsl/fsl_sai.c: - sound/soc/fsl/fsl_sai.h: Commit [2ea70e51eb72a] in NXP tree is now covered with commit [1ad7f52fe6683] from upstream. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2020-11-19MLK-24998-6 clk: imx: remove 2079M rate from imx_pll1443x_tblFancy Fang
Due to commit 82586f0aa1c2 (arm64: dts: imx8mp: correct assigned-clock-rates for video_pll1), so remove unused 2079M clock from imx_pll1443x_tbl. Signed-off-by: Fancy Fang <chen.fang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit b96af227c28b1dfdbdf656de2a77bc4de99136e2)
2020-11-13MLK-24992-01 clk: imx8mp: Change system pll1/pll2 as fixed rate clockJacky Bai
when system running at ND mode, the noc, noc_io & gic clock can be sourced from system PLL1, then system PLL2 will be disable during boot stage. it seems disabling system PLL2 will lead to system hang due to unknow reason. As the system PLL1/PLL2 should be used as fixed rate PLL, so simplify the complexity of clock tree management, change these two PLLs as fixed rate clock. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-11-13MLK-24980 clk: imx8mp: Add audio pll debug monitor on imx8mpJacky Bai
this support is similar as i.MX8MM. for userspace monitor control of the K-divider dynamically, we provide two interfaces to userspace: delta_k & pll_parameter 1): delta_k is used to adjust the K divider in PLL based on small steps; 2): the pll_parameter interface is used for get PLL's current M-divider, P-divider, S-divider & K-divider setting in PLL register example for the usage of these two interfaces: A): Get the current PLL setting of dividers: root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24dd B): if want to adjust the K-divider by a delta_k '1', then echo 0x1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k; root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24de C): if want to adjust the K-divider by a delta_k '-1', then echo -1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k; root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24dc Signed-off-by: Jacky Bai <ping.bai@nxp.com> Tested-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-11-06MLK-24969 clk: imx8mp: Correct the pll table count initJacky Bai
The PLL table count init is missed, then it will lead to pll set rate failure due. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-10-29clk: imx8mq: Fix usdhc parents orderAbel Vesa
[ Upstream commit b159c63d82ff8ffddc6c6f0eb881b113b36ecad7 ] According to the latest RM (see Table 5-1. Clock Root Table), both usdhc root clocks have the parent order as follows: 000 - 25M_REF_CLK 001 - SYSTEM_PLL1_DIV2 010 - SYSTEM_PLL1_CLK 011 - SYSTEM_PLL2_DIV2 100 - SYSTEM_PLL3_CLK 101 - SYSTEM_PLL1_DIV3 110 - AUDIO_PLL2_CLK 111 - SYSTEM_PLL1_DIV8 So the audio_pll2_out and sys3_pll_out have to be swapped. Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reported-by: Cosmin Stefan Stoica <cosmin.stoica@nxp.com> Link: https://lore.kernel.org/r/1602753944-30757-1-git-send-email-abel.vesa@nxp.com Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-27MLK-24922 clk: imx: Add CLK_GET_RATE_NOCACHE flag for dram pll on imx8mqJacky Bai
As the DRAM PLL frequency can be changed during busfreq transition by TF-A on i.MX8MQ, add 'CLK_GET_RATE_NOCACHE' flag for dram pll to make sure linux kernel can get the correct rate of this pll. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-10-20MA-17597 clk: imx8mp: remove __init in imx_clk_init_onJindong
Fix below section mismatch build warnings: The function imx8mp_clocks_probe() references the function __init imx_clk_init_on(). This is often because imx8mp_clocks_probe lacks a __init annotation or the annotation of imx_clk_init_on is wrong. FATAL: modpost: Section mismatches detected. Set CONFIG_SECTION_MISMATCH_WARN_ONLY=y to allow them. Signed-off-by: Jindong <jindong.yue@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-10-01clk: imx: Fix division by zero warning on pfdv2Anson Huang
[ Upstream commit 28b2f82e0383e27476be8a5e13d2aea07ebeb275 ] Fix below division by zero warning: [ 3.176443] Division by zero in kernel. [ 3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124 [ 3.191817] Hardware name: Freescale i.MX7ULP (Device Tree) [ 3.197821] Workqueue: events dbs_work_handler [ 3.202849] [<c01127d8>] (unwind_backtrace) from [<c010cd80>] (show_stack+0x10/0x14) [ 3.211058] [<c010cd80>] (show_stack) from [<c0c77e68>] (dump_stack+0xd8/0x110) [ 3.218820] [<c0c77e68>] (dump_stack) from [<c0c753c0>] (Ldiv0_64+0x8/0x18) [ 3.226263] [<c0c753c0>] (Ldiv0_64) from [<c05984b4>] (clk_pfdv2_set_rate+0x54/0xac) [ 3.234487] [<c05984b4>] (clk_pfdv2_set_rate) from [<c059192c>] (clk_change_rate+0x1a4/0x698) [ 3.243468] [<c059192c>] (clk_change_rate) from [<c0591a08>] (clk_change_rate+0x280/0x698) [ 3.252180] [<c0591a08>] (clk_change_rate) from [<c0591fc0>] (clk_core_set_rate_nolock+0x1a0/0x278) [ 3.261679] [<c0591fc0>] (clk_core_set_rate_nolock) from [<c05920c8>] (clk_set_rate+0x30/0x64) [ 3.270743] [<c05920c8>] (clk_set_rate) from [<c089cb88>] (imx7ulp_set_target+0x184/0x2a4) [ 3.279501] [<c089cb88>] (imx7ulp_set_target) from [<c0896358>] (__cpufreq_driver_target+0x188/0x514) [ 3.289196] [<c0896358>] (__cpufreq_driver_target) from [<c0899b0c>] (od_dbs_update+0x130/0x15c) [ 3.298438] [<c0899b0c>] (od_dbs_update) from [<c089a5d0>] (dbs_work_handler+0x2c/0x5c) [ 3.306914] [<c089a5d0>] (dbs_work_handler) from [<c0156858>] (process_one_work+0x2ac/0x704) [ 3.315826] [<c0156858>] (process_one_work) from [<c0156cdc>] (worker_thread+0x2c/0x574) [ 3.324404] [<c0156cdc>] (worker_thread) from [<c015cfe8>] (kthread+0x134/0x148) [ 3.332278] [<c015cfe8>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) [ 3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8) [ 3.345314] 5fa0: 00000000 00000000 00000000 00000000 [ 3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-09-23MLK-24833-2 clk: imx: scu: add lpi2c4 clock supportClark Wang
add lpi2c4 clock support which exists on MX8QM. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
2020-06-22MLK-24337-8 clk: imx8qxp: Support module buildAnson Huang
Export APIs and add module author, description and license to support module build. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-06-22MLK-24337-7 clk: imx8mq: Support module buildAnson Huang
Add module author, description and license to support module build. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-06-22MLK-24337-6 clk: imx8mp: Support module buildAnson Huang
Add module author, description and license to support module build. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-06-22MLK-24337-5 clk: imx8mn: Support module buildAnson Huang
Add module author, description and license to support module build. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-06-22MLK-24337-4 clk: imx8mm: Support module buildAnson Huang
Add module author, description and license to support module build. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-06-22MLK-24337-3 clk: imx: Support i.MX8 SoCs clock driver to be built as moduleAnson Huang
Export APIs and add module license to support i.MX8 SoCs clock driver to be built as module. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-06-22MLK-24337-2 clk: imx: Support i.MX8X SoCs to be built as moduleAnson Huang
Export APIs to support i.MX8X SoCs clock driver to be built as module. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-06-19Merge tag 'v5.4.47' into imx_5.4.yJason Liu
* tag 'v5.4.47': (2193 commits) Linux 5.4.47 KVM: arm64: Save the host's PtrAuth keys in non-preemptible context KVM: arm64: Synchronize sysreg state on injecting an AArch32 exception ... Conflicts: arch/arm/boot/dts/imx6qdl.dtsi arch/arm/mach-imx/Kconfig arch/arm/mach-imx/common.h arch/arm/mach-imx/suspend-imx6.S arch/arm64/boot/dts/freescale/imx8qxp-mek.dts arch/powerpc/include/asm/cacheflush.h drivers/cpufreq/imx6q-cpufreq.c drivers/dma/imx-sdma.c drivers/edac/synopsys_edac.c drivers/firmware/imx/imx-scu.c drivers/net/ethernet/freescale/fec.h drivers/net/ethernet/freescale/fec_main.c drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c drivers/net/phy/phy_device.c drivers/perf/fsl_imx8_ddr_perf.c drivers/usb/cdns3/gadget.c drivers/usb/dwc3/gadget.c include/uapi/linux/dma-buf.h Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
2020-06-17MLK-24334: clk: imx8mn: add sai7_ipg_clk clock settingsAdrian Alonso
Add sai7_ipg_clk clock settings, fixes use of SAI7 interface on imx8mn SoC. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
2020-06-10MLK-24307-2 clk: imx: clk-gate-shared: enable set parent rateViorel Suman
Enable set parent rate as for usual clock gate. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2020-06-10MLK-24307-1 clk: imx: clk-audiomix: enable set parent rate for ↵Viorel Suman
IMX8MP_CLK_AUDIOMIX_PDM_SEL Enable set parent rate for IMX8MP_CLK_AUDIOMIX_PDM_SEL mux. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2020-06-09clk: imx: clk-audiomix: fix PDM clocksViorel Suman
"pdm_sel" is first 2 bits in base + 0x318 GPR. "pdm_root_clk" has "pdm_sel" as parent. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
2020-06-04MLK-24253: clk: imx: clk-imx8xx-acm: Fix IMX_ADMA_ACM_AUD_CLK1_SELShengjiu Wang
There is a typo, the IMX_ADMA_ACM_AUD_CLK1_CLK should be IMX_ADMA_ACM_AUD_CLK1_SEL. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2020-05-29MLK-24135 clk: imx: Add a temporary workaround for suspend hang casued by ↵Jacky Bai
the EQOS module Keep the EQOS clocks always on to wrokaround the system hang issue when doing suspend/resume stress test. The root cause is still under debug. For now, we just add this workaround to make sure the system suspend/resume function is ok when EQOS is enanble. this workaround will be removed when the root cause is found. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit dd00d1354aebf0f869fdcd80b7df28b4f74ed169)
2020-05-22LF-811-2: clk: imx8qxp: add lcd clocksRobert Chiras
Make lcd_clk a mux from lcd_sels as they are defined in 4.19 tree. Also define the elcdif_pll, since this will be the parent of lcd_clk. Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
2020-05-21MLK-24076-1: clk: imx: acm: Add copyrightShengjiu Wang
Add copyright Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2020-05-22MLK-24064-2: clk: imx8dxl: add clock for lpuart in CM4Alice Guo
Add add clock for lpuart in ARM Cortex-M4 (CM4) Subsystem. Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-10clk: imx: clk-audiomix: Add SAI PLL frequenciesViorel Suman
Add SAI PLL frequencies. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
2020-05-09MLK-23960-1 clk: imx: scu: not attach pd for UART_0 in xen dom0Peng Fan
Since linux itself create clk scu devices which is not available to xen, xen not able to disable this device. However UART_0 device has been occupied by xen. So avoid runtime pd disable this power domain, ignore it for xen dom0. Otherwise system will hang. Acked-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-16 13:45:16 +0000