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2013-04-09ENGR00241003-1 mx6: need to add delay in LDO voltage settingAnson Huang
1.LDO ramp up time may be modified by ROM code according to fuse setting, cpu freq driver use fixed delay time which assume the LDO ramp up time is the reset value of ANATOP register, need to set it to reset value in regulator init. 2.The regulator set voltage should take care of the ramp up time, calculate the ramp up time based of register setting and to the delay, make sure that when the set voltage function return, the voltage is stable enough. 3.CPUFreq no need to use delay, it is already taken care by regulator voltage setting. Signed-off-by: Anson Huang <b20788@freescale.com> Acked-by: Lily Zhang Conflicts: arch/arm/mach-mx6/cpu_regulator-mx6.c arch/arm/mach-mx6/mx6_anatop_regulator.c
2012-09-14Merge commit '3dbe412085dee8e0c378af17fec523221392f565' into imx_3.0.35_androidXinyu Chen
2012-09-12ENGR00223964: CAAM: enable ahash feature in configTerry Lv
Enable ahash feature in mx6q config. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-09-12ENGR00223450 [MX6]Fix secondary cores BogoMIPs errorAnson Huang
After doing some suspend/resuem test, secondary cores BogoMIPs will be wrong, the root cause is that when cpufreq is changed, we only update the online cpus' loops_per_jiffy, and when secondary cores back to online, we skip the loops_per_jiffy calibration. During suspend/resume, the cpufreq can be changed during disabling/enabling secondary cores, which will make secondary cores loops_per_jiffy wrong, so here we need to update all possible cpus' loops_per_jiffy when cpufreq is changed. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-09-07Merge remote branch 'fsl-linux-sdk/imx_3.0.35_12.09.01' into imx_3.0.35_androidXinyu Chen
Conflicts: arch/arm/mach-mx6/pm.c
2012-09-06ENGR00222954 Enable PLL3 in GPU power up flowLoren Huang
If GPU2D used PLL3 as root, we need enable PLL during GPU power up flow so that we can power up GPU2D properly. Till now, this issue can only be duplicated on Android. Signed-off-by: Loren Huang <b02279@freescale.com>
2012-09-06ENGR00223103 ESAI ASRC: clean build warningChen Liangjun
BUILD WARNING: WARNING: arch/arm/mach-mx6/built-in.o(.data+0x7e44): Section mismatch in reference from the variable sab_audio_data to the (unknown reference) .init.rodata:(unknown) The variable sab_audio_data references the (unknown reference) __initconst (unknown) If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console In this patch, remove esai_p2p struct with init attribute. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-09-06ENGR00221719 MX6DQ SABRESD: Add new power key for new sbaresd boardLin Fuzhen
--New sabresd(RevB4 ane above) change the ONOFF key(SW1) design, the SW1 now connect to GPIO_3_29, so map it as the power key, and map SW5 as the volume down key which being mapped to power key for new boards. --Old sabresd such as RevB or older still use SW5 as the power key --Add SOC version check to identify different board revsion. It is the simplest way to achive this before board id/rev are defined clearly. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-09-06ENGR00223226 irq: Disable GPU IRQ trigger for governor to save powerXinyu Chen
This commit resolve the merge error. As PDK's IRQ trigger is enabled, so during merge 3way merge will combine them together, brings redundant codes. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-09-05ENGR00223097 sabresd pfuze:increase VDDARM_IN&VDDSOC_IN to 1.475V for 1.2GRobin Gong
consider ripple, IR drop and pfuze tolerance, we need incrase VDDARM_IN and VDDSOC_IN to 1.475V. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-09-05ENGR00223058 [MX6]Fix build warningAnson Huang
Fix below build warning: arch/arm/mach-mx6/irq.c: In function 'mx6_init_irq': arch/arm/mach-mx6/irq.c:106: warning: unused variable 'reg' arch/arm/mach-mx6/clock_mx6sl.c:1807: warning: function declaration isn't a prototype arch/arm/mach-mx6/clock_mx6sl.c:1535: warning: 'tzasc1_clk' defined but not used arch/arm/mach-mx6/clock_mx6sl.c:1576: warning: 'mx6per2_clk' defined but not used arch/arm/mach-mx6/clock_mx6sl.c:1708: warning: 'ocram_clk' defined but not used Signed-off-by: Anson Huang <b20788@freescale.com>
2012-09-05ENGR00215870-2: board-mx6 sabreauto fix i2c3 pad settingsAdrian Alonso
* Fix i2c3 pad settings, i2c3 conflicts with weim-nor and spi-nor only in rev b target boards. * For rev B targets setup extra pads. * Fix indentation. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-09-05ENGR00215870-1 board-mx6 sabreauto rev B add extra padsAdrian Alonso
* For rev_b target board add extra pads table, separate pad definitions from I2C3 pad array Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-09-05ENGR00222855 MX6 CPUFREQ: support three VDDSOC setpointsRobin Gong
On MX6Q/DL , there is only two set point of VDDSOC/VDDPU, one is 1.25V(1GHz), another is 1.175V. And in arch/arm/plat-mxc/cpufreq.c will judge whether the current cpu frequency is the highest set point(1G) or not to set the right VDDSOC/VDDPU. The logic is also match to dynamic ldo bypass function, since the change point is the highest set point too. But there is three set points of VDDSOC/VDDPU in MX6SL , so the logic in cpufreq.c need to change. Now VDDSOC/VDDPU will track with VDDARM fully. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-09-05ENGR00222835 MX6x-Fix incorrect enabling/disabling of PLL1Ranjani Vaidyanathan
PLL1 was enabled without incrementing the usecount, and was thus not getting disabled under certain conditions. This causes 2 issues: 1. Increases the power. 2. Causes crashes on MX6SL in audio mode as ARM is switched to PLL1 assuming its in bypass when entering WAIT mode. But PLL1 is enabled and not in bypass state. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00222834 MX6x-A9 prefetcher should not access DDR before IO is restoredRanjani Vaidyanathan
Add enough nops to suspend code when exiting due to a pending interrupt. This is required so that we can guarantee that the prefetch unit will not bring DDR out of self-refresh before all of the DDR's IO pads are restored. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00222197 MX6 SabreSD:Set pwm backlight max density to 248Liu Ying
This patch changes pwm backlight max density from 255 to 248 to workaround Hannstar LVDS panel unstable backlight issue when density is set to 250 or 251. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 8747626ca0bcdb6c9525e28d3fbb170db462a299)
2012-09-05ENGR00222157 MX6x-Fix bug in transitioning from low_bus to audio_bus mode.Ranjani Vaidyanathan
Ensure that the transtion from low bus freq mode to audio bus freq mode happens instantly. Don't schedule the delayed work in this case else there will be a pause in the audio playback. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00222257 MX6x-Prime TLB entries before DDR enters self-refresh.Ranjani Vaidyanathan
Need to ensure that no page table walk occurs in DDR when it is in self refresh and its IO pads are floated during suspend. Hence we need to make sure that the translation of all the addresses that the suspend code will access is in the TLB before DDR cannot be accessed anymore. So do a dummy read of IOMUX, MMDC, SRC and ANATOP regsiters. Also need to add a dsb to drain all the write buffers before DDR enters self-refresh. Also ensure that the LDO bypass enable is reset if an interrupt is pending before the system enters suspend. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00222134 MX6x - Fix race-conditions in low power code.Ranjani Vaidyanathan
Fix couple of race-conditions associated with low power IDLE code: 1. Ensure that bus freq mutex is used in the suspend/resume function 2. Ensure that the usecount of pll2 is incremented/decremented when ARM is switched to run from PLL2_PFD_400. And PLL2 is enabled/disabled when necessary. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE supportRanjani Vaidyanathan
Need to ensure that the ARM_CLK rate stays exactly the same when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system enters 24MHz state. Also need to ensure that PLL1 is enabled before relocking the PLL to the correct rate. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00221218: imx6: remove redundant spi defineRobby Cai
There're two imx6q_add_ecspi() defines, remove one. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-09-05ENGR00221975 Fix race condition in clock code.Ranjani Vaidyanathan
Need to ensure that check for usecount in clk_set_parent occurs within the protection of the clock mutex. Else there is a chance that the usecount can be decremented (and the clock disabled) after the check. Also add back the code to maintain the correct usecount for pll2_pfd_400. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00221974 MX6SL-Fix system hang/crash issue in low power IDLERanjani Vaidyanathan
Ensure that the pull-up is enabled when the DQS line of LPDDR2 is floated when DDR freq is dropped to 24MHz. This is required else its possible that the DDR will latch incorrect data when it exits self-refresh. CKE line should not be floated as it may cause DDR to incorrectly exit self-refresh mode. Also add 25 nops after the code that removes DDR from self-refresh. We need this to ensure that the prefetcher block in A9 does not access any instruction from DDR before the DDR exits self-refresh. The A9 prefetch depth is about 23, hence 25 nops. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-05ENGR00221970 MX6SL:Fix suspend/resume issue on MX6SLEVKRanjani Vaidyanathan
Make sure the Pull Ups are enabled on the DQS lines of LPDDR2 memory. Without that its possible that the data latched by the memory will be incorrect when exiting from self-refresh mode. So only set the drive strengths to 0 when floating the DDR IO pads before entering suspend. Also never float the CKE pad, this pin always needs to be driven, else the DDR may incorrectly exit self-refresh. Hence remove the line that was setting CKE drive strength to zero (GRP_CTLDS). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-03ENGR00222197 MX6 SabreSD:Set pwm backlight max density to 248Liu Ying
This patch changes pwm backlight max density from 255 to 248 to workaround Hannstar LVDS panel unstable backlight issue when density is set to 250 or 251. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-08-31ENGR00222076 MX6DQ/DL board:Set LVDS fb default bpp to 16 for AndroidLiu Ying
This patch changes LVDS fb(s) default bpp from 32(BGR32) to 16(RGB565) to align with Hannstar XGA LVDS panel's RGB666 display data color depth. Then, enabling GPU dithering function, we may get better UI quality. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-08-30ENGR00222005 mfgtool can't work on mx6sl evk boardTony LIU
- add imx6s_updater_defconfig to generate mx6sl firmware - add CONFIG_MACH_MX6SL_EVK=y - remove SMP for mx6sl - add CONFIG_MX6_INTER_LDO_BYPASS=y Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-08-30Merge remote branch 'fsl-linux-sdk/imx_3.0.35_12.09.01' into imx_3.0.35_androidXinyu Chen
Conflicts: arch/arm/mach-mx6/board-mx6q_sabresd.c arch/arm/mach-mx6/board-mx6sl_arm2.c arch/arm/mach-mx6/bus_freq.c arch/arm/mach-mx6/cpu_op-mx6.c arch/arm/plat-mxc/cpufreq.c
2012-08-29ENGR00221902 [MX6]Fix udelay inaccurate issue during suspend/resumeAnson Huang
When system enter suspend, we increase CPUFreq to the highest point without update the global loops_per_jiffy, it will lead to udelay inaccurate during the last phase of suspend/resume. WB counter and RBC counter need at least two 32K cycles to finish, here we add 80us for safe. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221867 sabresd : support adjust VDDSOC if enable LDO bypassRobin Gong
support adjust VDDSOC if enable LDO bypass on mx6_sabresd board Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-29ENGR00221716-02 Mx6 USB host: add port speed define MACRO to arc_otg.hmake shi
Add port speed define MACRO to arc_otg.h. Signed-off-by: make shi <b15407@freescale.com>
2012-08-29ENGR00221716-01 Mx6 USB host: set disconnect bit should wait for resume finishedmake shi
For i.MX6DLTO1.1 and i.MX6DQTO1.2, the disconnection-bit can only be set after the resume finished, otherwise, the remote-wake-up may fail. Because if the device not switch to High-Speed 45ohm termination resistors mode, when the disconnection detection bit is set the disconnection detection circuit will detect a high speed disconnection by mistake. Signed-off-by: make shi <b15407@freescale.com>
2012-08-29ENGR00221302 [MX6SL_ARM2/EVK]: VDDSOC adjust if use LDO bypassRobin Gong
The function has been implement in LDO enable , but not in LDO bypass. Implement it on mx6sl. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-29ENGR00221438 [MX6]Adjust CPU setpoint according to datasheetAnson Huang
1. Adjust ARM/SOC/PU voltage according to latest datasheet; 2. Remove Rigel's 200M setpoint to align with Arik. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221643 [MX6]Fix race condition of pfd 400 usecountAnson Huang
We can't modify the usecount of pfd 400M clock when ARM freq is changed, as when the children of pfd 400M do clock enable/disable, they will also modify this usecount, these two modification is out of same lock protection. And this wrong usecount may lead to pfd 400M or pll2 disabled accidently, and it will cause system hang! Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHzLiu Ying
This patch sets PLL3_PFD_540M clock frequency to 540MHz so that IPU and VPU clock can reach 270MHz. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)
2012-08-27ENGR00221438 [MX6]:Remove Rigel's 200M working pointLin Fuzhen
Remove Rigel's 200M working point to align with Arik Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-08-27ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHzLiu Ying
This patch sets PLL3_PFD_540M clock frequency to 540MHz so that IPU and VPU clock can reach 270MHz. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-08-26ENGR00221161 [MX6SL]- Add audio bus freq mode support.Ranjani Vaidyanathan
Set DDR to 50MHz in low power audio playback. AHB/AXI are at 24MHz. Also fix correct usecount for PLL1 main clock. If not it causes issues when pll1_sw_clk's parent is changed. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-26ENGR00221440 MX6x-Fix race-condition in checking bus_freq variablesRanjani Vaidyanathan
Checking of the bus_freq variables and changing of the bus/ddr frequency should be done under one mutex. Else there is a race-condition that the variable changed just after it was checked. Also ensure that the bus freq is always increased before the cpu freq is set to anything other than the lowest setpoint. Else there is a possibility that the ARM is set to run from PLL1 at higher frequency when bus/DDR are still at 24MHz. This is dangerous since when system enters WAIT mode in low bus freq state, PLL1 is set to bypass when ARM is being sourced from it. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-26ENGR00221441 MX6SL - Update voltages based on the latest datasheet.Ranjani Vaidyanathan
Add a new working point table to MX6SL and set the voltages according to the latest datasheet. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-24ENGR00220796-3: imx6sl arm2/evk: Add platform_device for V4L2 supportRobby Cai
Add platform device for V4L2 support Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-24ENGR00221317-02 Mx6 USB host: set stop_mode_config when any USB host enabledmake shi
The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1 is off. So we should keep the 1V1 active during the system suspend if any USB host enabled. - Add stop_mode_config to 1 with refcount - Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register - If stop_mode_config is set as 1, the otg vbus wakeup system will be supported Signed-off-by: make shi <b15407@freescale.com>
2012-08-24ENGR00221317-01 Mx6 USB host: set stop_mode_config when any USB host enabledmake shi
MSL headfile part change. Signed-off-by: make shi <b15407@freescale.com>
2012-08-24ENGR00221277 MX6DL/S - Set AXI clock to 270MHzimx-android-r13.4-betaRanjani Vaidyanathan
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it can run at 270MHz on MX6DL/S. This is required for improving VPU performance. Change AXI_CLK to be sourced from periph_clk just before the DDR freq is going to be dropped to 24MHz/50MHz. Change it back to PLL3_PFD1_540 when the DDR freq is back at 400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-23ENGR00221277 MX6DL/S - Set AXI clock to 270MHzRanjani Vaidyanathan
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it can run at 270MHz on MX6DL/S. This is required for improving VPU performance. Change AXI_CLK to be sourced from periph_clk just before the DDR freq is going to be dropped to 24MHz/50MHz. Change it back to PLL3_PFD1_540 when the DDR freq is back at 400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-23ENGR00221281 [MX6X] Fix BogoMIPS value is not correctNancy Chen
[MX6X] Fix BogoMIPS value is not correct Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-08-23ENGR00221131: imx6sl arm2/evk: add mma8450q accelerometer supportRobby Cai
mma8450q on E-INK DC3 boards, with i2c address 0x1c on I2C1. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-23ENGR00221214 MX6Q/DL SabreSD: avoid pop-noise on audio padsGary Zhang
config audio pads to avoid pop-noise Signed-off-by: Gary Zhang <b13634@freescale.com>
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