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To avoid memory corruption when device is operating at full temperature
QUSE_EXTRA should always be set to 0 for frequencies 150MHz and less.
As extra protection change FBIO_CFG5 to remove the region where there
is TriState on the DQS signals thus preventing false DQS pulses (and
false reads).
(cherry-picked from 2dc075be0e8495654a84a6bc6afa63408e141b02)
Original author: James Wylder <james.wylder@motorola.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I5c711343737edf972251006484ea84661106e0f9
Reviewed-on: http://git-master/r/43401
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Many platforms are derived from ventana and have different types
of memories. Add a separate array for the emc chips being used on
those platforms.
Be default, the array is not populated with any entries. This
disables memory scaling for that device.
BUG 854226
Change-Id: Ic200c980c074ce315880c964f08ce1d5482f6766
Reviewed-on: http://git-master/r/43038
Reviewed-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Tested-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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tegra_get_revision() returned chip minor version but it doesn't identify
A04 chip correctly. Add A04 revision to fix it.
Bug 856439
Change-Id: I7249633dccaa1f15dd275feeeb2c528322f1f47f
Reviewed-on: http://git-master/r/43481
Reviewed-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Tested-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: ChihJen Hsu <chhsu@nvidia.com>
Reviewed-by: Yu-Fong (Foster) Cho <ycho@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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H/W statistics monitor for AVP controls sclk depending on load.
Instead of overriding avp.sclk rate, separate sclk client added
for the statmon so that busy hints from AVP can be handled.
Bug 831892
Reviewed-on: http://git-master/r/36057
(cherry picked from commit a19f85a8a7af722bcfd729297e682574dc22de7b)
Change-Id: I6bd146536b208ed080512cac6f1903188ab240e9
Reviewed-on: http://git-master/r/43030
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Change-Id: I5ca8d77e29382e22c46deee7355e8ab59e6e4154
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/43026
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Tegra series of chips has a hardware statistic counter for CPU/AVP/VDE/SYS
modules. This commit adds support for AVP statistics gathering and
controlling avp clock during video playback.
Bug 831892
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/35647
(cherry picked from commit 145885b03cd9fc625f2ff3460c59ebbb3d93c98e)
Change-Id: Ib9e05c7dbf0b3a9c1a56da64b8b1f6d9edd2dd0a
Reviewed-on: http://git-master/r/42794
Tested-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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enable debugfs clock write by default
bug 847828
Change-Id: Ia58ea86a32d322d77561f9252112e7a0850cd22a
Reviewed-on: http://git-master/r/43193
Tested-by: Ken Chang <kenc@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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At the time of reboot, all rails need to be set to nominal to ensure
the success of subsequent boot
bug 821969
bug 797082
http://git-master/r/#change,42117
(cherry picked from commit 34a922bbf6cad91dd4f5129a1c7ad96f475f34fe)
Change-Id: I5044109866a032dc89d7cd0b83938ecd4b3f360a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/42297
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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below variables should be defined according to power sequence
specifications of panels.
- timing between panel power on to lvds singal enable
- timing between lvds signal enable to backlight enable
bug 818959
Change-Id: Idcc6de22178fa455e6e65ea89bbabd8a5eb9e6d9
Reviewed-on: http://git-master/r/41669
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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If the screen is idle (no POST for some time), reduce the DC EMC clock
according the windows size. If external display connected, the EMC clock
will not be reduced.
BUG 828306
Reviewed-on: http://git-master/r/37106
Change-Id: I88c76ef3afe5036f47d91f6540846fd767c399e4
Reviewed-on: http://git-master/r/38149
Reviewed-by: Xin Xie <xxie@nvidia.com>
Tested-by: Xin Xie <xxie@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Provides clock information for camera use cases to achieve
optimal power saving.
BUG 813159
Reviewed-on: http://git-master/r/31237
(cherry picked from commit 8180aabdb727b171ae9c49fbec991b3983ec87c8)
Change-Id: I19e99d39ff00bf0619d314854ce1b2fff670a8ff
Reviewed-on: http://git-master/r/37955
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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This option adds support for ASIX AX88xxx Based USB 2.0
Ethernet Adapters and it works with TrendNet TU2-ET100 devices.
Bug 834417
Similar change was done by http://git-master/r/35699
Change-Id: Iad0ba1df837db5b560cc3b942d55c6ea83ee34cc
Reviewed-on: http://git-master/r/42116
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Restore the target cpu frequency on exit from suspend. Also save target
frequency if set when the device is suspended.
Bug 841559
Change-Id: Id17a5945215e324d49e3d74b9603cc919a736c64
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-on: http://git-master/r/41710
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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To improve the power consumption situation for MP3 playback
the scaling governor is set to conservative when display
is turned off and the default governor is saved. The governor
is restored when display is turned on.
Bug 817727
Change-Id: I2184b422b6e25504a0fb7d78573c748599256908
Reviewed-on: http://git-master/r/28270
Reviewed-on: http://git-master/r/37936
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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If tagra_dap_port_info_table.dac_port is tegra_das_port_none,
das_set_pin_state() should not control tri-state for the DAP
pingroup.
Bug 824362
Change-Id: Id48945c21c0e383f5b43cc62ccc610af3a0fd2ee
Signed-off-by: Artiste Hsu <chhsu@nvidia.com>
Change-Id: I13bc31f0935547a0446c4e300ed0089042822e26
Reviewed-on: http://git-master/r/41489
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Yu-Fong (Foster) Cho <ycho@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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Set the working voltage for USB to 1.1 v.
Bug 796594
Reviewed-on: http://git-master/r/30219
(cherry picked from commit af08f51a8c51b7b8d3f25ee7a2372f9d423b78e7)
Change-Id: I3a5a97dae925262453e19fc9b597c0d4be5b2ba6
Reviewed-on: http://git-master/r/40684
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Per the 8.4.1 section of HDMI spec version 1.4a, 100KHz is the maximum
clock rate of DDC i2c bus.
Bug 820552
(cherry picked from commit 588d82e5106558e1c218506ea5067f23c3888db6)
Change-Id: Iba08e5ea9c46ab2c50f0716dee950bcc40a9fc4e
Signed-off-by: Haley Teng <hteng@nvidia.com>
Reviewed-on: http://git-master/r/41490
Reviewed-by: ChihJen Hsu <chhsu@nvidia.com>
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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some users might enter fuse data starting
with 0x/x. this will mess up the fuse programming.
do not consider 0x/x while programming the fuses.
also fix some compilation warnings
Change-Id: I5e888a769eb15dbe7eb35ce2d290246fcf9788c9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/38933
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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bug 846277
Change-Id: I6a3eed59ab2a906afea2b55213e0346491c19c58
Reviewed-on: http://git-master/r/40613
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
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3D power gate should be always disabled to keep the power. Set T20
enabled by default.
Bug 843271
Change-Id: I17745e37436414b3d5f905eb01e347743a012830
Reviewed-on: http://git-master/r/40342
Reviewed-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Tested-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: ChihJen Hsu <chhsu@nvidia.com>
Reviewed-by: Yu-Fong (Foster) Cho <ycho@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Change the permission to 644 for 'enable' and 'quantum'
TEGRA_MC_ATTRIBUTES to disable the write permission as
CTS test "android.permission.cts.FileSystemPermissionTes
t#testAllFilesInSysAreNotWritable" requires it as non-writable.
Bug 840411
Reviewed-on: http://git-master/r/36878
(cherry picked from commit 88982e06ac4d0b91828542ec9eaabf6e2c9a03e0)
Change-Id: Ie99ee941d976b08a5b145fafe9160d44ddcb9990
Reviewed-on: http://git-master/r/40797
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com>
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bug 846277
Change-Id: Ib435d07993d9987d6028e783fdce2d1ed68d19ca
Reviewed-on: http://git-master/r/40605
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
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EMC state control register is not programmed correctly as the value
is not reset after previous write is done.
Bug 829087
Change-Id: I6d1db2e605101d248ed08777135cb1a404fb3350
Reviewed-on: http://git-master/r/40230
Tested-by: Liang Cheng (SW) <licheng@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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Revised version of lp0 resume code for link ulpi.
Bug 786136
Change-Id: I6b644a596148ec975d2e74113499358fc115066e
Reviewed-on: http://git-master/r/39113
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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set usb2 phy type to TEGRA_USB_PHY_TYPE_LINK_ULPI
bug 845612
Change-Id: I35ae7a2e3eb6e0666a1b54e5249faad4f77bd299
Reviewed-on: http://git-master/r/39603
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
Reviewed-by: ChihJen Hsu <chhsu@nvidia.com>
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Modified the usb registration order, otg is the first to be registered.
Bug 835678
Change-Id: I709a944a49aa59886f906bd4184e80b35836125c
Reviewed-on: http://git-master/r/39505
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Alex Courbot <acourbot@nvidia.com>
Tested-by: Alex Courbot <acourbot@nvidia.com>
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usb hotplug is supported only for UTMI phy. usb_phy_type should be
carefully checked in ehci irq.
bug 845612
Change-Id: I2fdc7c79b9816dd3465353375448b07f138ff950
Reviewed-on: http://git-master/r/39338
Tested-by: Ken Chang <kenc@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Yu-Fong (Foster) Cho <ycho@nvidia.com>
Reviewed-by: ChihJen Hsu <chhsu@nvidia.com>
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- vdd_core needs to be 1.14V min before fuse
write/read
- add wait_for_idle before accessing fuses
- add proper programming of PRIV2INTFS field
Bug 841766
Change-Id: Ie9ec27bdbc975a4e3ce40a0ce60fe7049f7c2429
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/37618
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Bug 841766
Change-Id: I24e7102f3c2fb17b9f2095cf12feccefbcdf8dce
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/37617
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Andy Carman <acarman@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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keep fuse clock always enabled to allow fuse
read writes from multiple clients
Bug 841766
Change-Id: I01391ff88e1af5d622fe52b8fad30e2dfc02f38c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/38402
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Fix GART lockups caused by fragmentation by evicting
mapped areas from iovm space after unsuccessful array
pinning attempt.
Fix double unpin error happening during interrupted
submit.
Fix possible sleep in atomic context in iovmm code
(semaphore inside spinlock) by replacing spinlock
with mutex.
Fix race between handle_unpin and pin_handle.
bug 838579
bug 838073
bug 818058
bug 844307
Conflicts:
drivers/video/tegra/nvmap/nvmap_mru.c
Change-Id: Ie44fa88510f62ce5c7d31af3b07afdf69a3ad4a6
Reviewed-on: http://git-master/r/38430
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Tested-by: Kirill Artamonov <kartamonov@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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disable_irq() will do schedule() if threaded IRQ handler is running. But
suspend_cpu_complex() is called from IRQ disabled.
disable_irq_nosync() should be used here because it will not sleep.
BUG 841808
Change-Id: I5bc241e607ffb5cad34530185e308a9f9bbc6543
Reviewed-on: http://git-master/r/37505
Reviewed-on: http://git-master/r/38188
Reviewed-by: Xin Xie <xxie@nvidia.com>
Tested-by: Xin Xie <xxie@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Enabling cdev1 clk or DAP Mclk from board file instead of
codec soc file because Mclk needs to be enabled before
codec initialization. Also exposing set_parent() for cdev
clocks so that it is possible to enable them from board
file.
Bug 827709
Bug 839210
Bug 821178
Change-Id: I6e0e15be9f9a2da98ce2ba89e3390bef1e2b93a7
Reviewed-on: http://git-master/r/37631
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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Removed the semicolon after 'if'.
Change-Id: I91df7b367633e269116110b3469c1efcb2589a95
Reviewed-on: http://git-master/r/37459
Tested-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
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MMC_BLOCK_DEFERRED_RESUME causes race conditions in the SD/MMC driver,
i.e. mmc_sd_detect() will be called from different threads causing
inconsistent state. Disabling feature for Tegra.
Bug 833034
Change-Id: I516272a5a0af44ba27122cc0c6476512cf5b617d
Reviewed-on: http://git-master/r/36254
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Bug 820602
Change-Id: I6a5f116cc3c32f58a7404de24a073ddaf2c79227
Reviewed-on: http://git-master/r/35954
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.
This change also removes the workaroud for the bug.
bug 827353
bug 826234
Change-Id: I21876a4d2a8d729def9f43a0f8879e1de3e84dde
Reviewed-on: http://git-master/r/33083
Reviewed-on: http://git-master/r/35355
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 814896, 820602
Change-Id: Ief590e49f995dd1da6502707ac329057a12f4f17
Reviewed-on: http://git-master/r/35948
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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- handle scenarios when the number of fuses burnt
is a odd number
- wait for the fuse bock to be idle before issuing
any command
- burning of master_enb fuse is not required to be
done according to the guidelines
Bug 823552
Change-Id: I04477dcfae610aed3e2072adfc48ebd7212449ad
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/35883
Reviewed-by: Andy Carman <acarman@nvidia.com>
Tested-by: Andy Carman <acarman@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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use FB_BLANK_POWERDOWN on hdmi device in earlysuspend to cause
tegra_dc_disable.
Fixes bug 835171
Change-Id: I112d05f271b9d12319186ff1b9bd2d0e0667a75e
Reviewed-on: http://git-master/r/35412
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Added regulator vmic to use in soc-audio
Reviewed-on: http://git-master/r/33110
(cherry picked from commit 1b5f6d90219d6e3beeaeb2ec286949bc838d9bc4)
Change-Id: Iba33f5bf2bc5243ff13995005d1c182f6d120d55
Reviewed-on: http://git-master/r/35375
Tested-by: Viraj Karandikar <vkarandikar@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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disabling ldo4 kills power to the board completely.
there is no way to power on the board again, other
than reinserting the power plug.
Change-Id: I1e03389cf26ad8de7a5d5fb518f85fa6c9427752
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/35620
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This option adds support for ASIX AX88xxx Based USB 2.0
Ethernet Adapters and it works with TrendNet TU2-ET100 devices.
Bug 834417
Change-Id: I46d3990e72c66b6abc2821b7e70d039718bbf487
Reviewed-on: http://git-master/r/35699
Reviewed-by: Vandana Salve <vsalve@nvidia.com>
Tested-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Extend the wait interface to relay the actual resultant waited
point back.
Reviewed-on: http://git-master/r/23033
(cherry picked from commit bc22c56ecb54ec093262cee4b1105c2503e5497e)
Change-Id: I65224359f85d3f357e48eeacdf76c9bd97056a54
Reviewed-on: http://git-master/r/35919
Reviewed-by: Brian Anderson <branderson@nvidia.com>
Tested-by: Brian Anderson <branderson@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
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Passing card detect gpio polarity through platform data.
This is used in sd cards insertion/removal detection.
Bug 831409
Change-Id: I29c99696daf094d4f04789121ddfb681dccca12a
Reviewed-on: http://git-master/r/33123
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Tested-by: Joseph Lehrer <jlehrer@nvidia.com>
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Hotplug does not work if the regulator is disabled, so keep it enabled
until the device wants to enter lowpower mode.
Change-Id: I5a53a0fb0a7f26ba9f2674bbc65f4650948f6143
Reviewed-on: http://git-master/r/33117
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Change-Id: I6ec62abdaf3a8ec2e59e2a533b36b280d69538e1
Signed-off-by: Ari Hirvonen <ahirvonen@nvidia.com>
Reviewed-on: http://git-master/r/33037
Reviewed-by: Michael I Gold <gold@nvidia.com>
Tested-by: Michael I Gold <gold@nvidia.com>
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Enabling AHB prefetch on USB1, USB2, USB3 controllers,
to improve the USB transfer throughput.
Bug 820602
Change-Id: I4e9e9fa37624cc11f83effd268cdbf31c01f1df7
Reviewed-on: http://git-master/r/30475
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Change-Id: I2dcdfadb44a981cccf583a156be0be093ca5feec
Reviewed-on: http://git-master/r/34229
Reviewed-by: Maria Gutowski <mgutowski@nvidia.com>
Tested-by: Maria Gutowski <mgutowski@nvidia.com>
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this is done so that it's easy to get the emc stats without having to
enable this explicitly when one wants to get the emc stats.
Change-Id: Id6039e8cb4510740182981245453128f406ee00d
Reviewed-on: http://git-master/r/32171
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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