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Change-Id: I318afbe66efa346b71e82413ac6442672cef4d36
Reviewed-on: http://git-master/r/21196
Reviewed-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com>
Tested-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com>
Reviewed-by: Maria Gutowski <mgutowski@nvidia.com>
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Timer ticks aren't properly serviced while a CPU is in LP2 idle.
Although the Tegra LP2 idle code calls hrtimer_peek_ahead_timers,
because no IRQ regs have been saved, update_process_times is not
called, and thus the timer list is not serviced (and neither is
SMP rebalancing, etc.) This can cause significant delays
scheduling timer-based activity, especially on CPU 1 (which is
not servicing most other IRQs).
Colin Cross suggested a patch based on upstream review feedback
that uses clock notifiers to switch to the "broadcast" clock event
source ("timer0" Tegra timer 3) during LP2, which has a real
interrupt handler defined that calls the clock event handler in
IRQ context, allowing timers to be checked.
Change-Id: Ifa3f4ec662f07dc9636e433f278358f75b65d10c
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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Surprise bonus change: Rename tegra_enter_idle to more accurately reflect
what it does.
Change-Id: I1237e1271df693c109b9db8b47421f8a4c3043c3
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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Change-Id: Ieaee455b4e52f232c5b1285756c22bcdc7fdc6b4
Signed-off-by: Colin Cross <ccross@android.com>
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Change-Id: Id02744bcdfc079a6091be2e8a736bcd3a6cc0ba6
Signed-off-by: Colin Cross <ccross@android.com>
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Turn on the cpuidle_device power_specified field
to enable usage of the defined cpuidle_state.power_usage fields
for each state.
Signed-off-by: James Wylder <james.wylder@motorola.com>
Change-Id: Ibca20a937bf4079f61e4b3ae64394d797b4eb287
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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supports clock-gated (LP3) SMP idle mode, and power-gated (LP2) idle
mode when all slave processors are off-line
latency for LP2 idle state is calculated as a 2-sample weighted moving
average, to allow for future variations due to (e.g.) CPU frequency
scaling.
when LP2 is an allowed state (i.e., slave CPUs have been taken off-line),
LP3 will perform an hrtimer peek-ahead; this avoids waiting for the
first processor tick following an LP2 in order to run expired hrtimers
(which was causing a 1 tick delay for most user-space sleeps)
LP2 wakeup time and latency uses a 2ms hard-coded offset to account for
the CPU powergood timeout; this is reasonable for Harmony but should be
un-hardcoded for other platforms.
Change-Id: I75e36dc14341200ba85da7ef2db8a59cc487ecec
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
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