summaryrefslogtreecommitdiff
path: root/arch/arm/mach-shmobile/intc-sh73a0.c
AgeCommit message (Collapse)Author
2013-03-18ARM: shmobile: INTC External IRQ pin driver on sh73a0Magnus Damm
Adjust the sh73a0 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ31. This removes quite a bit of special-case code in intc-sh73a0.c but the number of lines get replaced with platform device information in setup-sh73a0.c. The PFC code is also adjusted to make gpio_to_irq() return the correct interrupt number. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-03-13ARM: shmobile: sh73a0: Remove sh73a0_init_irq_dt()Simon Horman
This is not needed as irq_set_wake is only used for suspend to ram which is not a requirement for bringing up boards using DT. Reported-by: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-25ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DTSimon Horman
This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-25ARM: mach-shmobile: sh73a0 external IRQ wake updateMagnus Damm
Use sh73a0_set_wake() for external IRQ signals on sh73a0. The sh73a0 IRQ hardware for external IRQ pins consists of the INTCA interrupt controller and the GIC together doing their best to limp along. These external IRQ pins are treated as a special case where interrupts need to be managed in both interrupt controllers in parallel. The ->irq_set_wake() callback for the external IRQ pins can be dealt with in the same way as INTCA-only without involving the GIC. So this patch updates the external IRQ pin code for sh73a0 to no longer involve the GIC. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-12irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.hRob Herring
Now that we have GIC moved to drivers/irqchip and all GIC DT init for platforms using irqchip_init, move gic.h and update the remaining includes. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com>
2012-09-22Merge branch 'cleanup/__iomem' into next/cleanupOlof Johansson
__iomem annotation cleanup branch from Arnd. * cleanup/__iomem: (21 commits) net: seeq: use __iomem pointers for MMIO video: da8xx-fb: use __iomem pointers for MMIO scsi: eesox: use __iomem pointers for MMIO serial: ks8695: use __iomem pointers for MMIO input: rpcmouse: use __iomem pointers for MMIO ARM: samsung: use __iomem pointers for MMIO ARM: spear13xx: use __iomem pointers for MMIO ARM: sa1100: use __iomem pointers for MMIO ARM: prima2: use __iomem pointers for MMIO ARM: nomadik: use __iomem pointers for MMIO ARM: msm: use __iomem pointers for MMIO ARM: lpc32xx: use __iomem pointers for MMIO ARM: ks8695: use __iomem pointers for MMIO ARM: ixp4xx: use __iomem pointers for MMIO ARM: iop32x: use __iomem pointers for MMIO ARM: iop13xx: use __iomem pointers for MMIO ARM: integrator: use __iomem pointers for MMIO ARM: imx: use __iomem pointers for MMIO ARM: ebsa110: use __iomem pointers for MMIO ARM: at91: use __iomem pointers for MMIO ... Signed-off-by: Olof Johansson <olof@lixom.net>
2012-09-18ARM: shmobile: use __iomem pointers for MMIOArnd Bergmann
ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. This patch is a bit ugly for shmobile, which is the only platform that just uses integer literals all over the place, but I can't see a better way to do this. Acked-by: Simon Horman <horms@verge.net.au> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: linux-sh@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-08-22ARM: shmobile: sh73a0: fixup RELOC_BASE of intca_irq_pins_descKuninori Morimoto
sh73a0 :: intca_irq_pins_desc irq table had conflict from irq 552 to irq 557 before. But the second controller was simply trampling the first one by way of the -EEXIST case from irq_alloc_desc_at(). But now, we have irqdomain support from 1d6a21b0a672fb29b01ccf397d478e0541e17716 (sh: intc: initial irqdomain support) The irqdomain code has simply tightened down the sanity checks and error path. So, sh73a0 CPU board got some WARNING when booting now. This patch fixup RELOC_BASE to solve this issue. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-03-29Merge tag 'cleanup2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: cleanups of io includes" from Olof Johansson: "Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes, moving some of the oft-repeated macros to a common location and removing a bunch of boiler plate. This is another step closer to a common zImage for multiple platforms." Fix up various fairly trivial conflicts (<mach/io.h> removal vs changes around it, tegra localtimer.o is *still* gone, yadda-yadda). * tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits) ARM: tegra: Include assembler.h in sleep.S to fix build break ARM: pxa: use common IOMEM definition ARM: dma-mapping: convert ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol ARM: __io abuse cleanup ARM: create a common IOMEM definition ARM: iop13xx: fix missing declaration of iop13xx_init_early ARM: fix ioremap/iounmap for !CONFIG_MMU ARM: kill off __mem_pci ARM: remove bunch of now unused mach/io.h files ARM: make mach/io.h include optional ARM: clps711x: remove unneeded include of mach/io.h ARM: dove: add explicit include of dove.h to addr-map.c ARM: at91: add explicit include of hardware.h to uncompressor ARM: ep93xx: clean-up mach/io.h ARM: tegra: clean-up mach/io.h ARM: orion5x: clean-up mach/io.h ARM: davinci: remove unneeded mach/io.h include [media] davinci: remove includes of mach/io.h ARM: OMAP: Remove remaining includes for mach/io.h ARM: msm: clean-up mach/io.h ...
2012-03-29Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds
Pull more ARM updates from Russell King. This got a fair number of conflicts with the <asm/system.h> split, but also with some other sparse-irq and header file include cleanups. They all looked pretty trivial, though. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits) ARM: fix Kconfig warning for HAVE_BPF_JIT ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds ARM: 7349/1: integrator: convert to sparse irqs ARM: 7259/3: net: JIT compiler for packet filters ARM: 7334/1: add jump label support ARM: 7333/2: jump label: detect %c support for ARM ARM: 7338/1: add support for early console output via semihosting ARM: use set_current_blocked() and block_sigmask() ARM: exec: remove redundant set_fs(USER_DS) ARM: 7332/1: extract out code patch function from kprobes ARM: 7331/1: extract out insn generation code from ftrace ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format ARM: 7351/1: ftrace: remove useless memory checks ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path ARM: Versatile Express: add NO_IOPORT ARM: get rid of asm/irq.h in asm/prom.h ARM: 7319/1: Print debug info for SIGBUS in user faults ARM: 7318/1: gic: refactor irq_start assignment ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop ARM: 7315/1: perf: add support for the Cortex-A7 PMU ...
2012-03-13ARM: __io abuse cleanupRob Herring
Several platforms incorrectly use __io() for casting to 'void __iomem *'. This converts all of those uses to use the common IOMEM macro. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-sh@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-01-25ARM: shmobile: remove NR_IRQSRob Herring
Remove NR_IRQS and explicitly include mach/irqs.h as needed. shmobile properly allocates irq_descs for each irqchip, so setting .nr_irqs for each machine is not needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-01-18ARM: mach-shmobile: sh73a0 IRQ sparse alloc fixMagnus Damm
Fix the sh73a0 external IRQ pin code to properly support CONFIG_SPARSE_IRQ=y by allocating IRQ descriptors for the cascaded IRQs associated with external IRQ pins. Without this fix it is impossible to request IRQ0->IRQ31 on the Kota2 board when sparse IRQs are enabled. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-11-05ARM: mach-shmobile: sh73a0 and AG5EVM PINT supportMagnus Damm
Support PINT on sh73a0 and AG5EVM using INTC PINT macros. With this patch applied the AG5EVM ethernet is handled through one of the chained sh73a0 PINT interrupt controllers. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-11-05ARM: mach-shmobile: Use common INTC IRQ code on sh73a0Magnus Damm
Improve IRQ triggering support by making use of the macro INTC_IRQ_PINS_32() for INTCA on sh73a0. Unfortunately it is not as easy as just using the macro as-is, we need to do mask and unmaks in the GIC but configure other bits and ack in INTCA. Update GPIO IRQ mappings while at it. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-06-14ARM: mach-shmobile: sh73a0 gic_arch_extn.irq_set_wake() fixMagnus Damm
Initialize ->irq_set_wake() in gic_arch_extn to unbreak wake up from the KEYSC device on AG5EVM in case of Suspend-to-RAM. Without this patch "echo mem > /sys/power/state" and a key press results in the following message on resume: WARNING: at kernel/irq/manage.c:507 irq_set_irq_wake+0x7c/0xd8() Unbalanced IRQ 103 wake disable Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-01-14ARM: mach-shmobile: fix cpu_base of gic_init() on sh73a0Yoshii Takashi
The latest rmobile-latest doesn't run on ag5evm because of a small mistake on initialization. Though, I don't have any idea to write them smart. anyway, On sh73a0, GIC cpu_base is 0xf0000100 but 0xf0001000. Signed-off-by: Takashi YOSHII <takashi.yoshii.zj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-01-07ARM: mach-shmobile: update for GIC changes.Paul Mundt
This fixes up the SMP support to use the refactored GIC APIs. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-22ARM: mach-shmobile: sh73a0 INTCS supportMagnus Damm
Add INTCS support for the sh73a0 processor. The interrupts on the sh73a0 processor are managed through controllers such as GIC, INTCS and INTCA. The ARM cores use the GIC as primary interrupt controller and the INTCS and INTCA are hanging off the GIC as cascaded interrupt controllers. Peripherals connected both to the GIC and the INTC controllers should if possible only use the GIC. If no GIC connection is available then INTCS and INTCA may be used instead. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>