diff options
Diffstat (limited to 'drivers/phy/freescale/phy-fsl-imx8mq-usb.c')
| -rw-r--r-- | drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 642 |
1 files changed, 641 insertions, 1 deletions
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c index a29b4a6f7c24..2f905616f86c 100644 --- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c +++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c @@ -3,23 +3,30 @@ #include <linux/bitfield.h> #include <linux/clk.h> +#include <linux/debugfs.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_platform.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> +#include <linux/power_supply.h> #include <linux/regulator/consumer.h> #define PHY_CTRL0 0x0 #define PHY_CTRL0_REF_SSP_EN BIT(2) #define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) #define PHY_CTRL0_FSEL_24M 0x2a +#define PHY_CTRL0_FSEL_100M 0x27 +#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) +#define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21) #define PHY_CTRL1 0x4 #define PHY_CTRL1_RESET BIT(0) #define PHY_CTRL1_COMMONONN BIT(1) #define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_DCDENB BIT(17) +#define PHY_CTRL1_CHRGSEL BIT(18) #define PHY_CTRL1_VDATSRCENB0 BIT(19) #define PHY_CTRL1_VDATDETENB0 BIT(20) @@ -27,17 +34,371 @@ #define PHY_CTRL2_TXENABLEN0 BIT(8) #define PHY_CTRL2_OTG_DISABLE BIT(9) +#define PHY_CTRL3 0xc +#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0) +#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15) +#define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15 +#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20) +#define PHY_CTRL3_TXRISE_TUNE_SHIFT 20 +/* 1111: +24% ... 0000: -6% step: 2% */ +#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22) +#define PHY_CTRL3_TXVREF_TUNE_SHIFT 22 +#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29) +#define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29 + +#define PHY_CTRL4 0x10 +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15) +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15 + +#define PHY_CTRL5 0x14 +#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23) +#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22) +#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21) +#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20) +#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0) + #define PHY_CTRL6 0x18 +#define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) #define PHY_CTRL6_ALT_CLK_EN BIT(1) #define PHY_CTRL6_ALT_CLK_SEL BIT(0) +/* PHY control register access */ +#define PHY_CTRL_REG_COUNT_MAX 0x42 +#define PHY_CTRL_REG_OFFSET_MAX 0x201f + +#define PHY_CRCTL 0x30 +#define PHY_CRCTL_DATA_IN_MASK GENMASK(15, 0) +#define PHY_CRCTL_CAP_ADDR BIT(16) +#define PHY_CRCTL_CAP_DATA BIT(17) +#define PHY_CRCTL_CR_WRITE BIT(18) +#define PHY_CRCTL_CR_READ BIT(19) + +#define PHY_CRSR 0x34 +#define PHY_CRSR_DATA_OUT_MASK GENMASK(15, 0) +#define PHY_CRSR_CR_ACK BIT(16) + +#define PHY_STS0 0x40 +#define PHY_STS0_OTGSESSVLD BIT(7) +#define PHY_STS0_CHGDET BIT(4) +#define PHY_STS0_FSVPLUS BIT(3) +#define PHY_STS0_FSVMINUS BIT(2) + +#define PHY_TUNE_DEFAULT 0xffffffff + struct imx8mq_usb_phy { struct phy *phy; struct clk *clk; void __iomem *base; struct regulator *vbus; + struct notifier_block chg_det_nb; + struct power_supply *vbus_power_supply; + enum power_supply_usb_type chg_type; + struct dentry *debugfs; + u16 cr_access_base; + u16 cr_read_count; + u32 pcs_tx_swing_full; + u32 pcs_tx_deemph_3p5db; + u32 tx_vref_tune; + u32 tx_rise_tune; + u32 tx_preemp_amp_tune; + u32 tx_vboost_level; + u32 comp_dis_tune; +}; + +#define IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT 500000 +static int imx8mq_phy_ctrl_reg_addr(struct imx8mq_usb_phy *imx_phy, u16 offset) +{ + void __iomem *cr_ctrl = imx_phy->base + PHY_CRCTL; + void __iomem *cr_sr = imx_phy->base + PHY_CRSR; + struct device *dev = &imx_phy->phy->dev; + int i; + + /* Address Phrase */ + writel(offset, cr_ctrl); + writel(readl(cr_ctrl) | PHY_CRCTL_CAP_ADDR, cr_ctrl); + + /* Wait CRSR[16] == 1 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while (!(readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_addr_err; + + writel(readl(cr_ctrl) & (~PHY_CRCTL_CAP_ADDR), cr_ctrl); + + /* Wait CRSR[16] == 0 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while ((readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_addr_err; + + return 0; + +cr_addr_err: + dev_err(dev, "Failed to address reg 0x%x.\n", offset); + return -EIO; +} + +static int imx8mq_phy_ctrl_reg_read(struct imx8mq_usb_phy *imx_phy, u16 offset) +{ + void __iomem *cr_ctrl = imx_phy->base + PHY_CRCTL; + void __iomem *cr_sr = imx_phy->base + PHY_CRSR; + struct device *dev = &imx_phy->phy->dev; + int val, i; + + /* Address Phrase */ + val = imx8mq_phy_ctrl_reg_addr(imx_phy, offset); + if (val) + return val; + + /* Read Phrase */ + writel(readl(cr_ctrl) | PHY_CRCTL_CR_READ, cr_ctrl); + + /* Wait CRSR[16] == 1 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while (!(readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_read_err; + + val = readl(cr_sr); + writel(val & ~PHY_CRCTL_CR_READ, cr_ctrl); + + /* Wait CRSR[16] == 0 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while (!(readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_read_err; + + return val; + +cr_read_err: + dev_err(dev, "Failed to read reg 0x%x.\n", offset); + return -EIO; +} + +static int imx8mq_phy_ctrl_reg_write(struct imx8mq_usb_phy *imx_phy, + u16 offset, u16 val) +{ + void __iomem *cr_ctrl = imx_phy->base + PHY_CRCTL; + void __iomem *cr_sr = imx_phy->base + PHY_CRSR; + struct device *dev = &imx_phy->phy->dev; + int i, ret; + + /* Address Phrase */ + ret = imx8mq_phy_ctrl_reg_addr(imx_phy, offset); + if (ret) + return ret; + + writel(val, cr_ctrl); + + /* Set cr_cap_data to be 1'b1 */ + writel(readl(cr_ctrl) | PHY_CRCTL_CAP_DATA, cr_ctrl); + /* Wait CRSR[16] == 1 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while (!(readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_write_err; + + /* Clear cr_cap_data to be 1'br0 */ + writel(readl(cr_ctrl) & ~PHY_CRCTL_CAP_DATA, cr_ctrl); + /* Wait CRSR[16] == 0 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while ((readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_write_err; + + /* Set cr_write to be 1'b1 */ + writel(readl(cr_ctrl) | PHY_CRCTL_CR_WRITE, cr_ctrl); + /* Wait CRSR[16] == 1 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while (!(readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_write_err; + + /* Clear cr_write to be 1'br0 */ + writel(readl(cr_ctrl) & ~PHY_CRCTL_CR_WRITE, cr_ctrl); + /* Wait CRSR[16] == 0 */ + i = IMX8M_PHY_DEBUG_PORT_LOOP_TIMEOUT; + while ((readl(cr_sr) & PHY_CRSR_CR_ACK) && i > 0) + i--; + if (i == 0) + goto cr_write_err; + + return 0; + +cr_write_err: + dev_err(dev, "Failed to write reg 0x%x.\n", offset); + + return -EIO; + +} + +static int ctrl_reg_value_show(struct seq_file *s, void *unused) +{ + struct imx8mq_usb_phy *imx_phy = s->private; + u16 i, val, base = imx_phy->cr_access_base; + + for (i = 0; i < imx_phy->cr_read_count; i++) { + val = imx8mq_phy_ctrl_reg_read(imx_phy, base + i); + seq_printf(s, "Control Register 0x%x value is 0x%4x\n", + base + i, val); + } + + return 0; +} + +static int ctrl_reg_value_open(struct inode *inode, struct file *file) +{ + return single_open(file, ctrl_reg_value_show, inode->i_private); +} + +static ssize_t ctrl_reg_value_write(struct file *file, const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct seq_file *s = file->private_data; + struct imx8mq_usb_phy *imx_phy = s->private; + u16 cr_value; + int ret; + + ret = kstrtou16_from_user(ubuf, count, 16, &cr_value); + if (ret) + return ret; + + imx8mq_phy_ctrl_reg_write(imx_phy, imx_phy->cr_access_base, cr_value); + + return count; +} + +static const struct file_operations ctrl_reg_value_fops = { + .open = ctrl_reg_value_open, + .write = ctrl_reg_value_write, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, }; +static void debug_create_files(struct imx8mq_usb_phy *imx_phy) +{ + struct device *dev = &imx_phy->phy->dev; + + imx_phy->debugfs = debugfs_create_dir(dev_name(dev), + phy_debugfs_root); + + debugfs_create_x16("ctrl_reg_base", 0600, imx_phy->debugfs, + &imx_phy->cr_access_base); + debugfs_create_x16("ctrl_reg_count", 0600, imx_phy->debugfs, + &imx_phy->cr_read_count); + debugfs_create_file("ctrl_reg_value", 0600, imx_phy->debugfs, + imx_phy, &ctrl_reg_value_fops); + + imx_phy->cr_access_base = 0; + imx_phy->cr_read_count = 1; +} + +static void debug_remove_files(struct imx8mq_usb_phy *imx_phy) +{ + debugfs_remove_recursive(imx_phy->debugfs); +} + +static void imx8m_get_phy_tuning_data(struct imx8mq_usb_phy *imx_phy) +{ + struct device *dev = imx_phy->phy->dev.parent; + + if (device_property_read_u32(dev, "fsl,phy-tx-vref-tune", + &imx_phy->tx_vref_tune)) + imx_phy->tx_vref_tune = PHY_TUNE_DEFAULT; + + if (device_property_read_u32(dev, "fsl,phy-tx-rise-tune", + &imx_phy->tx_rise_tune)) + imx_phy->tx_rise_tune = PHY_TUNE_DEFAULT; + + if (device_property_read_u32(dev, "fsl,phy-tx-preemp-amp-tune", + &imx_phy->tx_preemp_amp_tune)) + imx_phy->tx_preemp_amp_tune = PHY_TUNE_DEFAULT; + + if (device_property_read_u32(dev, "fsl,phy-tx-vboost-level", + &imx_phy->tx_vboost_level)) + imx_phy->tx_vboost_level = PHY_TUNE_DEFAULT; + + if (device_property_read_u32(dev, "fsl,phy-comp-dis-tune", + &imx_phy->comp_dis_tune)) + imx_phy->comp_dis_tune = PHY_TUNE_DEFAULT; + + if (device_property_read_u32(dev, "fsl,pcs-tx-deemph-3p5db", + &imx_phy->pcs_tx_deemph_3p5db)) + imx_phy->pcs_tx_deemph_3p5db = PHY_TUNE_DEFAULT; + + if (device_property_read_u32(dev, "fsl,phy-pcs-tx-swing-full", + &imx_phy->pcs_tx_swing_full)) + imx_phy->pcs_tx_swing_full = PHY_TUNE_DEFAULT; +} + +static void imx8m_phy_tune(struct imx8mq_usb_phy *imx_phy) +{ + u32 value; + + /* PHY tuning */ + if (imx_phy->pcs_tx_deemph_3p5db != PHY_TUNE_DEFAULT) { + value = readl(imx_phy->base + PHY_CTRL4); + value &= ~PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK; + value |= imx_phy->pcs_tx_deemph_3p5db << + PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT; + writel(value, imx_phy->base + PHY_CTRL4); + } + + if (imx_phy->pcs_tx_swing_full != PHY_TUNE_DEFAULT) { + value = readl(imx_phy->base + PHY_CTRL5); + value &= ~PHY_CTRL5_PCS_TX_SWING_FULL_MASK; + value |= imx_phy->pcs_tx_swing_full; + writel(value, imx_phy->base + PHY_CTRL5); + } + + if ((imx_phy->tx_vref_tune & imx_phy->tx_rise_tune & + imx_phy->tx_preemp_amp_tune & imx_phy->comp_dis_tune & + imx_phy->tx_vboost_level) == PHY_TUNE_DEFAULT) + /* If all are the default values, no need update. */ + return; + + value = readl(imx_phy->base + PHY_CTRL3); + if (imx_phy->tx_vref_tune == PHY_TUNE_DEFAULT) + imx_phy->tx_vref_tune = (value & PHY_CTRL3_TXVREF_TUNE_MASK) >> + PHY_CTRL3_TXVREF_TUNE_SHIFT; + + if (imx_phy->tx_rise_tune == PHY_TUNE_DEFAULT) + imx_phy->tx_rise_tune = (value & PHY_CTRL3_TXRISE_TUNE_MASK) >> + PHY_CTRL3_TXRISE_TUNE_SHIFT; + + if (imx_phy->tx_preemp_amp_tune == PHY_TUNE_DEFAULT) + imx_phy->tx_preemp_amp_tune = (value & PHY_CTRL3_TXPREEMP_TUNE_MASK) >> + PHY_CTRL3_TXPREEMP_TUNE_SHIFT; + + if (imx_phy->comp_dis_tune == PHY_TUNE_DEFAULT) + imx_phy->comp_dis_tune = value & PHY_CTRL3_COMPDISTUNE_MASK; + + if (imx_phy->tx_vboost_level == PHY_TUNE_DEFAULT) + imx_phy->tx_vboost_level = (value & PHY_CTRL3_TX_VBOOST_LEVEL_MASK) >> + PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT; + + value &= ~(PHY_CTRL3_TXVREF_TUNE_MASK | + PHY_CTRL3_TXRISE_TUNE_MASK | + PHY_CTRL3_TXPREEMP_TUNE_MASK | + PHY_CTRL3_COMPDISTUNE_MASK | + PHY_CTRL3_TX_VBOOST_LEVEL_MASK); + value |= imx_phy->tx_vref_tune << PHY_CTRL3_TXVREF_TUNE_SHIFT | + imx_phy->tx_rise_tune << PHY_CTRL3_TXRISE_TUNE_SHIFT | + imx_phy->tx_preemp_amp_tune << PHY_CTRL3_TXPREEMP_TUNE_SHIFT | + imx_phy->tx_vboost_level << PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT | + imx_phy->comp_dis_tune; + + writel(value, imx_phy->base + PHY_CTRL3); +} + static int imx8mq_usb_phy_init(struct phy *phy) { struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy); @@ -51,6 +412,8 @@ static int imx8mq_usb_phy_init(struct phy *phy) value = readl(imx_phy->base + PHY_CTRL0); value |= PHY_CTRL0_REF_SSP_EN; + value &= ~PHY_CTRL0_SSC_RANGE_MASK; + value |= PHY_CTRL0_SSC_RANGE_4003PPM; writel(value, imx_phy->base + PHY_CTRL0); value = readl(imx_phy->base + PHY_CTRL2); @@ -99,24 +462,42 @@ static int imx8mp_usb_phy_init(struct phy *phy) value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); writel(value, imx_phy->base + PHY_CTRL1); + imx8m_phy_tune(imx_phy); + return 0; } static int imx8mq_phy_power_on(struct phy *phy) { struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy); + u32 value; int ret; ret = regulator_enable(imx_phy->vbus); if (ret) return ret; - return clk_prepare_enable(imx_phy->clk); + ret = clk_prepare_enable(imx_phy->clk); + if (ret) + return ret; + + /* Disable rx term override */ + value = readl(imx_phy->base + PHY_CTRL6); + value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + + return 0; } static int imx8mq_phy_power_off(struct phy *phy) { struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy); + u32 value; + + /* Override rx term to be 0 */ + value = readl(imx_phy->base + PHY_CTRL6); + value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); clk_disable_unprepare(imx_phy->clk); regulator_disable(imx_phy->vbus); @@ -124,10 +505,245 @@ static int imx8mq_phy_power_off(struct phy *phy) return 0; } +static int imx8mq_chg_data_contact_det(struct imx8mq_usb_phy *imx_phy) +{ + int i, data_pin_contact_count = 0; + u32 val; + + /* Set DMPULLDOWN<#> = 1'b1 (to enable RDM_DWN) */ + val = readl(imx_phy->base + PHY_CTRL5); + val |= PHY_CTRL5_DMPWD_OVERRIDE_SEL | PHY_CTRL5_DMPWD_OVERRIDE; + writel(val, imx_phy->base + PHY_CTRL5); + + /* Set DPPULLDOWN<#> = 1'b0 */ + val = readl(imx_phy->base + PHY_CTRL5); + val |= PHY_CTRL5_DMPWD_OVERRIDE_SEL | PHY_CTRL5_DMPWD_OVERRIDE; + writel(val, imx_phy->base + PHY_CTRL5); + + /* Enable Data Contact Detect (DCD) per the USB BC 1.2 */ + val = readl(imx_phy->base + PHY_CTRL1); + writel(val | PHY_CTRL1_DCDENB, imx_phy->base + PHY_CTRL1); + + for (i = 0; i < 100; i = i + 1) { + val = readl(imx_phy->base + PHY_STS0); + /* DP is low */ + if (!(val & PHY_STS0_FSVPLUS)) { + if (data_pin_contact_count++ > 5) + /* Data pin makes contact */ + break; + usleep_range(5000, 10000); + } else { + data_pin_contact_count = 0; + usleep_range(5000, 6000); + } + } + + /* Disable DCD after finished data contact check */ + val = readl(imx_phy->base + PHY_CTRL1); + val &= ~PHY_CTRL1_DCDENB; + writel(val, imx_phy->base + PHY_CTRL1); + + if (i == 100) { + dev_err(&imx_phy->phy->dev, + "VBUS is coming from a dedicated power supply.\n"); + + /* disable override before finish */ + val = readl(imx_phy->base + PHY_CTRL5); + val &= ~(PHY_CTRL5_DMPWD_OVERRIDE | PHY_CTRL5_DPPWD_OVERRIDE); + writel(val, imx_phy->base + PHY_CTRL5); + + return -ENXIO; + } + + /* Set DMPULLDOWN<#> to 1'b0 when DCD is completed */ + val = readl(imx_phy->base + PHY_CTRL5); + val &= ~PHY_CTRL5_DMPWD_OVERRIDE_SEL; + val |= PHY_CTRL5_DMPWD_OVERRIDE; + writel(val, imx_phy->base + PHY_CTRL5); + + return 0; +} + +static int imx8mq_chg_primary_detect(struct imx8mq_usb_phy *imx_phy) +{ + u32 val; + + /* VDP_SRC is connected to D+ and IDM_SINK is connected to D- */ + val = readl(imx_phy->base + PHY_CTRL1); + val &= ~PHY_CTRL1_CHRGSEL; + val |= PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0; + writel(val, imx_phy->base + PHY_CTRL1); + + msleep(40); + + /* Check if D- is less than VDAT_REF to determine an SDP per BC 1.2 */ + val = readl(imx_phy->base + PHY_STS0); + if (!(val & PHY_STS0_CHGDET)) { + dev_dbg(&imx_phy->phy->dev, "It is a SDP.\n"); + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_SDP; + } + + return 0; +} + +static int imx8mq_phy_chg_secondary_det(struct imx8mq_usb_phy *imx_phy) +{ + u32 val; + + /* VDM_SRC is connected to D- and IDP_SINK is connected to D+ */ + val = readl(imx_phy->base + PHY_CTRL1); + writel(val | PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 | + PHY_CTRL1_CHRGSEL, imx_phy->base + PHY_CTRL1); + + msleep(40); + + /* + * Per BC 1.2, check voltage of D+: + * DCP: if greater than VDAT_REF; + * CDP: if less than VDAT0_REF. + */ + val = readl(imx_phy->base + PHY_STS0); + if (val & PHY_STS0_CHGDET) { + dev_dbg(&imx_phy->phy->dev, "It is a DCP.\n"); + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_DCP; + } else { + dev_dbg(&imx_phy->phy->dev, "It is a CDP.\n"); + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_CDP; + } + + return 0; +} + +static void imx8mq_phy_disable_chg_det(struct imx8mq_usb_phy *imx_phy) +{ + u32 val; + + val = readl(imx_phy->base + PHY_CTRL5); + val &= ~(PHY_CTRL5_DMPWD_OVERRIDE | PHY_CTRL5_DPPWD_OVERRIDE); + writel(val, imx_phy->base + PHY_CTRL5); + + val = readl(imx_phy->base + PHY_CTRL1); + val &= ~(PHY_CTRL1_DCDENB | PHY_CTRL1_VDATSRCENB0 | + PHY_CTRL1_VDATDETENB0 | PHY_CTRL1_CHRGSEL); + writel(val, imx_phy->base + PHY_CTRL1); +} + +static int imx8mq_phy_charger_detect(struct imx8mq_usb_phy *imx_phy) +{ + struct device *dev = &imx_phy->phy->dev; + struct device_node *np = dev->parent->of_node; + union power_supply_propval propval; + u32 value; + int ret = 0; + + if (!np) + return 0; + + imx_phy->vbus_power_supply = power_supply_get_by_phandle(np, + "vbus-power-supply"); + if (IS_ERR_OR_NULL(imx_phy->vbus_power_supply)) + return 0; + + if (imx_phy->chg_type != POWER_SUPPLY_USB_TYPE_UNKNOWN) + goto put_psy; + + ret = power_supply_get_property(imx_phy->vbus_power_supply, + POWER_SUPPLY_PROP_ONLINE, + &propval); + if (ret || propval.intval == 0) { + dev_err(dev, "failed to get psy online infor\n"); + ret = -EINVAL; + goto put_psy; + } + + /* Check if vbus is valid */ + value = readl(imx_phy->base + PHY_STS0); + if (!(value & PHY_STS0_OTGSESSVLD)) { + dev_err(&imx_phy->phy->dev, "vbus is error\n"); + ret = -EINVAL; + goto put_psy; + } + + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_UNKNOWN; + + ret = imx8mq_chg_data_contact_det(imx_phy); + if (ret) + goto put_psy; + + ret = imx8mq_chg_primary_detect(imx_phy); + if (!ret && imx_phy->chg_type != POWER_SUPPLY_USB_TYPE_SDP) + ret = imx8mq_phy_chg_secondary_det(imx_phy); + + imx8mq_phy_disable_chg_det(imx_phy); + + if (!ret) { + propval.intval = imx_phy->chg_type; + power_supply_set_property(imx_phy->vbus_power_supply, + POWER_SUPPLY_PROP_USB_TYPE, + &propval); + } + +put_psy: + power_supply_put(imx_phy->vbus_power_supply); + + return ret; +} + +static int imx8mq_phy_usb_vbus_notify(struct notifier_block *nb, + unsigned long val, void *v) +{ + struct imx8mq_usb_phy *imx_phy = container_of(nb, struct imx8mq_usb_phy, + chg_det_nb); + struct device *dev = &imx_phy->phy->dev; + struct device_node *np = dev->parent->of_node; + union power_supply_propval propval; + struct power_supply *psy = v; + int ret; + + if (!np) + return NOTIFY_DONE; + + imx_phy->vbus_power_supply = power_supply_get_by_phandle(np, + "vbus-power-supply"); + if (IS_ERR_OR_NULL(imx_phy->vbus_power_supply)) { + dev_err(dev, "failed to get power supply\n"); + return NOTIFY_DONE; + } + + if (val == PSY_EVENT_PROP_CHANGED && psy == imx_phy->vbus_power_supply) { + ret = power_supply_get_property(imx_phy->vbus_power_supply, + POWER_SUPPLY_PROP_ONLINE, + &propval); + if (ret) { + power_supply_put(imx_phy->vbus_power_supply); + dev_err(dev, "failed to get psy online info\n"); + return NOTIFY_DONE; + } + + if (propval.intval == 0) + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_UNKNOWN; + } + power_supply_put(imx_phy->vbus_power_supply); + + return NOTIFY_OK; +} + +static int imx8mq_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy); + + if (mode == PHY_MODE_USB_DEVICE) + return imx8mq_phy_charger_detect(imx_phy); + + return 0; +} + static const struct phy_ops imx8mq_usb_phy_ops = { .init = imx8mq_usb_phy_init, .power_on = imx8mq_phy_power_on, .power_off = imx8mq_phy_power_off, + .set_mode = imx8mq_phy_set_mode, .owner = THIS_MODULE, }; @@ -135,6 +751,7 @@ static const struct phy_ops imx8mp_usb_phy_ops = { .init = imx8mp_usb_phy_init, .power_on = imx8mq_phy_power_on, .power_off = imx8mq_phy_power_off, + .set_mode = imx8mq_phy_set_mode, .owner = THIS_MODULE, }; @@ -181,14 +798,37 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev) return PTR_ERR(imx_phy->vbus); phy_set_drvdata(imx_phy->phy, imx_phy); + platform_set_drvdata(pdev, imx_phy); + + if (device_property_present(dev, "vbus-power-supply")) { + imx_phy->chg_det_nb.notifier_call = imx8mq_phy_usb_vbus_notify; + power_supply_reg_notifier(&imx_phy->chg_det_nb); + } + + imx8m_get_phy_tuning_data(imx_phy); + + debug_create_files(imx_phy); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); return PTR_ERR_OR_ZERO(phy_provider); } +static int imx8mq_usb_phy_remove(struct platform_device *pdev) +{ + struct imx8mq_usb_phy *imx_phy = platform_get_drvdata(pdev); + + if (device_property_present(&pdev->dev, "vbus-power-supply")) + power_supply_unreg_notifier(&imx_phy->chg_det_nb); + + debug_remove_files(imx_phy); + + return 0; +} + static struct platform_driver imx8mq_usb_phy_driver = { .probe = imx8mq_usb_phy_probe, + .remove = imx8mq_usb_phy_remove, .driver = { .name = "imx8mq-usb-phy", .of_match_table = imx8mq_usb_phy_of_match, |