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path: root/drivers/mtd/spi-nor/macronix.c
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Diffstat (limited to 'drivers/mtd/spi-nor/macronix.c')
-rw-r--r--drivers/mtd/spi-nor/macronix.c199
1 files changed, 199 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 27498ed0cc0d..2c6ed978c69b 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -8,6 +8,13 @@
#include "core.h"
+#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */
+#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */
+#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */
+#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
+#define SPINOR_REG_MXIC_SPI_EN 0x0 /* Enable SPI */
+#define SPINOR_OP_OPI_DTR_RD 0xEE /* OPI DTR first read opcode */
+
static int
mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
@@ -32,6 +39,98 @@ static struct spi_nor_fixups mx25l25635_fixups = {
.post_bfpt = mx25l25635_post_bfpt_fixups,
};
+/**
+ * spi_nor_macronix_octal_dtr_enable() - Enable octal DTR on Macronix flashes.
+ * @nor: pointer to a 'struct spi_nor'
+ * @enable: whether to enable Octal DTR or switch back to SPI
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor, bool enable)
+{
+ struct spi_mem_op op;
+ u8 *buf = nor->bouncebuf, i;
+ int ret;
+
+ /* Set/unset the octal and DTR enable bits. */
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ if (enable) {
+ buf[0] = SPINOR_REG_MXIC_OPI_DTR_EN;
+ } else {
+ /*
+ * The register is 1-byte wide, but 1-byte transactions are not
+ * allowed in 8D-8D-8D mode. Since there is no register at the
+ * next location, just initialize the value to 0 and let the
+ * transaction go on.
+ */
+ buf[0] = SPINOR_REG_MXIC_SPI_EN;
+ buf[1] = 0x0;
+ }
+
+ op = (struct spi_mem_op)
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
+ SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
+
+ if (!enable)
+ spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ if (ret)
+ return ret;
+
+ /* Read flash ID to make sure the switch was successful. */
+ op = (struct spi_mem_op)
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
+ SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1),
+ SPI_MEM_OP_DUMMY(enable ? 4 : 0, 1),
+ SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, buf, 1));
+
+ if (enable)
+ spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ if (ret)
+ return ret;
+
+ if (enable) {
+ for (i = 0; i < nor->info->id_len; i++)
+ if (buf[i * 2] != nor->info->id[i])
+ return -EINVAL;
+ } else {
+ if (memcmp(buf, nor->info->id, nor->info->id_len))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void octaflash_default_init(struct spi_nor *nor)
+{
+ nor->params->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
+}
+
+static struct spi_nor_fixups octaflash_fixups = {
+ .default_init = octaflash_default_init,
+};
+
+static void mx25uw51345g_post_sfdp_fixup(struct spi_nor *nor)
+{
+ nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+ spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+ 0, 20, SPINOR_OP_OPI_DTR_RD,
+ SNOR_PROTO_8_8_8_DTR);
+}
+
+static struct spi_nor_fixups mx25uw51345g_fixups = {
+ .default_init = octaflash_default_init,
+ .post_sfdp = mx25uw51345g_post_sfdp_fixup,
+};
+
static const struct flash_info macronix_parts[] = {
/* Macronix */
{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
@@ -87,6 +186,106 @@ static const struct flash_info macronix_parts[] = {
{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { "mx66lm2g45g", INFO(0xc2853c, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66lm1g45g", INFO(0xc2853b, 0, 32 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66lw1g45g", INFO(0xc2863b, 0, 32 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25lm51245g", INFO(0xc2853a, 0, 16 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25lw51245g", INFO(0xc2863a, 0, 16 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25lm25645g", INFO(0xc28539, 0, 8 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25lw25645g", INFO(0xc28639, 0, 8 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66um2g45g", INFO(0xc2803c, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66uw2g345g", INFO(0xc2843c, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66uw2g345gx0", INFO(0xc2943c, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66um1g45g", INFO(0xc2803b, 0, 32 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66um1g45g40", INFO(0xc2808b, 0, 32 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx66uw1g45g", INFO(0xc2813b, 0, 32 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25um51245g", INFO(0xc2803a, 0, 16 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw51245g", INFO(0xc2813a, 0, 16 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw51345g", INFO(0xc2843a, 0, 16 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &mx25uw51345g_fixups },
+ { "mx25um25645g", INFO(0xc28039, 0, 8 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw25645g", INFO(0xc28139, 0, 8 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25um25345g", INFO(0xc28339, 0, 8 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw25345g", INFO(0xc28439, 0, 8 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw12845g", INFO(0xc28138, 0, 4 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw12a45g", INFO(0xc28938, 0, 4 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw12345g", INFO(0xc28438, 0, 4 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw6445g", INFO(0xc28137, 0, 2 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
+ { "mx25uw6345g", INFO(0xc28437, 0, 2 * 1024, 4096,
+ SECT_4K | SPI_NOR_OCTAL_DTR_READ |
+ SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
+ .fixups = &octaflash_fixups },
};
static void macronix_default_init(struct spi_nor *nor)
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-14 13:15:39 +0000