diff options
Diffstat (limited to 'drivers/mailbox/imx-mailbox.c')
-rw-r--r-- | drivers/mailbox/imx-mailbox.c | 379 |
1 files changed, 334 insertions, 45 deletions
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 850d4004c50e..7bea28a03713 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -5,9 +5,11 @@ #include <linux/clk.h> #include <linux/firmware/imx/ipc.h> +#include <linux/firmware/imx/s4.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> +#include <linux/jiffies.h> #include <linux/kernel.h> #include <linux/mailbox_controller.h> #include <linux/module.h> @@ -19,8 +21,13 @@ #define IMX_MU_CHANS 16 /* TX0/RX0/RXDB[0-3] */ #define IMX_MU_SCU_CHANS 6 +/* TX0/RX0 */ +#define IMX_MU_S4_CHANS 2 #define IMX_MU_CHAN_NAME_SIZE 20 +#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) +#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) + enum imx_mu_chan_type { IMX_MU_TYPE_TX, /* Tx */ IMX_MU_TYPE_RX, /* Rx */ @@ -45,7 +52,12 @@ enum imx_mu_xsr { struct imx_sc_rpc_msg_max { struct imx_sc_rpc_msg hdr; - u32 data[7]; + u32 data[30]; +}; + +struct imx_s4_rpc_msg_max { + struct imx_s4_rpc_msg hdr; + u32 data[254]; }; struct imx_mu_con_priv { @@ -59,6 +71,7 @@ struct imx_mu_con_priv { struct imx_mu_priv { struct device *dev; void __iomem *base; + void *msg; spinlock_t xcr_lock; /* control register lock */ struct mbox_controller mbox; @@ -78,11 +91,13 @@ struct imx_mu_priv { enum imx_mu_type { IMX_MU_V1, IMX_MU_V2, + IMX_MU_V2_S4 = BIT(15), }; struct imx_mu_dcfg { int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); + int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); void (*init)(struct imx_mu_priv *priv); enum imx_mu_type type; u32 xTR; /* Transmit Register0 */ @@ -91,18 +106,18 @@ struct imx_mu_dcfg { u32 xCR[4]; /* Control Registers */ }; -#define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) -#define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) -#define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) +#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) +#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) +#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) /* General Purpose Interrupt Enable */ -#define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) +#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) /* Receive Interrupt Enable */ -#define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) +#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) /* Transmit Interrupt Enable */ -#define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) +#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) /* General Purpose Interrupt Request */ -#define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) +#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) @@ -120,6 +135,55 @@ static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) return ioread32(priv->base + offs); } +static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx) +{ + u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT; + u32 status; + u32 can_write; + + dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); + + do { + status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); + can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); + } while (!can_write && time_is_after_jiffies64(timeout_time)); + + if (!can_write) { + dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", + val, idx, status); + return -ETIME; + } + + imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); + + return 0; +} + +static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx) +{ + u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT; + u32 status; + u32 can_read; + + dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); + + do { + status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); + can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); + } while (!can_read && time_is_after_jiffies64(timeout_time)); + + if (!can_read) { + dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", + idx, status); + return -ETIME; + } + + *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); + dev_dbg(priv->dev, "Read %.8x\n", *val); + + return 0; +} + static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) { unsigned long flags; @@ -169,14 +233,32 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv, return 0; } -static int imx_mu_scu_tx(struct imx_mu_priv *priv, - struct imx_mu_con_priv *cp, - void *data) +static int imx_mu_generic_rxdb(struct imx_mu_priv *priv, + struct imx_mu_con_priv *cp) +{ + imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), + priv->dcfg->xSR[IMX_MU_GSR]); + mbox_chan_received_data(cp->chan, NULL); + + return 0; +} + +static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data) { - struct imx_sc_rpc_msg_max *msg = data; u32 *arg = data; int i, ret; u32 xsr; + u32 size, max_size, num_tr; + + if (priv->dcfg->type & IMX_MU_V2_S4) { + size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; + max_size = sizeof(struct imx_s4_rpc_msg_max); + num_tr = 8; + } else { + size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; + max_size = sizeof(struct imx_sc_rpc_msg_max); + num_tr = 4; + } switch (cp->type) { case IMX_MU_TYPE_TX: @@ -185,27 +267,27 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv, * sizeof yields bytes. */ - if (msg->hdr.size > sizeof(*msg) / 4) { + if (size > max_size / 4) { /* * The real message size can be different to - * struct imx_sc_rpc_msg_max size + * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size */ - dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2); + dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2); return -EINVAL; } - for (i = 0; i < 4 && i < msg->hdr.size; i++) - imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4); - for (; i < msg->hdr.size; i++) { + for (i = 0; i < num_tr && i < size; i++) + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); + for (; i < size; i++) { ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], xsr, - xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4), - 0, 100); + xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), + 0, 5 * USEC_PER_SEC); if (ret) { dev_err(priv->dev, "Send data index: %d timeout\n", i); return ret; } - imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4); + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); } imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); @@ -218,38 +300,166 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv, return 0; } -static int imx_mu_scu_rx(struct imx_mu_priv *priv, - struct imx_mu_con_priv *cp) +static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) { - struct imx_sc_rpc_msg_max msg; - u32 *data = (u32 *)&msg; + u32 *data; int i, ret; u32 xsr; + u32 size, max_size; + + data = (u32 *)priv->msg; imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); *data++ = imx_mu_read(priv, priv->dcfg->xRR); - if (msg.hdr.size > sizeof(msg) / 4) { - dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2); + if (priv->dcfg->type & IMX_MU_V2_S4) { + size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; + max_size = sizeof(struct imx_s4_rpc_msg_max); + } else { + size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; + max_size = sizeof(struct imx_sc_rpc_msg_max); + } + + if (size > max_size / 4) { + dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2); return -EINVAL; } - for (i = 1; i < msg.hdr.size; i++) { + for (i = 1; i < size; i++) { ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, - xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100); + xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 5 * USEC_PER_SEC); if (ret) { - dev_err(priv->dev, "timeout read idx %d\n", i); + dev_err(priv->dev, "Send data index: %d timeout, \n", i); return ret; } *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); } imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); - mbox_chan_received_data(cp->chan, (void *)&msg); + mbox_chan_received_data(cp->chan, (void *)priv->msg); + + return 0; +} + +static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, + void *data) +{ + struct imx_sc_rpc_msg_max *msg = data; + u32 *arg = data; + u32 byte_size; + int err; + int i; + + dev_dbg(priv->dev, "Sending message\n"); + + switch (cp->type) { + case IMX_MU_TYPE_TXDB: + byte_size = msg->hdr.size * sizeof(u32); + if (byte_size > sizeof(*msg)) { + /* + * The real message size can be different to + * struct imx_sc_rpc_msg_max size + */ + dev_err(priv->dev, + "Exceed max msg size (%zu) on TX, got: %i\n", + sizeof(*msg), byte_size); + return -EINVAL; + } + + print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4, + data, byte_size, false); + + /* Send first word */ + dev_dbg(priv->dev, "Sending header\n"); + imx_mu_write(priv, *arg++, priv->dcfg->xTR); + + /* Send signaling */ + dev_dbg(priv->dev, "Sending signaling\n"); + imx_mu_xcr_rmw(priv, IMX_MU_GCR, + IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); + + /* Send words to fill the mailbox */ + for (i = 1; i < 4 && i < msg->hdr.size; i++) { + dev_dbg(priv->dev, "Sending word %d\n", i); + imx_mu_write(priv, *arg++, + priv->dcfg->xTR + (i % 4) * 4); + } + + /* Send rest of message waiting for remote read */ + for (; i < msg->hdr.size; i++) { + dev_dbg(priv->dev, "Sending word %d\n", i); + err = imx_mu_tx_waiting_write(priv, *arg++, i); + if (err) { + dev_err(priv->dev, "Timeout tx %d\n", i); + return err; + } + } + + /* Simulate hack for mbox framework */ + tasklet_schedule(&cp->txdb_tasklet); + + break; + default: + dev_warn_ratelimited(priv->dev, + "Send data on wrong channel type: %d\n", + cp->type); + return -EINVAL; + } return 0; } +static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) +{ + struct imx_sc_rpc_msg_max msg; + u32 *data = (u32 *)&msg; + u32 byte_size; + int err = 0; + int i; + + dev_dbg(priv->dev, "Receiving message\n"); + + /* Read header */ + dev_dbg(priv->dev, "Receiving header\n"); + *data++ = imx_mu_read(priv, priv->dcfg->xRR); + byte_size = msg.hdr.size * sizeof(u32); + if (byte_size > sizeof(msg)) { + dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", + sizeof(msg), byte_size); + err = -EINVAL; + goto error; + } + + /* Read message waiting they are written */ + for (i = 1; i < msg.hdr.size; i++) { + dev_dbg(priv->dev, "Receiving word %d\n", i); + err = imx_mu_rx_waiting_read(priv, data++, i); + if (err) { + dev_err(priv->dev, "Timeout rx %d\n", i); + goto error; + } + } + + /* Clear GIP */ + imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), + priv->dcfg->xSR[IMX_MU_GSR]); + + print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4, + &msg, byte_size, false); + + /* send data to client */ + dev_dbg(priv->dev, "Sending message to client\n"); + mbox_chan_received_data(cp->chan, (void *)&msg); + + goto exit; + +error: + mbox_chan_received_data(cp->chan, ERR_PTR(err)); + +exit: + return err; +} + static void imx_mu_txdb_tasklet(unsigned long data) { struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data; @@ -301,16 +511,14 @@ static irqreturn_t imx_mu_isr(int irq, void *p) priv->dcfg->rx(priv, cp); } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && (cp->type == IMX_MU_TYPE_RXDB)) { - imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), - priv->dcfg->xSR[IMX_MU_GSR]); - mbox_chan_received_data(chan, NULL); + priv->dcfg->rxdb(priv, cp); } else { dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); return IRQ_NONE; } if (priv->suspend) - pm_system_wakeup(); + pm_system_irq_wakeup(priv->irq); return IRQ_HANDLED; } @@ -399,8 +607,8 @@ static const struct mbox_chan_ops imx_mu_ops = { .shutdown = imx_mu_shutdown, }; -static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox, - const struct of_phandle_args *sp) +static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) { u32 type, idx, chan; @@ -457,6 +665,28 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, return &mbox->chans[chan]; } +static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + u32 type; + + if (sp->args_count < 1) { + dev_err(mbox->dev, "Invalid argument count %d\n", + sp->args_count); + return ERR_PTR(-EINVAL); + } + + type = sp->args[0]; /* channel type */ + + /* Only supports TXDB and RXDB */ + if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) { + dev_err(mbox->dev, "Invalid type: %d\n", type); + return ERR_PTR(-EINVAL); + } + + return imx_mu_xlate(mbox, sp); +} + static void imx_mu_init_generic(struct imx_mu_priv *priv) { unsigned int i; @@ -483,11 +713,12 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) imx_mu_write(priv, 0, priv->dcfg->xCR[i]); } -static void imx_mu_init_scu(struct imx_mu_priv *priv) +static void imx_mu_init_specific(struct imx_mu_priv *priv) { unsigned int i; + int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; - for (i = 0; i < IMX_MU_SCU_CHANS; i++) { + for (i = 0; i < num_chans; i++) { struct imx_mu_con_priv *cp = &priv->con_priv[i]; cp->idx = i < 2 ? 0 : i - 2; @@ -498,14 +729,20 @@ static void imx_mu_init_scu(struct imx_mu_priv *priv) "imx_mu_chan[%i-%i]", cp->type, cp->idx); } - priv->mbox.num_chans = IMX_MU_SCU_CHANS; - priv->mbox.of_xlate = imx_mu_scu_xlate; + priv->mbox.num_chans = num_chans; + priv->mbox.of_xlate = imx_mu_specific_xlate; /* Set default MU configuration */ for (i = 0; i < IMX_MU_xCR_MAX; i++) imx_mu_write(priv, 0, priv->dcfg->xCR[i]); } +static void imx_mu_init_seco(struct imx_mu_priv *priv) +{ + imx_mu_init_generic(priv); + priv->mbox.of_xlate = imx_mu_seco_xlate; +} + static int imx_mu_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -513,6 +750,7 @@ static int imx_mu_probe(struct platform_device *pdev) struct imx_mu_priv *priv; const struct imx_mu_dcfg *dcfg; int ret; + u32 size; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -533,6 +771,15 @@ static int imx_mu_probe(struct platform_device *pdev) return -EINVAL; priv->dcfg = dcfg; + if (priv->dcfg->type & IMX_MU_V2_S4) + size = sizeof(struct imx_s4_rpc_msg_max); + else + size = sizeof(struct imx_sc_rpc_msg_max); + + priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); + if (IS_ERR(priv->msg)) + return PTR_ERR(priv->msg); + priv->clk = devm_clk_get(dev, NULL); if (IS_ERR(priv->clk)) { if (PTR_ERR(priv->clk) != -ENOENT) @@ -600,6 +847,7 @@ static int imx_mu_remove(struct platform_device *pdev) static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { .tx = imx_mu_generic_tx, .rx = imx_mu_generic_rx, + .rxdb = imx_mu_generic_rxdb, .init = imx_mu_init_generic, .xTR = 0x0, .xRR = 0x10, @@ -610,6 +858,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { .tx = imx_mu_generic_tx, .rx = imx_mu_generic_rx, + .rxdb = imx_mu_generic_rxdb, .init = imx_mu_init_generic, .xTR = 0x20, .xRR = 0x40, @@ -620,7 +869,9 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { .tx = imx_mu_generic_tx, .rx = imx_mu_generic_rx, + .rxdb = imx_mu_generic_rxdb, .init = imx_mu_init_generic, + .rxdb = imx_mu_generic_rxdb, .type = IMX_MU_V2, .xTR = 0x200, .xRR = 0x280, @@ -628,10 +879,33 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { .xCR = {0x110, 0x114, 0x120, 0x128}, }; +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { + .tx = imx_mu_specific_tx, + .rx = imx_mu_specific_rx, + .init = imx_mu_init_specific, + .type = IMX_MU_V2 | IMX_MU_V2_S4, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { - .tx = imx_mu_scu_tx, - .rx = imx_mu_scu_rx, - .init = imx_mu_init_scu, + .tx = imx_mu_specific_tx, + .rx = imx_mu_specific_rx, + .init = imx_mu_init_specific, + .rxdb = imx_mu_generic_rxdb, + .xTR = 0x0, + .xRR = 0x10, + .xSR = {0x20, 0x20, 0x20, 0x20}, + .xCR = {0x24, 0x24, 0x24, 0x24}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = { + .tx = imx_mu_seco_tx, + .rx = imx_mu_generic_rx, + .rxdb = imx_mu_seco_rxdb, + .init = imx_mu_init_seco, .xTR = 0x0, .xRR = 0x10, .xSR = {0x20, 0x20, 0x20, 0x20}, @@ -642,7 +916,9 @@ static const struct of_device_id imx_mu_dt_ids[] = { { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, + { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, + { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco }, { }, }; MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); @@ -722,7 +998,20 @@ static struct platform_driver imx_mu_driver = { .pm = &imx_mu_pm_ops, }, }; -module_platform_driver(imx_mu_driver); +static int __init imx_mu_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_mu_driver); + if (ret) + pr_err("Unable to initialize mu driver\n"); + else + pr_info("imx mu driver is registered.\n"); + + return ret; +} + +arch_initcall(imx_mu_init); MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); MODULE_DESCRIPTION("Message Unit driver for i.MX"); |