diff options
Diffstat (limited to 'arch/powerpc')
120 files changed, 4555 insertions, 195 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 757175ccf53c..e1a50e4a7725 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -323,7 +323,7 @@ config ARCH_HIBERNATION_POSSIBLE config ARCH_SUSPEND_POSSIBLE def_bool y depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ - (PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \ + FSL_SOC_BOOKE || PPC_86xx || PPC_PSERIES \ || 44x || 40x config ARCH_SUSPEND_NONZERO_CPU @@ -979,8 +979,6 @@ config FSL_PCI config FSL_PMC bool - default y - depends on SUSPEND && (PPC_85xx || PPC_86xx) help Freescale MPC85xx/MPC86xx power management controller support (suspend/resume). For MPC83xx see platforms/83xx/suspend.c diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 9f73fb6b1cc9..db5a323ed06c 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -351,6 +351,31 @@ corenet64_smp_defconfig: $(call merge_into_defconfig,corenet_basic_defconfig,\ 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw dpaa) +PHONY += corenet32_smp_sdk_defconfig +corenet32_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw sdk_dpaa) + +PHONY += corenet32_fmanv3l_smp_sdk_defconfig +corenet32_fmanv3l_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3l) + +PHONY += corenet64_smp_sdk_defconfig +corenet64_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa) + +PHONY += corenet64_fmanv3l_smp_sdk_defconfig +corenet64_fmanv3l_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3l) + +PHONY += corenet64_fmanv3h_smp_sdk_defconfig +corenet64_fmanv3h_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_basic_defconfig,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3h) + PHONY += mpc86xx_defconfig mpc86xx_defconfig: $(call merge_into_defconfig,mpc86xx_basic_defconfig,\ diff --git a/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts b/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts new file mode 100644 index 000000000000..974838fdf86b --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "b4420qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts b/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts new file mode 100644 index 000000000000..d708f9b85997 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "b4860qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi index 41935709ebe8..fba40a1bccc0 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi @@ -199,6 +199,10 @@ /include/ "pq3-dma-0.dtsi" /include/ "pq3-etsec1-0.dtsi" + enet0: ethernet@24000 { + fsl,wake-on-filer; + fsl,pmc-handle = <&etsec1_clk>; + }; /include/ "pq3-etsec1-timer-0.dtsi" usb@22000 { @@ -222,9 +226,10 @@ }; /include/ "pq3-etsec1-2.dtsi" - - ethernet@26000 { + enet2: ethernet@26000 { cell-index = <1>; + fsl,wake-on-filer; + fsl,pmc-handle = <&etsec3_clk>; }; usb@2b000 { @@ -249,4 +254,9 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" + power@e0070 { + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; + }; }; diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi index b68eb119faef..ea7416af7ee3 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi @@ -188,4 +188,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi index 579d76cb8e32..dddb7374508d 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi @@ -156,4 +156,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi index 49294cf36b4e..40a6cff77032 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi @@ -193,4 +193,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts b/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts index 3a94acbb3c03..ce3346d77858 100644 --- a/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts +++ b/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts @@ -29,3 +29,19 @@ }; /include/ "p1010si-post.dtsi" + +&pci0 { + pcie@0 { + interrupt-map = < + /* IDSEL 0x0 */ + /* + *irq[4:5] are active-high + *irq[6:7] are active-low + */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts b/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts index 4cf255fedc96..83590354f9a0 100644 --- a/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts +++ b/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts @@ -56,3 +56,19 @@ }; /include/ "p1010si-post.dtsi" + +&pci0 { + pcie@0 { + interrupt-map = < + /* IDSEL 0x0 */ + /* + *irq[4:5] are active-high + *irq[6:7] are active-low + */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi b/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi index 2ca9cee2ddeb..ef49a7d6c69d 100644 --- a/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi @@ -215,19 +215,3 @@ phy-connection-type = "sgmii"; }; }; - -&pci0 { - pcie@0 { - interrupt-map = < - /* IDSEL 0x0 */ - /* - *irq[4:5] are active-high - *irq[6:7] are active-low - */ - 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 - 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 - 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 - 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 - >; - }; -}; diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi index 9716a0484ecf..63a7493b924f 100644 --- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi @@ -181,6 +181,8 @@ /include/ "pq3-etsec2-0.dtsi" enet0: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; + queue-group@b0000 { fsl,rx-bit-map = <0xff>; fsl,tx-bit-map = <0xff>; @@ -189,6 +191,8 @@ /include/ "pq3-etsec2-1.dtsi" enet1: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; + queue-group@b1000 { fsl,rx-bit-map = <0xff>; fsl,tx-bit-map = <0xff>; @@ -197,6 +201,8 @@ /include/ "pq3-etsec2-2.dtsi" enet2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; + queue-group@b2000 { fsl,rx-bit-map = <0xff>; fsl,tx-bit-map = <0xff>; @@ -209,4 +215,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi index 642dc3a83d0e..cc4c7461003b 100644 --- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi @@ -163,14 +163,17 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; }; /include/ "pq3-etsec2-2.dtsi" enet2: enet2_grp2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; }; global-utilities@e0000 { @@ -178,6 +181,8 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; /include/ "pq3-etsec2-grp2-0.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi index 407cb5fd0f5b..378195db9fca 100644 --- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi @@ -159,14 +159,17 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; }; /include/ "pq3-etsec2-2.dtsi" enet2: enet2_grp2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; }; global-utilities@e0000 { @@ -174,6 +177,8 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; &qe { diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi index 5f51b7bfc064..6ac21e81344a 100644 --- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi @@ -225,11 +225,13 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { fsl,wake-on-filer; + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { fsl,wake-on-filer; + fsl,pmc-handle = <&etsec2_clk>; }; global-utilities@e0000 { @@ -238,9 +240,10 @@ fsl,has-rstcr; }; - power@e0070{ - compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; - reg = <0xe0070 0x20>; +/include/ "pq3-power.dtsi" + power@e0070 { + compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc", + "fsl,mpc8548-pmc"; }; }; diff --git a/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts new file mode 100644 index 000000000000..85ccbfc9dc89 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p1023rdb.dts" + +&soc { + fman0: fman@100000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + compatible = "fsl,fman", "simple-bus"; + ranges = <0 0x100000 0x100000>; + reg = <0x100000 0x100000>; + clock-frequency = <0>; + interrupts = < + 24 2 0 0 + 16 2 0 0>; + cc@0 { + compatible = "fsl,fman-cc"; + }; + muram@0 { + compatible = "fsl,fman-muram"; + reg = <0x0 0x10000>; + }; + bmi@80000 { + compatible = "fsl,fman-bmi"; + reg = <0x80000 0x400>; + }; + qmi@80400 { + compatible = "fsl,fman-qmi"; + reg = <0x80400 0x400>; + }; + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + fman0_rx0: port@88000 { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx"; + reg = <0x88000 0x1000>; + }; + fman0_rx1: port@89000 { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx"; + reg = <0x89000 0x1000>; + }; + fman0_tx0: port@a8000 { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx"; + reg = <0xa8000 0x1000>; + fsl,qman-channel-id = <0x40>; + }; + fman0_tx1: port@a9000 { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx"; + reg = <0xa9000 0x1000>; + fsl,qman-channel-id = <0x41>; + }; + fman0_oh1: port@82000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x82000 0x1000>; + fsl,qman-channel-id = <0x43>; + }; + fman0_oh2: port@83000 { + cell-index = <2>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + fsl,qman-channel-id = <0x44>; + }; + fman0_oh3: port@84000 { + cell-index = <3>; + compatible = "fsl,fman-port-oh"; + reg = <0x84000 0x1000>; + fsl,qman-channel-id = <0x45>; + }; + fman0_oh4: port@85000 { + cell-index = <4>; + compatible = "fsl,fman-port-oh"; + reg = <0x85000 0x1000>; + fsl,qman-channel-id = <0x46>; + }; + enet0: ethernet@e0000 { + cell-index = <0>; + compatible = "fsl,fman-dtsec"; + reg = <0xe0000 0x1000>; + fsl,port-handles = <&fman0_rx0 &fman0_tx0>; + }; + enet1: ethernet@e2000 { + cell-index = <1>; + compatible = "fsl,fman-dtsec"; + reg = <0xe2000 0x1000>; + fsl,port-handles = <&fman0_rx1 &fman0_tx1>; + }; + mdio0: mdio@e1120 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-mdio"; + reg = <0xe1120 0xee0>; + interrupts = <26 1 0 0>; + }; + }; +}; + +&bportals { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; +}; diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi index 884e01bcb243..2c4787cbf395 100644 --- a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi @@ -175,6 +175,10 @@ compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; }; /include/ "pq3-etsec1-0.dtsi" + enet0: ethernet@24000 { + fsl,pmc-handle = <&etsec1_clk>; + + }; /include/ "pq3-etsec1-timer-0.dtsi" ptp_clock@24e00 { @@ -183,7 +187,15 @@ /include/ "pq3-etsec1-1.dtsi" + enet1: ethernet@25000 { + fsl,pmc-handle = <&etsec2_clk>; + }; + /include/ "pq3-etsec1-2.dtsi" + enet2: ethernet@26000 { + fsl,pmc-handle = <&etsec3_clk>; + }; + /include/ "pq3-esdhc-0.dtsi" sdhc@2e000 { compatible = "fsl,p2020-esdhc", "fsl,esdhc"; @@ -198,4 +210,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts new file mode 100644 index 000000000000..4c8371b316a8 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p2041rdb.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts new file mode 100644 index 000000000000..6f473416a51b --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p3041ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@2 { + status = "disabled"; + }; + }; +}; + diff --git a/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts new file mode 100644 index 000000000000..6b2dbfc1e08b --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p4080ds.dts" + +/ { + + aliases { + phy_rgmii = &phyrgmii; + phy5_slot3 = &phy5slot3; + phy6_slot3 = &phy6slot3; + phy7_slot3 = &phy7slot3; + phy8_slot3 = &phy8slot3; + emi1_slot3 = &p4080mdio2; + emi1_slot4 = &p4080mdio1; + emi1_slot5 = &p4080mdio3; + emi1_rgmii = &p4080mdio0; + emi2_slot4 = &p4080xmdio1; + emi2_slot5 = &p4080xmdio3; + }; +}; + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-fman-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts new file mode 100644 index 000000000000..42240a85054d --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p5020ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + status = "disabled"; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts b/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts new file mode 100644 index 000000000000..d5af499a1962 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p5040ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-fman-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + status = "disabled"; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + status = "disabled"; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + ethernet@10 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet10>; + }; + ethernet@11 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet11>; + }; + }; +}; + diff --git a/arch/powerpc/boot/dts/fsl/pq3-power.dtsi b/arch/powerpc/boot/dts/fsl/pq3-power.dtsi new file mode 100644 index 000000000000..5a760b3855bc --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/pq3-power.dtsi @@ -0,0 +1,48 @@ +/* + * PQ3 Power Management device tree stub + * + * Copyright 2012-2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + + etsec1_clk: soc-clk@24 { + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@25 { + fsl,pmcdr-mask = <0x00000040>; + }; + etsec3_clk: soc-clk@26 { + fsl,pmcdr-mask = <0x00000020>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi new file mode 100644 index 000000000000..130393056e1c --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi @@ -0,0 +1,80 @@ +/* + * QorIQ BMan Portal device tree stub for 10 portals + * + * Copyright 2011 - 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&bportals { + bman-portal@0 { + cell-index = <0>; + }; + + bman-portal@4000 { + cell-index = <1>; + }; + + bman-portal@8000 { + cell-index = <2>; + }; + + bman-portal@c000 { + cell-index = <3>; + }; + + bman-portal@10000 { + cell-index = <4>; + }; + + bman-portal@14000 { + cell-index = <5>; + }; + + bman-portal@18000 { + cell-index = <6>; + }; + + bman-portal@1c000 { + cell-index = <7>; + }; + + bman-portal@20000 { + cell-index = <8>; + }; + + bman-portal@24000 { + cell-index = <9>; + }; + + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi new file mode 100644 index 000000000000..d12b19191030 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi index eb77675c255a..29c4c8349890 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi index b965bc219bae..f8f44eb639fe 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi index 9eb6e6dd7cf9..4e55ac7b0e34 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi index 092b89936743..4c537954bfbb 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi index 2df0dc876045..1d458ed65c68 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi index 5fceb2438fdc..e2f4dc73e42e 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi new file mode 100644 index 000000000000..46189b62a211 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018 NXP + */ + +&soc { + chosen { + name = "chosen"; + dpaa-extended-args { + fman0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-extended-args"; + total-fifo-size = <0x27000>; + fman0_oh1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-op-extended-args"; + fifo-size = <0x800 0x0>; + num-dmas = <0x1 0x1>; + num-tnums = <0x1 0x4>; + }; + fman0_rx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + fifo-size = <0x7000 0x3000>; + num-dmas = <0x8 0x8>; + num-tnums = <0x10 0x8>; + }; + fman0_tx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-tx-extended-args"; + fifo-size = <0x4000 0x0>; + num-dmas = <0x8 0x0>; + num-tnums = <0x10 0x8>; + }; + }; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi new file mode 100644 index 000000000000..41bf8dee7b5a --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x41>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x42>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x43>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x44>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x45>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x40>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x46>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x47>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x48>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x49>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x4a>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x4b>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; +}; + diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi index 83ae87b69d92..3e2ef2b10414 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; }; fman1_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi index b0f0e36a4eac..8b41c39af8c1 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman1_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi index a3a79f8552a3..91dad61ba25c 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman1_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi index 96a69a84b8a8..26ed88f2f741 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman1_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi index 7405d1940133..dd708f384219 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman1_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi index f49ad69e5212..0c6aba079e1c 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman1_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi new file mode 100644 index 000000000000..90f47c9a2995 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018 NXP + */ + +&soc { + chosen { + name = "chosen"; + dpaa-extended-args { + fman1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-extended-args"; + total-fifo-size = <0x27000>; + fman1_oh1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-op-extended-args"; + fifo-size = <0x800 0x0>; + num-dmas = <0x1 0x1>; + num-tnums = <0x1 0x4>; + }; + fman1_rx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + fifo-size = <0x7000 0x3000>; + num-dmas = <0x8 0x8>; + num-tnums = <0x10 0x8>; + }; + fman1_tx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-tx-extended-args"; + fifo-size = <0x4000 0x0>; + num-dmas = <0x8 0x0>; + num-tnums = <0x10 0x8>; + }; + }; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi new file mode 100644 index 000000000000..cba95e0e5ae6 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman1 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x61>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x62>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x63>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x64>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x65>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x60>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x66>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x67>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x68>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x69>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x6a>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x6b>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi index baa0c503e741..8c239cd0f1d8 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi @@ -35,7 +35,7 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x88000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; @@ -43,7 +43,7 @@ fman@400000 { fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xa8000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi index 93095600e808..f310f4573390 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi @@ -35,14 +35,14 @@ fman@400000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi index ff4bd38f0645..5b5307546318 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi @@ -35,7 +35,7 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x89000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; @@ -43,7 +43,7 @@ fman@400000 { fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xa9000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi index 1fa38ed6f59e..f42856e56f3e 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi @@ -35,14 +35,14 @@ fman@400000 { fman0_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi index a8cc9780c0c4..eab7e908a87b 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi index 8b8bd70c9382..2e37b6c973b1 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi index 619c880b54d8..be3e7c8729f7 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi index d7ebb73a400d..5fab79e7b345 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi index b151d696a069..7675c7b028fe 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi index adc0ae0013a3..dbab7e1349a0 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman0_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi new file mode 100644 index 000000000000..a21ae92f7d13 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 10g - 2 */ + port@a8000 { + fsl,qman-channel-id = <0x802>; + }; + /* tx - 10g - 3 */ + port@a9000 { + fsl,qman-channel-id = <0x803>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x804>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x805>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x806>; + }; + /* tx - 1g - 5 */ + port@ad000 { + fsl,qman-channel-id = <0x807>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x800>; + }; + /* tx - 10g - 1 */ + port@b1000 { + fsl,qman-channel-id = <0x801>; + }; + /* offline - 1 */ + port@82000 { + fsl,qman-channel-id = <0x809>; + }; + /* offline - 2 */ + port@83000 { + fsl,qman-channel-id = <0x80a>; + }; + /* offline - 3 */ + port@84000 { + fsl,qman-channel-id = <0x80b>; + }; + /* offline - 4 */ + port@85000 { + fsl,qman-channel-id = <0x80c>; + }; + /* offline - 5 */ + port@86000 { + fsl,qman-channel-id = <0x80d>; + }; + /* offline - 6 */ + port@87000 { + fsl,qman-channel-id = <0x80e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi index 435047e0e250..58780bb2db13 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi @@ -35,14 +35,14 @@ fman@500000 { fman1_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman1_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi index c098657cca0a..0da76c16acf3 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi @@ -35,14 +35,14 @@ fman@500000 { fman1_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman1_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi index 9d06824815f3..e1d7067b1b58 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman1_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi index 70e947730c4b..1db943eae81b 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman1_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi index ad96e6529595..08346b532eba 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman1_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi index 034bc4b71f7a..11ee2e966083 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman1_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi index 93ca23d82b39..ad6cc1636f85 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman1_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi index 23b3117a2fd2..f64a6c47b99b 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman1_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; }; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi new file mode 100644 index 000000000000..397017ac910a --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman1 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x822>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x823>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x824>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x825>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x826>; + }; + /* tx - 1g - 5 */ + port@ad000 { + fsl,qman-channel-id = <0x827>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x820>; + }; + /* tx - 10g - 1 */ + port@b1000 { + fsl,qman-channel-id = <0x821>; + }; + /* offline - 1 */ + port@82000 { + fsl,qman-channel-id = <0x829>; + }; + /* offline - 2 */ + port@83000 { + fsl,qman-channel-id = <0x82a>; + }; + /* offline - 3 */ + port@84000 { + fsl,qman-channel-id = <0x82b>; + }; + /* offline - 4 */ + port@85000 { + fsl,qman-channel-id = <0x82c>; + }; + /* offline - 5 */ + port@86000 { + fsl,qman-channel-id = <0x82d>; + }; + /* offline - 6 */ + port@87000 { + fsl,qman-channel-id = <0x82e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi new file mode 100644 index 000000000000..91266d19fbe2 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 256>; + }; + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x21 0xf>; + }; + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi new file mode 100644 index 000000000000..a6205b1a4929 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi new file mode 100644 index 000000000000..779ab5ebb805 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 8>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi new file mode 100644 index 000000000000..2c75f4d168ae --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@1 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf10000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi new file mode 100644 index 000000000000..d8cb5390a305 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 512>; + }; + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x401 0xf>; + }; + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts new file mode 100644 index 000000000000..6a88f1e1f61e --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1023rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1023rdb.dts b/arch/powerpc/boot/dts/fsl/t1023rdb.dts index f82f85c65964..637e19b78e08 100644 --- a/arch/powerpc/boot/dts/fsl/t1023rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1023rdb.dts @@ -142,23 +142,23 @@ }; fman@400000 { - fm1mac1: ethernet@e0000 { + enet0: ethernet@e0000 { phy-handle = <&sgmii_rtk_phy2>; phy-connection-type = "sgmii"; sleep = <&rcpm 0x80000000>; }; - fm1mac2: ethernet@e2000 { + enet1: ethernet@e2000 { sleep = <&rcpm 0x40000000>; }; - fm1mac3: ethernet@e4000 { + enet2: ethernet@e4000 { phy-handle = <&sgmii_aqr_phy3>; phy-connection-type = "2500base-x"; sleep = <&rcpm 0x20000000>; }; - fm1mac4: ethernet@e6000 { + enet3: ethernet@e6000 { phy-handle = <&rgmii_rtk_phy1>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x10000000>; diff --git a/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts new file mode 100644 index 000000000000..a1b812d763fc --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1024qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts new file mode 100644 index 000000000000..a49b97dbf2a4 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts @@ -0,0 +1,28 @@ +#include "t1024rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1024rdb.dts b/arch/powerpc/boot/dts/fsl/t1024rdb.dts index 73a645324bc1..645caff98ed1 100644 --- a/arch/powerpc/boot/dts/fsl/t1024rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1024rdb.dts @@ -91,7 +91,7 @@ board-control@2,0 { #address-cells = <1>; #size-cells = <1>; - compatible = "fsl,t1024-cpld"; + compatible = "fsl,t1024-cpld", "fsl,deepsleep-cpld"; reg = <3 0 0x300>; ranges = <0 3 0 0x300>; bank-width = <1>; @@ -175,23 +175,23 @@ }; fman@400000 { - fm1mac1: ethernet@e0000 { + enet0: ethernet@e0000 { phy-handle = <&xg_aqr105_phy3>; phy-connection-type = "xgmii"; sleep = <&rcpm 0x80000000>; }; - fm1mac2: ethernet@e2000 { + enet1: ethernet@e2000 { sleep = <&rcpm 0x40000000>; }; - fm1mac3: ethernet@e4000 { + enet2: ethernet@e4000 { phy-handle = <&rgmii_phy2>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x20000000>; }; - fm1mac4: ethernet@e6000 { + enet3: ethernet@e6000 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x10000000>; diff --git a/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts new file mode 100644 index 000000000000..97439ff5ae32 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040d4rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts new file mode 100644 index 000000000000..c316c9b56de6 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts new file mode 100644 index 000000000000..ef1e80bcf484 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts index 65ff34c49025..825665c470e4 100644 --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts @@ -70,7 +70,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1040rdb-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; }; diff --git a/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts new file mode 100644 index 000000000000..6c3d636b5a3a --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042d4rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts new file mode 100644 index 000000000000..e9c68d063fe8 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts new file mode 100644 index 000000000000..38f7032441b5 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042rdb.dts" + + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb.dts b/arch/powerpc/boot/dts/fsl/t1042rdb.dts index 3ebb712224cb..099764322b33 100644 --- a/arch/powerpc/boot/dts/fsl/t1042rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1042rdb.dts @@ -68,7 +68,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1042rdb-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; }; diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts index 8ec3ff45e6fc..b10cab1a347b 100644 --- a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts +++ b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts @@ -41,7 +41,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1042rdb_pi-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; diff --git a/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts new file mode 100644 index 000000000000..898ea467b56a --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t2080qds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts new file mode 100644 index 000000000000..b3a5d7526c20 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t2080rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + }; +}; + +&bportals { + bman-portal@28000 { + cell-index = <0xa>; + }; + + bman-portal@2c000 { + cell-index = <0xb>; + }; + + bman-portal@30000 { + cell-index = <0xc>; + }; + + bman-portal@34000 { + cell-index = <0xd>; + }; + + bman-portal@38000 { + cell-index = <0xe>; + }; + + bman-portal@3c000 { + cell-index = <0xf>; + }; + + bman-portal@40000 { + cell-index = <0x10>; + }; + + bman-portal@44000 { + cell-index = <0x11>; + }; +}; diff --git a/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts new file mode 100644 index 000000000000..2dcec8a5939b --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t2081qds.dts" diff --git a/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts b/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts new file mode 100644 index 000000000000..db27e43751ee --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t4240qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts b/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts new file mode 100644 index 000000000000..4698f916330f --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t4240rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-fman3-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" +/include/ "qoriq-qman3-ceetm1-32-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + status = "disabled"; + }; + ethernet@5 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + status = "disabled"; + }; + ethernet@6 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + ethernet@10 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet10>; + }; + ethernet@11 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet11>; + }; + ethernet@12 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet12>; + status = "disabled"; + }; + ethernet@13 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet13>; + status = "disabled"; + }; + ethernet@14 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet14>; + }; + ethernet@15 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet15>; + }; + }; +}; + +&bportals { + bman-portal@28000 { + cell-index = <0xa>; + }; + + bman-portal@2c000 { + cell-index = <0xb>; + }; + + bman-portal@30000 { + cell-index = <0xc>; + }; + + bman-portal@34000 { + cell-index = <0xd>; + }; + + bman-portal@38000 { + cell-index = <0xe>; + }; + + bman-portal@3c000 { + cell-index = <0xf>; + }; + + bman-portal@40000 { + cell-index = <0x10>; + }; + + bman-portal@44000 { + cell-index = <0x11>; + }; + + bman-portal@48000 { + cell-index = <0x12>; + }; + + bman-portal@4c000 { + cell-index = <0x13>; + }; + + bman-portal@50000 { + cell-index = <0x14>; + }; + + bman-portal@54000 { + cell-index = <0x15>; + }; + + bman-portal@58000 { + cell-index = <0x16>; + }; + + bman-portal@5c000 { + cell-index = <0x17>; + }; + + bman-portal@60000 { + cell-index = <0x18>; + }; + + bman-portal@64000 { + cell-index = <0x19>; + }; + + bman-portal@68000 { + cell-index = <0x1a>; + }; + + bman-portal@6c000 { + cell-index = <0x1b>; + }; + + bman-portal@70000 { + cell-index = <0x1c>; + }; + + bman-portal@74000 { + cell-index = <0x1d>; + }; + + bman-portal@78000 { + cell-index = <0x1e>; + }; + + bman-portal@7c000 { + cell-index = <0x1f>; + }; + + bman-portal@80000 { + cell-index = <0x20>; + }; + + bman-portal@84000 { + cell-index = <0x21>; + }; + + bman-portal@88000 { + cell-index = <0x22>; + }; + + bman-portal@8c000 { + cell-index = <0x23>; + }; + + bman-portal@90000 { + cell-index = <0x24>; + }; + + bman-portal@94000 { + cell-index = <0x25>; + }; + + bman-portal@98000 { + cell-index = <0x26>; + }; + + bman-portal@9c000 { + cell-index = <0x27>; + }; + + bman-portal@a0000 { + cell-index = <0x28>; + }; + + bman-portal@a4000 { + cell-index = <0x29>; + }; + + bman-portal@a8000 { + cell-index = <0x2a>; + }; + + bman-portal@ac000 { + cell-index = <0x2b>; + }; + + bman-portal@b0000 { + cell-index = <0x2c>; + }; + + bman-portal@b4000 { + cell-index = <0x2d>; + }; + + bman-portal@b8000 { + cell-index = <0x2e>; + }; + + bman-portal@bc000 { + cell-index = <0x2f>; + }; + + bman-portal@c0000 { + cell-index = <0x30>; + }; + + bman-portal@c4000 { + cell-index = <0x31>; + }; +}; diff --git a/arch/powerpc/configs/85xx/p1023_sdk_defconfig b/arch/powerpc/configs/85xx/p1023_sdk_defconfig new file mode 100644 index 000000000000..64b304bc269d --- /dev/null +++ b/arch/powerpc/configs/85xx/p1023_sdk_defconfig @@ -0,0 +1,200 @@ +CONFIG_PPC_85xx=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_RCU_FANOUT=32 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_P1023_RDB=y +CONFIG_P1023_RDS=y +# CONFIG_QUICC_ENGINE is not set +# CONFIG_CPM is not set +# CONFIG_CPM2 is not set +# CONFIG_QE_GPIO is not set +CONFIG_CPM2=y +CONFIG_HIGHMEM=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_MISC=m +CONFIG_MATH_EMULATION=y +CONFIG_SWIOTLB=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MSI=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IP_SCTP=m +CONFIG_VLAN_8021Q=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_LEGACY=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_LOGGING=y +CONFIG_ATA=y +CONFIG_SATA_FSL=y +CONFIG_SATA_SIL24=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +CONFIG_HAS_FSL_QBMAN=y +CONFIG_FS_ENET=y +CONFIG_FSL_PQ_MDIO=y +CONFIG_FMAN_P1023=y +CONFIG_FSL_DPAA_ETH=y +CONFIG_E1000E=y +CONFIG_ATHEROS_PHY=y +CONFIG_PHYLIB=y +CONFIG_AT803X_PHY=y +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y +CONFIG_NVRAM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CPM=m +CONFIG_I2C_MPC=y +CONFIG_GPIO_MPC8XXX=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_MON=y +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_STORAGE=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_DMADEVICES=y +CONFIG_FSL_DMA=y +# CONFIG_NET_DMA is not set +CONFIG_STAGING=y +CONFIG_MEMORY=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_CRAMFS=y +CONFIG_VXFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_CRC_T10DIF=y +CONFIG_FRAME_WARN=8092 +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +CONFIG_STRICT_DEVMEM=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y diff --git a/arch/powerpc/configs/fmanv3h.config b/arch/powerpc/configs/fmanv3h.config new file mode 100644 index 000000000000..9d6bdd12988c --- /dev/null +++ b/arch/powerpc/configs/fmanv3h.config @@ -0,0 +1 @@ +CONFIG_FMAN_V3H=y diff --git a/arch/powerpc/configs/fmanv3l.config b/arch/powerpc/configs/fmanv3l.config new file mode 100644 index 000000000000..60f56f939c4e --- /dev/null +++ b/arch/powerpc/configs/fmanv3l.config @@ -0,0 +1 @@ +CONFIG_FMAN_V3L=y diff --git a/arch/powerpc/configs/sdk_dpaa.config b/arch/powerpc/configs/sdk_dpaa.config new file mode 100644 index 000000000000..78db185b6ca1 --- /dev/null +++ b/arch/powerpc/configs/sdk_dpaa.config @@ -0,0 +1,7 @@ +CONFIG_STAGING=y +CONFIG_FSL_SDK_BMAN=y +CONFIG_FSL_SDK_QMAN=y +CONFIG_FSL_SDK_DPA=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FSL_SDK_DPAA_ETH=y +CONFIG_CORTINA_PHY=y diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h index 4a1c9f0200e1..d76afc549c3c 100644 --- a/arch/powerpc/include/asm/cacheflush.h +++ b/arch/powerpc/include/asm/cacheflush.h @@ -42,6 +42,13 @@ extern void flush_dcache_page(struct page *page); #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) +extern void __flush_disable_L1(void); +#ifdef CONFIG_FSL_SOC_BOOKE +extern void flush_dcache_L1(void); +#else +#define flush_dcache_L1() do { } while (0) +#endif + void flush_icache_range(unsigned long start, unsigned long stop); extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, unsigned long addr, diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 235911fb0e24..7a66e76d182d 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -43,6 +43,14 @@ extern int machine_check_e500mc(struct pt_regs *regs); extern int machine_check_e500(struct pt_regs *regs); extern int machine_check_e200(struct pt_regs *regs); extern int machine_check_47x(struct pt_regs *regs); + +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) +extern void __flush_caches_e500v2(void); +extern void __flush_caches_e500mc(void); +extern void __flush_caches_e5500(void); +extern void __flush_caches_e6500(void); +#endif + int machine_check_8xx(struct pt_regs *regs); int machine_check_83xx(struct pt_regs *regs); @@ -70,6 +78,10 @@ struct cpu_spec { /* flush caches inside the current cpu */ void (*cpu_down_flush)(void); +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) + /* flush caches of the cpu which is running the function */ + void (*cpu_flush_caches)(void); +#endif /* number of performance monitor counters */ unsigned int num_pmcs; enum powerpc_pmc_type pmc_type; diff --git a/arch/powerpc/include/asm/fsl_pm.h b/arch/powerpc/include/asm/fsl_pm.h index 61a4c977320f..07bc10501969 100644 --- a/arch/powerpc/include/asm/fsl_pm.h +++ b/arch/powerpc/include/asm/fsl_pm.h @@ -7,6 +7,9 @@ #ifndef __PPC_FSL_PM_H #define __PPC_FSL_PM_H +#ifndef __ASSEMBLY__ +#include <linux/suspend.h> + #define E500_PM_PH10 1 #define E500_PM_PH15 2 #define E500_PM_PH20 3 @@ -42,6 +45,34 @@ struct fsl_pm_ops { extern const struct fsl_pm_ops *qoriq_pm_ops; +struct fsm_reg_vals { + u32 offset; + u32 value; +}; + +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val); +void fsl_epu_setup_default(void __iomem *epu_base); +void fsl_npc_setup_default(void __iomem *npc_base); +void fsl_fsm_clean(void __iomem *base, struct fsm_reg_vals *val); +void fsl_epu_clean_default(void __iomem *epu_base); + +extern int fsl_dp_iomap(void); +extern void fsl_dp_iounmap(void); + +extern int fsl_enter_epu_deepsleep(void); +extern void fsl_dp_enter_low(void __iomem *ccsr_base, void __iomem *dcsr_base, + void __iomem *pld_base, int pld_flag); +extern void fsl_booke_deep_sleep_resume(void); + int __init fsl_rcpm_init(void); +void set_pm_suspend_state(suspend_state_t state); +suspend_state_t pm_suspend_state(void); + +void fsl_set_power_except(struct device *dev, int on); +#endif /* __ASSEMBLY__ */ + +#define T1040QDS_TETRA_FLAG 1 +#define T104xRDB_CPLD_FLAG 2 + #endif /* __PPC_FSL_PM_H */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index afbd47b0a75c..56931ea2febe 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o ifneq ($(CONFIG_FA_DUMP)$(CONFIG_PRESERVE_FA_DUMP),) obj-y += fadump.o endif +obj-$(CONFIG_FSL_SOC) += fsl_pm.o ifdef CONFIG_PPC32 obj-$(CONFIG_E500) += idle_e500.o endif diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index af399675248e..377446b74e8d 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -365,6 +365,9 @@ int main(void) OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore); +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) + OFFSET(CPU_FLUSH_CACHES, cpu_spec, cpu_flush_caches); +#endif OFFSET(pbe_address, pbe, address); OFFSET(pbe_orig_address, pbe, orig_address); diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 2b4f3ec0acf7..1b543b5fed59 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -340,3 +340,84 @@ _GLOBAL(cpu_down_flush_e5500) /* L1 Data Cache of e6500 contains no modified data, no flush is required */ _GLOBAL(cpu_down_flush_e6500) blr + +_GLOBAL(__flush_caches_e500v2) + mflr r0 + bl flush_dcache_L1 + mtlr r0 + blr + +_GLOBAL(__flush_caches_e500mc) +_GLOBAL(__flush_caches_e5500) + mflr r0 + bl flush_dcache_L1 + bl flush_backside_L2_cache + mtlr r0 + blr + +/* L1 Data Cache of e6500 contains no modified data, no flush is required */ +_GLOBAL(__flush_caches_e6500) + blr + + /* r3 = virtual address of L2 controller, WIMG = 01xx */ +_GLOBAL(flush_disable_L2) + /* It's a write-through cache, so only invalidation is needed. */ + mbar + isync + lwz r4, 0(r3) + li r5, 1 + rlwimi r4, r5, 30, 0xc0000000 + stw r4, 0(r3) + + /* Wait for the invalidate to finish */ +1: lwz r4, 0(r3) + andis. r4, r4, 0x4000 + bne 1b + mbar + + blr + + /* r3 = virtual address of L2 controller, WIMG = 01xx */ +_GLOBAL(invalidate_enable_L2) + mbar + isync + lwz r4, 0(r3) + li r5, 3 + rlwimi r4, r5, 30, 0xc0000000 + stw r4, 0(r3) + + /* Wait for the invalidate to finish */ +1: lwz r4, 0(r3) + andis. r4, r4, 0x4000 + bne 1b + mbar + + blr + +/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */ +_GLOBAL(__flush_disable_L1) + mflr r10 + bl flush_dcache_L1 /* Flush L1 d-cache */ + mtlr r10 + + mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */ + li r5, 2 + rlwimi r4, r5, 0, 3 + + msync + isync + mtspr SPRN_L1CSR0, r4 + isync + +1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */ + andi. r4, r4, 2 + bne 1b + + mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */ + li r5, 2 + rlwimi r4, r5, 0, 3 + + mtspr SPRN_L1CSR1, r4 + isync + + blr diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 245be4fafe13..a099347404db 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -2051,6 +2051,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500, .platform = "ppc8548", .cpu_down_flush = cpu_down_flush_e500v2, + .cpu_flush_caches = __flush_caches_e500v2, }, #else { /* e500mc */ @@ -2071,6 +2072,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500mc, .platform = "ppce500mc", .cpu_down_flush = cpu_down_flush_e500mc, + .cpu_flush_caches = __flush_caches_e500mc, }, #endif /* CONFIG_PPC_E500MC */ #endif /* CONFIG_PPC32 */ @@ -2096,6 +2098,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500mc, .platform = "ppce5500", .cpu_down_flush = cpu_down_flush_e5500, + .cpu_flush_caches = __flush_caches_e5500, }, { /* e6500 */ .pvr_mask = 0xffff0000, @@ -2119,6 +2122,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500mc, .platform = "ppce6500", .cpu_down_flush = cpu_down_flush_e6500, + .cpu_flush_caches = __flush_caches_e6500, }, #endif /* CONFIG_PPC_E500MC */ #ifdef CONFIG_PPC32 diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S index ea065282b303..0e3484d3b663 100644 --- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S +++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S @@ -174,6 +174,10 @@ skpinv: addi r6,r6,1 /* Increment */ lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@h ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@l mtspr SPRN_MAS2,r6 +#ifdef ENTRY_DEEPSLEEP_SETUP + LOAD_REG_IMMEDIATE(r8, MEMORY_START) + ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR) +#endif mtspr SPRN_MAS3,r8 tlbwe @@ -216,12 +220,18 @@ next_tlb_setup: #error You need to specify the mapping or not use this at all. #endif +#ifdef ENTRY_DEEPSLEEP_SETUP + LOAD_REG_ADDR(r6, 2f) + mfmsr r7 + rlwinm r7,r7,0,~(MSR_IS|MSR_DS) +#else lis r7,MSR_KERNEL@h ori r7,r7,MSR_KERNEL@l bl 1f /* Find our address */ 1: mflr r9 rlwimi r6,r9,0,20,31 addi r6,r6,(2f - 1b) +#endif mtspr SPRN_SRR0,r6 mtspr SPRN_SRR1,r7 rfi /* start execution out of TLB1[0] entry */ diff --git a/arch/powerpc/kernel/fsl_pm.c b/arch/powerpc/kernel/fsl_pm.c new file mode 100644 index 000000000000..24a179fd8784 --- /dev/null +++ b/arch/powerpc/kernel/fsl_pm.c @@ -0,0 +1,49 @@ +/* + * Freescale General Power Management Implementation + * + * Copyright 2018 NXP + * Author: Wang Dongsheng <dongsheng.wang@freescale.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/suspend.h> +#include <asm/fsl_pm.h> + +static suspend_state_t pm_state; + +void set_pm_suspend_state(suspend_state_t state) +{ + pm_state = state; +} + +suspend_state_t pm_suspend_state(void) +{ + return pm_state; +} diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 9019f1395d39..9abae702f7b9 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -860,7 +860,7 @@ _GLOBAL(start_secondary_resume) /* * This subroutine clobbers r11 and r12 */ -enable_64b_mode: +_GLOBAL(enable_64b_mode) mfmsr r11 /* grab the current MSR */ #ifdef CONFIG_PPC_BOOK3E oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h index c750ac9ec713..3b520aa5523e 100644 --- a/arch/powerpc/mm/mmu_decl.h +++ b/arch/powerpc/mm/mmu_decl.h @@ -89,6 +89,12 @@ void print_system_hash_info(void); #endif /* CONFIG_PPC_MMU_NOHASH */ +void settlbcam(int index, unsigned long virt, phys_addr_t phys, + unsigned long size, unsigned long flags, unsigned int pid); + +void cleartlbcam(unsigned long virt, unsigned int pid); + + #ifdef CONFIG_PPC32 void hash_preload(struct mm_struct *mm, unsigned long ea); diff --git a/arch/powerpc/mm/nohash/fsl_booke.c b/arch/powerpc/mm/nohash/fsl_booke.c index 556e3cd52a35..e454a69ce6bc 100644 --- a/arch/powerpc/mm/nohash/fsl_booke.c +++ b/arch/powerpc/mm/nohash/fsl_booke.c @@ -102,7 +102,7 @@ unsigned long p_block_mapped(phys_addr_t pa) * an unsigned long (for example, 32-bit implementations cannot support a 4GB * size). */ -static void settlbcam(int index, unsigned long virt, phys_addr_t phys, +void settlbcam(int index, unsigned long virt, phys_addr_t phys, unsigned long size, unsigned long flags, unsigned int pid) { unsigned int tsize; @@ -140,6 +140,18 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys, tlbcam_addrs[index].phys = phys; } +void cleartlbcam(unsigned long virt, unsigned int pid) +{ + int i = 0; + for (i = 0; i < NUM_TLBCAMS; i++) { + if (tlbcam_addrs[i].start == virt) { + TLBCAM[i].MAS1 = 0; + loadcam_entry(i); + return; + } + } +} + unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, phys_addr_t phys) { diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c index 273145aed90a..5c6227f7bc37 100644 --- a/arch/powerpc/platforms/83xx/km83xx.c +++ b/arch/powerpc/platforms/83xx/km83xx.c @@ -34,7 +34,6 @@ #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c index f46d7bf3b140..6935a5b9fbd1 100644 --- a/arch/powerpc/platforms/83xx/misc.c +++ b/arch/powerpc/platforms/83xx/misc.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <asm/hw_irq.h> #include <asm/ipic.h> -#include <soc/fsl/qe/qe_ic.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> @@ -90,24 +89,9 @@ void __init mpc83xx_ipic_init_IRQ(void) } #ifdef CONFIG_QUICC_ENGINE -void __init mpc83xx_qe_init_IRQ(void) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (!np) { - np = of_find_node_by_type(NULL, "qeic"); - if (!np) - return; - } - qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); - of_node_put(np); -} - void __init mpc83xx_ipic_and_qe_init_IRQ(void) { mpc83xx_ipic_init_IRQ(); - mpc83xx_qe_init_IRQ(); } #endif /* CONFIG_QUICC_ENGINE */ diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index b428835e5919..1c73af104d19 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -33,7 +33,6 @@ #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c index 4588ce632484..87f68ca06255 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c @@ -22,7 +22,6 @@ #include <asm/ipic.h> #include <asm/udbg.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index 4a4efa906d35..5b484da9533e 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -41,7 +41,6 @@ #include <sysdev/fsl_pci.h> #include <sysdev/simple_gpio.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c index 9923059cb111..b7119e443920 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c +++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c @@ -17,7 +17,6 @@ #include <asm/ipic.h> #include <asm/udbg.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index fa3d29dcb57e..a933e74ca65f 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -10,6 +10,8 @@ menuconfig FSL_SOC_BOOKE select SERIAL_8250_EXTENDED if SERIAL_8250 select SERIAL_8250_SHARE_IRQ if SERIAL_8250 select FSL_CORENET_RCPM if PPC_E500MC + select FSL_QORIQ_PM if SUSPEND && PPC_E500MC + select FSL_PMC if SUSPEND && !PPC_E500MC default y if FSL_SOC_BOOKE @@ -292,3 +294,7 @@ endif # FSL_SOC_BOOKE config TQM85xx bool + +config FSL_QORIQ_PM + bool + select FSL_SLEEP_FSM diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index d1dd0dca5ebf..8e9f3699a6a7 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -3,7 +3,9 @@ # Makefile for the PowerPC 85xx linux kernel. # obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SUSPEND) += sleep.o obj-$(CONFIG_FSL_PMC) += mpc85xx_pm_ops.o +obj-$(CONFIG_FSL_QORIQ_PM) += qoriq_pm.o deepsleep.o obj-y += common.o diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index 7ee2c6628f64..8c1bb3941642 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -24,7 +24,6 @@ #include <asm/mpic.h> #include <asm/ehv_pic.h> #include <asm/swiotlb.h> -#include <soc/fsl/qe/qe_ic.h> #include <linux/of_platform.h> #include <sysdev/fsl_soc.h> @@ -38,8 +37,6 @@ void __init corenet_gen_pic_init(void) unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | MPIC_NO_RESET; - struct device_node *np; - if (ppc_md.get_irq == mpic_get_coreint_irq) flags |= MPIC_ENABLE_COREINT; @@ -47,13 +44,6 @@ void __init corenet_gen_pic_init(void) BUG_ON(mpic == NULL); mpic_init(mpic); - - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (np) { - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - of_node_put(np); - } } /* diff --git a/arch/powerpc/platforms/85xx/deepsleep.c b/arch/powerpc/platforms/85xx/deepsleep.c new file mode 100644 index 000000000000..73992b4fedcc --- /dev/null +++ b/arch/powerpc/platforms/85xx/deepsleep.c @@ -0,0 +1,349 @@ +/* + * Support deep sleep feature for T104x + * + * Copyright 2018 NXP + * Author: Chenhui Zhao <chenhui.zhao@freescale.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/kernel.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <sysdev/fsl_soc.h> +#include <asm/machdep.h> +#include <asm/fsl_pm.h> + +#define SIZE_1MB 0x100000 +#define SIZE_2MB 0x200000 + +#define CPC_CPCHDBCR0 0x10f00 +#define CPC_CPCHDBCR0_SPEC_DIS 0x08000000 + +#define CCSR_SCFG_DPSLPCR 0xfc000 +#define CCSR_SCFG_DPSLPCR_WDRR_EN 0x1 +#define CCSR_SCFG_SPARECR2 0xfc504 +#define CCSR_SCFG_SPARECR3 0xfc508 + +#define CCSR_GPIO1_GPDIR 0x130000 +#define CCSR_GPIO1_GPODR 0x130004 +#define CCSR_GPIO1_GPDAT 0x130008 +#define CCSR_GPIO1_GPDIR_29 0x4 + +#define RCPM_BLOCK_OFFSET 0x00022000 +#define EPU_BLOCK_OFFSET 0x00000000 +#define NPC_BLOCK_OFFSET 0x00001000 + +#define CSTTACR0 0xb00 +#define CG1CR0 0x31c + +#define CCSR_LAW_BASE 0xC00 +#define DCFG_BRR 0xE4 /* boot release register */ +#define LCC_BSTRH 0x20 /* Boot space translation register high */ +#define LCC_BSTRL 0x24 /* Boot space translation register low */ +#define LCC_BSTAR 0x28 /* Boot space translation attribute register */ +#define RCPM_PCTBENR 0x1A0 /* Physical Core Timebase Enable Register */ +#define RCPM_BASE 0xE2000 +#define DCFG_BASE 0xE0000 + +/* 128 bytes buffer for restoring data broke by DDR training initialization */ +#define DDR_BUF_SIZE 128 +static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64); + +static void *dcsr_base, *ccsr_base, *pld_base; +static int pld_flag; + +/* for law */ +struct fsl_law { + u32 lawbarh; /* LAWn base address high */ + u32 lawbarl; /* LAWn base address low */ + u32 lawar; /* LAWn attributes */ + u32 reserved; +}; + +struct fsl_law *saved_law; +static u32 num_laws; + +/* for nonboot cpu */ +struct fsl_bstr { + u32 bstrh; + u32 bstrl; + u32 bstar; + u32 cpu_mask; +}; +static struct fsl_bstr saved_bstr; + +int fsl_dp_iomap(void) +{ + struct device_node *np; + int ret = 0; + phys_addr_t ccsr_phy_addr, dcsr_phy_addr; + + saved_law = NULL; + ccsr_base = NULL; + dcsr_base = NULL; + pld_base = NULL; + + ccsr_phy_addr = get_immrbase(); + if (ccsr_phy_addr == -1) { + pr_err("%s: Can't get the address of CCSR\n", __func__); + ret = -EINVAL; + goto ccsr_err; + } + ccsr_base = ioremap(ccsr_phy_addr, SIZE_2MB); + if (!ccsr_base) { + ret = -ENOMEM; + goto ccsr_err; + } + + dcsr_phy_addr = get_dcsrbase(); + if (dcsr_phy_addr == -1) { + pr_err("%s: Can't get the address of DCSR\n", __func__); + ret = -EINVAL; + goto dcsr_err; + } + dcsr_base = ioremap(dcsr_phy_addr, SIZE_1MB); + if (!dcsr_base) { + ret = -ENOMEM; + goto dcsr_err; + } + + np = of_find_compatible_node(NULL, NULL, "fsl,tetra-fpga"); + if (np) { + pld_flag = T1040QDS_TETRA_FLAG; + } else { + np = of_find_compatible_node(NULL, NULL, "fsl,deepsleep-cpld"); + if (np) { + pld_flag = T104xRDB_CPLD_FLAG; + } else { + pr_err("%s: Can't find the FPGA/CPLD node\n", + __func__); + ret = -EINVAL; + goto pld_err; + } + } + pld_base = of_iomap(np, 0); + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "fsl,corenet-law"); + if (!np) { + pr_err("%s: Can't find the node of \"law\"\n", __func__); + ret = -EINVAL; + goto alloc_err; + } + ret = of_property_read_u32(np, "fsl,num-laws", &num_laws); + if (ret) { + ret = -EINVAL; + goto alloc_err; + } + + saved_law = kzalloc(sizeof(*saved_law) * num_laws, GFP_KERNEL); + if (!saved_law) { + ret = -ENOMEM; + goto alloc_err; + } + of_node_put(np); + + return 0; + +alloc_err: + iounmap(pld_base); + pld_base = NULL; +pld_err: + iounmap(dcsr_base); + dcsr_base = NULL; +dcsr_err: + iounmap(ccsr_base); + ccsr_base = NULL; +ccsr_err: + return ret; +} + +void fsl_dp_iounmap(void) +{ + if (dcsr_base) { + iounmap(dcsr_base); + dcsr_base = NULL; + } + + if (ccsr_base) { + iounmap(ccsr_base); + ccsr_base = NULL; + } + + if (pld_base) { + iounmap(pld_base); + pld_base = NULL; + } + + kfree(saved_law); + saved_law = NULL; +} + +static void fsl_dp_ddr_save(void *ccsr_base) +{ + u32 ddr_buff_addr; + + /* + * DDR training initialization will break 128 bytes at the beginning + * of DDR, therefore, save them so that the bootloader will restore + * them. Assume that DDR is mapped to the address space started with + * CONFIG_PAGE_OFFSET. + */ + memcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE); + + /* assume ddr_buff is in the physical address space of 4GB */ + ddr_buff_addr = (u32)(__pa(ddr_buff) & 0xffffffff); + + /* + * the bootloader will restore the first 128 bytes of DDR from + * the location indicated by the register SPARECR3 + */ + out_be32(ccsr_base + CCSR_SCFG_SPARECR3, ddr_buff_addr); +} + +static void fsl_dp_mp_save(void *ccsr) +{ + struct fsl_bstr *dst = &saved_bstr; + + dst->bstrh = in_be32(ccsr + LCC_BSTRH); + dst->bstrl = in_be32(ccsr + LCC_BSTRL); + dst->bstar = in_be32(ccsr + LCC_BSTAR); + dst->cpu_mask = in_be32(ccsr + DCFG_BASE + DCFG_BRR); +} + +static void fsl_dp_mp_restore(void *ccsr) +{ + struct fsl_bstr *src = &saved_bstr; + + out_be32(ccsr + LCC_BSTRH, src->bstrh); + out_be32(ccsr + LCC_BSTRL, src->bstrl); + out_be32(ccsr + LCC_BSTAR, src->bstar); + + /* release the nonboot cpus */ + out_be32(ccsr + DCFG_BASE + DCFG_BRR, src->cpu_mask); + + /* enable the time base */ + out_be32(ccsr + RCPM_BASE + RCPM_PCTBENR, src->cpu_mask); + /* read back to sync write */ + in_be32(ccsr + RCPM_BASE + RCPM_PCTBENR); +} + +static void fsl_dp_law_save(void *ccsr) +{ + int i; + struct fsl_law *dst = saved_law; + struct fsl_law *src = (void *)(ccsr + CCSR_LAW_BASE); + + for (i = 0; i < num_laws; i++) { + dst->lawbarh = in_be32(&src->lawbarh); + dst->lawbarl = in_be32(&src->lawbarl); + dst->lawar = in_be32(&src->lawar); + dst++; + src++; + } +} + +static void fsl_dp_law_restore(void *ccsr) +{ + int i; + struct fsl_law *src = saved_law; + struct fsl_law *dst = (void *)(ccsr + CCSR_LAW_BASE); + + for (i = 0; i < num_laws - 1; i++) { + out_be32(&dst->lawar, 0); + out_be32(&dst->lawbarl, src->lawbarl); + out_be32(&dst->lawbarh, src->lawbarh); + out_be32(&dst->lawar, src->lawar); + + /* Read back so that we sync the writes */ + in_be32(&dst->lawar); + src++; + dst++; + } +} + +static void fsl_dp_set_resume_pointer(void *ccsr_base) +{ + u32 resume_addr; + + /* the bootloader will finally jump to this address to return kernel */ +#ifdef CONFIG_PPC32 + resume_addr = (u32)(__pa(fsl_booke_deep_sleep_resume)); +#else + resume_addr = (u32)(__pa(*(u64 *)fsl_booke_deep_sleep_resume) + & 0xffffffff); +#endif + + /* use the register SPARECR2 to save the resume address */ + out_be32(ccsr_base + CCSR_SCFG_SPARECR2, resume_addr); + +} + +int fsl_enter_epu_deepsleep(void) +{ + fsl_dp_ddr_save(ccsr_base); + + fsl_dp_set_resume_pointer(ccsr_base); + + fsl_dp_mp_save(ccsr_base); + fsl_dp_law_save(ccsr_base); + /* enable Warm Device Reset request. */ + setbits32(ccsr_base + CCSR_SCFG_DPSLPCR, CCSR_SCFG_DPSLPCR_WDRR_EN); + + /* set GPIO1_29 as an output pin (not open-drain), and output 0 */ + clrbits32(ccsr_base + CCSR_GPIO1_GPDAT, CCSR_GPIO1_GPDIR_29); + clrbits32(ccsr_base + CCSR_GPIO1_GPODR, CCSR_GPIO1_GPDIR_29); + setbits32(ccsr_base + CCSR_GPIO1_GPDIR, CCSR_GPIO1_GPDIR_29); + + /* + * Disable CPC speculation to avoid deep sleep hang, especially + * in secure boot mode. This bit will be cleared automatically + * when resuming from deep sleep. + */ + setbits32(ccsr_base + CPC_CPCHDBCR0, CPC_CPCHDBCR0_SPEC_DIS); + + fsl_epu_setup_default(dcsr_base + EPU_BLOCK_OFFSET); + fsl_npc_setup_default(dcsr_base + NPC_BLOCK_OFFSET); + out_be32(dcsr_base + RCPM_BLOCK_OFFSET + CSTTACR0, 0x00001001); + out_be32(dcsr_base + RCPM_BLOCK_OFFSET + CG1CR0, 0x00000001); + + fsl_dp_enter_low(ccsr_base, dcsr_base, pld_base, pld_flag); + + fsl_dp_law_restore(ccsr_base); + fsl_dp_mp_restore(ccsr_base); + + /* disable Warm Device Reset request */ + clrbits32(ccsr_base + CCSR_SCFG_DPSLPCR, CCSR_SCFG_DPSLPCR_WDRR_EN); + + fsl_epu_clean_default(dcsr_base + EPU_BLOCK_OFFSET); + + return 0; +} diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 5ca254256c47..7d3129030395 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -45,7 +45,6 @@ #include <sysdev/fsl_pci.h> #include <sysdev/simple_gpio.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include <asm/mpic.h> #include <asm/swiotlb.h> #include "smp.h" @@ -279,20 +278,6 @@ static void __init mpc85xx_mds_qeic_init(void) of_node_put(np); return; } - - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (!np) { - np = of_find_node_by_type(NULL, "qeic"); - if (!np) - return; - } - - if (machine_is(p1021_mds)) - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - else - qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); - of_node_put(np); } #else static void __init mpc85xx_mds_qe_init(void) { } diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index d3c540ee558f..14b5a61d49c1 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -23,7 +23,6 @@ #include <asm/udbg.h> #include <asm/mpic.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> @@ -44,10 +43,6 @@ void __init mpc85xx_rdb_pic_init(void) { struct mpic *mpic; -#ifdef CONFIG_QUICC_ENGINE - struct device_node *np; -#endif - if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) { mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | MPIC_BIG_ENDIAN | @@ -62,18 +57,6 @@ void __init mpc85xx_rdb_pic_init(void) BUG_ON(mpic == NULL); mpic_init(mpic); - -#ifdef CONFIG_QUICC_ENGINE - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (np) { - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - of_node_put(np); - - } else - pr_err("%s: Could not find qe-ic node\n", __func__); -#endif - } /* diff --git a/arch/powerpc/platforms/85xx/qoriq_pm.c b/arch/powerpc/platforms/85xx/qoriq_pm.c new file mode 100644 index 000000000000..9390944c53f0 --- /dev/null +++ b/arch/powerpc/platforms/85xx/qoriq_pm.c @@ -0,0 +1,222 @@ +/* + * Support Power Management feature + * + * Copyright 2018 NXP + * Author: Chenhui Zhao <chenhui.zhao@freescale.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/kernel.h> +#include <linux/suspend.h> +#include <linux/of_platform.h> +#include <linux/usb.h> + +#include <asm/fsl_pm.h> + +#define FSL_SLEEP 0x1 +#define FSL_DEEP_SLEEP 0x2 + +int (*fsl_enter_deepsleep)(void); + +/* specify the sleep state of the present platform */ +unsigned int sleep_pm_state; +/* supported sleep modes by the present platform */ +static unsigned int sleep_modes; + +/** + * fsl_set_power_except - set which IP block is not powerdown when sleep, + * such as MAC, USB, etc. + * + * @dev: a pointer to the struct device + * @on: if 1, do not power down; if 0, power down. + */ +void fsl_set_power_except(struct device *dev, int on) +{ + u32 value[2]; + u32 pw_mask; + int ret; + struct device_node *mac_node; + const phandle *phandle_prop; + + if (dev && !strncmp(dev->bus->name, "usb", 3)) { + struct usb_device *udev = container_of(dev, + struct usb_device, dev); + struct device *controller = udev->bus->controller; + + ret = of_property_read_u32_array(controller->parent->of_node, + "sleep", value, 2); + } else + ret = of_property_read_u32_array(dev->of_node, "sleep", + value, 2); + + if (ret) { + /* search fman mac node */ + phandle_prop = of_get_property(dev->of_node, "fsl,fman-mac", + NULL); + if (phandle_prop == NULL) + goto err; + + mac_node = of_find_node_by_phandle(*phandle_prop); + ret = of_property_read_u32_array(mac_node, "sleep", value, 2); + of_node_put(mac_node); + if (ret) + goto err; + } + /* get the second value, it is a mask */ + pw_mask = value[1]; + qoriq_pm_ops->set_ip_power(on, pw_mask); + return; + +err: + dev_err(dev, "Can not set wakeup sources\n"); +} +EXPORT_SYMBOL_GPL(fsl_set_power_except); + +void qoriq_set_wakeup_source(struct device *dev, void *enable) +{ + if (!device_may_wakeup(dev)) + return; + + fsl_set_power_except(dev, *((int *)enable)); +} + +static int qoriq_suspend_enter(suspend_state_t state) +{ + int ret = 0; + int cpu; + + switch (state) { + case PM_SUSPEND_STANDBY: + + if (cur_cpu_spec->cpu_flush_caches) + cur_cpu_spec->cpu_flush_caches(); + + ret = qoriq_pm_ops->plat_enter_sleep(); + + break; + + case PM_SUSPEND_MEM: + + cpu = smp_processor_id(); + qoriq_pm_ops->irq_mask(cpu); + + ret = fsl_enter_deepsleep(); + + qoriq_pm_ops->irq_unmask(cpu); + + break; + + default: + ret = -EINVAL; + + } + + return ret; +} + +static int qoriq_suspend_valid(suspend_state_t state) +{ + set_pm_suspend_state(state); + + if (state == PM_SUSPEND_STANDBY && (sleep_modes & FSL_SLEEP)) + return 1; + + if (state == PM_SUSPEND_MEM && (sleep_modes & FSL_DEEP_SLEEP)) + return 1; + + set_pm_suspend_state(PM_SUSPEND_ON); + return 0; +} + +static int qoriq_suspend_begin(suspend_state_t state) +{ + const int enable = 1; + + dpm_for_each_dev((void *)&enable, qoriq_set_wakeup_source); + + if (state == PM_SUSPEND_MEM) + return fsl_dp_iomap(); + + return 0; +} + +static void qoriq_suspend_end(void) +{ + const int enable = 0; + + dpm_for_each_dev((void *)&enable, qoriq_set_wakeup_source); + + set_pm_suspend_state(PM_SUSPEND_ON); + fsl_dp_iounmap(); +} + +static const struct platform_suspend_ops qoriq_suspend_ops = { + .valid = qoriq_suspend_valid, + .enter = qoriq_suspend_enter, + .begin = qoriq_suspend_begin, + .end = qoriq_suspend_end, +}; + +static const struct of_device_id deepsleep_matches[] = { + { + .compatible = "fsl,t1040-rcpm", + }, + { + .compatible = "fsl,t1024-rcpm", + }, + { + .compatible = "fsl,t1023-rcpm", + }, + {}, +}; + +static int __init qoriq_suspend_init(void) +{ + struct device_node *np; + + sleep_modes = FSL_SLEEP; + sleep_pm_state = PLAT_PM_SLEEP; + + np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-rcpm-2.0"); + if (np) + sleep_pm_state = PLAT_PM_LPM20; + + np = of_find_matching_node_and_match(NULL, deepsleep_matches, NULL); + if (np) { + fsl_enter_deepsleep = fsl_enter_epu_deepsleep; + sleep_modes |= FSL_DEEP_SLEEP; + } + + suspend_set_ops(&qoriq_suspend_ops); + set_pm_suspend_state(PM_SUSPEND_ON); + + return 0; +} +arch_initcall(qoriq_suspend_init); diff --git a/arch/powerpc/platforms/85xx/sleep.S b/arch/powerpc/platforms/85xx/sleep.S new file mode 100644 index 000000000000..b7942edce2f0 --- /dev/null +++ b/arch/powerpc/platforms/85xx/sleep.S @@ -0,0 +1,1192 @@ +/* + * Enter and leave deep sleep/sleep state + * + * Copyright 2018 NXP + * Author: Scott Wood <scottwood@freescale.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <asm/page.h> +#include <asm/ppc_asm.h> +#include <asm/reg.h> +#include <asm/asm-offsets.h> +#include <asm/fsl_pm.h> +#include <asm/mmu.h> + +/* + * the number of bytes occupied by one register + * the value of 8 is compatible with both 32-bit and 64-bit registers + */ +#define STRIDE_SIZE 8 + +/* GPR0 - GPR31 */ +#define BOOKE_GPR0_OFF 0x0000 +#define BOOKE_GPR_COUNT 32 +/* IVOR0 - IVOR42 */ +#define BOOKE_IVOR0_OFF (BOOKE_GPR0_OFF + BOOKE_GPR_COUNT * STRIDE_SIZE) +#define BOOKE_IVOR_COUNT 43 +/* SPRG0 - SPRG9 */ +#define BOOKE_SPRG0_OFF (BOOKE_IVOR0_OFF + BOOKE_IVOR_COUNT * STRIDE_SIZE) +#define BOOKE_SPRG_COUNT 10 +/* IVPR */ +#define BOOKE_IVPR_OFF (BOOKE_SPRG0_OFF + BOOKE_SPRG_COUNT * STRIDE_SIZE) + +#define BOOKE_LR_OFF (BOOKE_IVPR_OFF + STRIDE_SIZE) +#define BOOKE_MSR_OFF (BOOKE_LR_OFF + STRIDE_SIZE) +#define BOOKE_TBU_OFF (BOOKE_MSR_OFF + STRIDE_SIZE) +#define BOOKE_TBL_OFF (BOOKE_TBU_OFF + STRIDE_SIZE) +#define BOOKE_EPCR_OFF (BOOKE_TBL_OFF + STRIDE_SIZE) +#define BOOKE_HID0_OFF (BOOKE_EPCR_OFF + STRIDE_SIZE) +#define BOOKE_PIR_OFF (BOOKE_HID0_OFF + STRIDE_SIZE) +#define BOOKE_PID0_OFF (BOOKE_PIR_OFF + STRIDE_SIZE) +#define BOOKE_BUCSR_OFF (BOOKE_PID0_OFF + STRIDE_SIZE) + +#define BUFFER_SIZE (BOOKE_BUCSR_OFF + STRIDE_SIZE) + +#undef SAVE_GPR +#define SAVE_GPR(gpr, offset) \ + PPC_STL gpr, offset(r10) + +#define RESTORE_GPR(gpr, offset) \ + PPC_LL gpr, offset(r10) + +#define SAVE_SPR(spr, offset) \ + mfspr r0, spr ;\ + PPC_STL r0, offset(r10) + +#define RESTORE_SPR(spr, offset) \ + PPC_LL r0, offset(r10) ;\ + mtspr spr, r0 + +#define SAVE_ALL_GPR \ + SAVE_GPR(r1, BOOKE_GPR0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_GPR(r2, BOOKE_GPR0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_GPR(r13, BOOKE_GPR0_OFF + STRIDE_SIZE * 13) ;\ + SAVE_GPR(r14, BOOKE_GPR0_OFF + STRIDE_SIZE * 14) ;\ + SAVE_GPR(r15, BOOKE_GPR0_OFF + STRIDE_SIZE * 15) ;\ + SAVE_GPR(r16, BOOKE_GPR0_OFF + STRIDE_SIZE * 16) ;\ + SAVE_GPR(r17, BOOKE_GPR0_OFF + STRIDE_SIZE * 17) ;\ + SAVE_GPR(r18, BOOKE_GPR0_OFF + STRIDE_SIZE * 18) ;\ + SAVE_GPR(r19, BOOKE_GPR0_OFF + STRIDE_SIZE * 19) ;\ + SAVE_GPR(r20, BOOKE_GPR0_OFF + STRIDE_SIZE * 20) ;\ + SAVE_GPR(r21, BOOKE_GPR0_OFF + STRIDE_SIZE * 21) ;\ + SAVE_GPR(r22, BOOKE_GPR0_OFF + STRIDE_SIZE * 22) ;\ + SAVE_GPR(r23, BOOKE_GPR0_OFF + STRIDE_SIZE * 23) ;\ + SAVE_GPR(r24, BOOKE_GPR0_OFF + STRIDE_SIZE * 24) ;\ + SAVE_GPR(r25, BOOKE_GPR0_OFF + STRIDE_SIZE * 25) ;\ + SAVE_GPR(r26, BOOKE_GPR0_OFF + STRIDE_SIZE * 26) ;\ + SAVE_GPR(r27, BOOKE_GPR0_OFF + STRIDE_SIZE * 27) ;\ + SAVE_GPR(r28, BOOKE_GPR0_OFF + STRIDE_SIZE * 28) ;\ + SAVE_GPR(r29, BOOKE_GPR0_OFF + STRIDE_SIZE * 29) ;\ + SAVE_GPR(r30, BOOKE_GPR0_OFF + STRIDE_SIZE * 30) ;\ + SAVE_GPR(r31, BOOKE_GPR0_OFF + STRIDE_SIZE * 31) + +#define RESTORE_ALL_GPR \ + RESTORE_GPR(r1, BOOKE_GPR0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_GPR(r2, BOOKE_GPR0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_GPR(r13, BOOKE_GPR0_OFF + STRIDE_SIZE * 13) ;\ + RESTORE_GPR(r14, BOOKE_GPR0_OFF + STRIDE_SIZE * 14) ;\ + RESTORE_GPR(r15, BOOKE_GPR0_OFF + STRIDE_SIZE * 15) ;\ + RESTORE_GPR(r16, BOOKE_GPR0_OFF + STRIDE_SIZE * 16) ;\ + RESTORE_GPR(r17, BOOKE_GPR0_OFF + STRIDE_SIZE * 17) ;\ + RESTORE_GPR(r18, BOOKE_GPR0_OFF + STRIDE_SIZE * 18) ;\ + RESTORE_GPR(r19, BOOKE_GPR0_OFF + STRIDE_SIZE * 19) ;\ + RESTORE_GPR(r20, BOOKE_GPR0_OFF + STRIDE_SIZE * 20) ;\ + RESTORE_GPR(r21, BOOKE_GPR0_OFF + STRIDE_SIZE * 21) ;\ + RESTORE_GPR(r22, BOOKE_GPR0_OFF + STRIDE_SIZE * 22) ;\ + RESTORE_GPR(r23, BOOKE_GPR0_OFF + STRIDE_SIZE * 23) ;\ + RESTORE_GPR(r24, BOOKE_GPR0_OFF + STRIDE_SIZE * 24) ;\ + RESTORE_GPR(r25, BOOKE_GPR0_OFF + STRIDE_SIZE * 25) ;\ + RESTORE_GPR(r26, BOOKE_GPR0_OFF + STRIDE_SIZE * 26) ;\ + RESTORE_GPR(r27, BOOKE_GPR0_OFF + STRIDE_SIZE * 27) ;\ + RESTORE_GPR(r28, BOOKE_GPR0_OFF + STRIDE_SIZE * 28) ;\ + RESTORE_GPR(r29, BOOKE_GPR0_OFF + STRIDE_SIZE * 29) ;\ + RESTORE_GPR(r30, BOOKE_GPR0_OFF + STRIDE_SIZE * 30) ;\ + RESTORE_GPR(r31, BOOKE_GPR0_OFF + STRIDE_SIZE * 31) + +#define SAVE_ALL_SPRG \ + SAVE_SPR(SPRN_SPRG0, BOOKE_SPRG0_OFF + STRIDE_SIZE * 0) ;\ + SAVE_SPR(SPRN_SPRG1, BOOKE_SPRG0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_SPR(SPRN_SPRG2, BOOKE_SPRG0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_SPR(SPRN_SPRG3, BOOKE_SPRG0_OFF + STRIDE_SIZE * 3) ;\ + SAVE_SPR(SPRN_SPRG4, BOOKE_SPRG0_OFF + STRIDE_SIZE * 4) ;\ + SAVE_SPR(SPRN_SPRG5, BOOKE_SPRG0_OFF + STRIDE_SIZE * 5) ;\ + SAVE_SPR(SPRN_SPRG6, BOOKE_SPRG0_OFF + STRIDE_SIZE * 6) ;\ + SAVE_SPR(SPRN_SPRG7, BOOKE_SPRG0_OFF + STRIDE_SIZE * 7) ;\ + SAVE_SPR(SPRN_SPRG8, BOOKE_SPRG0_OFF + STRIDE_SIZE * 8) ;\ + SAVE_SPR(SPRN_SPRG9, BOOKE_SPRG0_OFF + STRIDE_SIZE * 9) + +#define RESTORE_ALL_SPRG \ + RESTORE_SPR(SPRN_SPRG0, BOOKE_SPRG0_OFF + STRIDE_SIZE * 0) ;\ + RESTORE_SPR(SPRN_SPRG1, BOOKE_SPRG0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_SPR(SPRN_SPRG2, BOOKE_SPRG0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_SPR(SPRN_SPRG3, BOOKE_SPRG0_OFF + STRIDE_SIZE * 3) ;\ + RESTORE_SPR(SPRN_SPRG4, BOOKE_SPRG0_OFF + STRIDE_SIZE * 4) ;\ + RESTORE_SPR(SPRN_SPRG5, BOOKE_SPRG0_OFF + STRIDE_SIZE * 5) ;\ + RESTORE_SPR(SPRN_SPRG6, BOOKE_SPRG0_OFF + STRIDE_SIZE * 6) ;\ + RESTORE_SPR(SPRN_SPRG7, BOOKE_SPRG0_OFF + STRIDE_SIZE * 7) ;\ + RESTORE_SPR(SPRN_SPRG8, BOOKE_SPRG0_OFF + STRIDE_SIZE * 8) ;\ + RESTORE_SPR(SPRN_SPRG9, BOOKE_SPRG0_OFF + STRIDE_SIZE * 9) + +#define SAVE_ALL_IVOR \ + SAVE_SPR(SPRN_IVOR0, BOOKE_IVOR0_OFF + STRIDE_SIZE * 0) ;\ + SAVE_SPR(SPRN_IVOR1, BOOKE_IVOR0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_SPR(SPRN_IVOR2, BOOKE_IVOR0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_SPR(SPRN_IVOR3, BOOKE_IVOR0_OFF + STRIDE_SIZE * 3) ;\ + SAVE_SPR(SPRN_IVOR4, BOOKE_IVOR0_OFF + STRIDE_SIZE * 4) ;\ + SAVE_SPR(SPRN_IVOR5, BOOKE_IVOR0_OFF + STRIDE_SIZE * 5) ;\ + SAVE_SPR(SPRN_IVOR6, BOOKE_IVOR0_OFF + STRIDE_SIZE * 6) ;\ + SAVE_SPR(SPRN_IVOR7, BOOKE_IVOR0_OFF + STRIDE_SIZE * 7) ;\ + SAVE_SPR(SPRN_IVOR8, BOOKE_IVOR0_OFF + STRIDE_SIZE * 8) ;\ + SAVE_SPR(SPRN_IVOR9, BOOKE_IVOR0_OFF + STRIDE_SIZE * 9) ;\ + SAVE_SPR(SPRN_IVOR10, BOOKE_IVOR0_OFF + STRIDE_SIZE * 10) ;\ + SAVE_SPR(SPRN_IVOR11, BOOKE_IVOR0_OFF + STRIDE_SIZE * 11) ;\ + SAVE_SPR(SPRN_IVOR12, BOOKE_IVOR0_OFF + STRIDE_SIZE * 12) ;\ + SAVE_SPR(SPRN_IVOR13, BOOKE_IVOR0_OFF + STRIDE_SIZE * 13) ;\ + SAVE_SPR(SPRN_IVOR14, BOOKE_IVOR0_OFF + STRIDE_SIZE * 14) ;\ + SAVE_SPR(SPRN_IVOR15, BOOKE_IVOR0_OFF + STRIDE_SIZE * 15) ;\ + SAVE_SPR(SPRN_IVOR35, BOOKE_IVOR0_OFF + STRIDE_SIZE * 35) ;\ + SAVE_SPR(SPRN_IVOR36, BOOKE_IVOR0_OFF + STRIDE_SIZE * 36) ;\ + SAVE_SPR(SPRN_IVOR37, BOOKE_IVOR0_OFF + STRIDE_SIZE * 37) ;\ + SAVE_SPR(SPRN_IVOR38, BOOKE_IVOR0_OFF + STRIDE_SIZE * 38) ;\ + SAVE_SPR(SPRN_IVOR39, BOOKE_IVOR0_OFF + STRIDE_SIZE * 39) ;\ + SAVE_SPR(SPRN_IVOR40, BOOKE_IVOR0_OFF + STRIDE_SIZE * 40) ;\ + SAVE_SPR(SPRN_IVOR41, BOOKE_IVOR0_OFF + STRIDE_SIZE * 41) + +#define RESTORE_ALL_IVOR \ + RESTORE_SPR(SPRN_IVOR0, BOOKE_IVOR0_OFF + STRIDE_SIZE * 0) ;\ + RESTORE_SPR(SPRN_IVOR1, BOOKE_IVOR0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_SPR(SPRN_IVOR2, BOOKE_IVOR0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_SPR(SPRN_IVOR3, BOOKE_IVOR0_OFF + STRIDE_SIZE * 3) ;\ + RESTORE_SPR(SPRN_IVOR4, BOOKE_IVOR0_OFF + STRIDE_SIZE * 4) ;\ + RESTORE_SPR(SPRN_IVOR5, BOOKE_IVOR0_OFF + STRIDE_SIZE * 5) ;\ + RESTORE_SPR(SPRN_IVOR6, BOOKE_IVOR0_OFF + STRIDE_SIZE * 6) ;\ + RESTORE_SPR(SPRN_IVOR7, BOOKE_IVOR0_OFF + STRIDE_SIZE * 7) ;\ + RESTORE_SPR(SPRN_IVOR8, BOOKE_IVOR0_OFF + STRIDE_SIZE * 8) ;\ + RESTORE_SPR(SPRN_IVOR9, BOOKE_IVOR0_OFF + STRIDE_SIZE * 9) ;\ + RESTORE_SPR(SPRN_IVOR10, BOOKE_IVOR0_OFF + STRIDE_SIZE * 10) ;\ + RESTORE_SPR(SPRN_IVOR11, BOOKE_IVOR0_OFF + STRIDE_SIZE * 11) ;\ + RESTORE_SPR(SPRN_IVOR12, BOOKE_IVOR0_OFF + STRIDE_SIZE * 12) ;\ + RESTORE_SPR(SPRN_IVOR13, BOOKE_IVOR0_OFF + STRIDE_SIZE * 13) ;\ + RESTORE_SPR(SPRN_IVOR14, BOOKE_IVOR0_OFF + STRIDE_SIZE * 14) ;\ + RESTORE_SPR(SPRN_IVOR15, BOOKE_IVOR0_OFF + STRIDE_SIZE * 15) ;\ + RESTORE_SPR(SPRN_IVOR35, BOOKE_IVOR0_OFF + STRIDE_SIZE * 35) ;\ + RESTORE_SPR(SPRN_IVOR36, BOOKE_IVOR0_OFF + STRIDE_SIZE * 36) ;\ + RESTORE_SPR(SPRN_IVOR37, BOOKE_IVOR0_OFF + STRIDE_SIZE * 37) ;\ + RESTORE_SPR(SPRN_IVOR38, BOOKE_IVOR0_OFF + STRIDE_SIZE * 38) ;\ + RESTORE_SPR(SPRN_IVOR39, BOOKE_IVOR0_OFF + STRIDE_SIZE * 39) ;\ + RESTORE_SPR(SPRN_IVOR40, BOOKE_IVOR0_OFF + STRIDE_SIZE * 40) ;\ + RESTORE_SPR(SPRN_IVOR41, BOOKE_IVOR0_OFF + STRIDE_SIZE * 41) + +/* reset time base to prevent from overflow */ +#define DELAY(count) \ + li r3, count; \ + li r4, 0; \ + mtspr SPRN_TBWL, r4; \ +101: mfspr r4, SPRN_TBRL; \ + cmpw r4, r3; \ + blt 101b + +#define FSL_DIS_ALL_IRQ \ + mfmsr r8; \ + rlwinm r8, r8, 0, ~MSR_CE; \ + rlwinm r8, r8, 0, ~MSR_ME; \ + rlwinm r8, r8, 0, ~MSR_EE; \ + rlwinm r8, r8, 0, ~MSR_DE; \ + mtmsr r8; \ + isync + +#ifndef CONFIG_PPC_E500MC +#define SS_TB 0x00 +#define SS_HID 0x08 /* 2 HIDs */ +#define SS_IAC 0x10 /* 2 IACs */ +#define SS_DAC 0x18 /* 2 DACs */ +#define SS_DBCR 0x20 /* 3 DBCRs */ +#define SS_PID 0x2c /* 3 PIDs */ +#define SS_SPRG 0x38 /* 8 SPRGs */ +#define SS_IVOR 0x58 /* 20 interrupt vectors */ +#define SS_TCR 0xa8 +#define SS_BUCSR 0xac +#define SS_L1CSR 0xb0 /* 2 L1CSRs */ +#define SS_MSR 0xb8 +#define SS_USPRG 0xbc +#define SS_GPREG 0xc0 /* r12-r31 */ +#define SS_LR 0x110 +#define SS_CR 0x114 +#define SS_SP 0x118 +#define SS_CURRENT 0x11c +#define SS_IVPR 0x120 +#define SS_BPTR 0x124 + + +#define STATE_SAVE_SIZE 0x128 + + .section .data + .align 5 +mpc85xx_sleep_save_area: + .space STATE_SAVE_SIZE +ccsrbase_low: + .long 0 +ccsrbase_high: + .long 0 +powmgtreq: + .long 0 + + .section .text + .align 12 + + /* + * r3 = high word of physical address of CCSR + * r4 = low word of physical address of CCSR + * r5 = JOG or deep sleep request + * JOG-0x00200000, deep sleep-0x00100000 + */ +_GLOBAL(mpc85xx_enter_deep_sleep) + lis r6, ccsrbase_low@ha + stw r4, ccsrbase_low@l(r6) + lis r6, ccsrbase_high@ha + stw r3, ccsrbase_high@l(r6) + + lis r6, powmgtreq@ha + stw r5, powmgtreq@l(r6) + + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + mfspr r5, SPRN_HID0 + mfspr r6, SPRN_HID1 + + stw r5, SS_HID+0(r10) + stw r6, SS_HID+4(r10) + + mfspr r4, SPRN_IAC1 + mfspr r5, SPRN_IAC2 + mfspr r6, SPRN_DAC1 + mfspr r7, SPRN_DAC2 + + stw r4, SS_IAC+0(r10) + stw r5, SS_IAC+4(r10) + stw r6, SS_DAC+0(r10) + stw r7, SS_DAC+4(r10) + + mfspr r4, SPRN_DBCR0 + mfspr r5, SPRN_DBCR1 + mfspr r6, SPRN_DBCR2 + + stw r4, SS_DBCR+0(r10) + stw r5, SS_DBCR+4(r10) + stw r6, SS_DBCR+8(r10) + + mfspr r4, SPRN_PID0 + mfspr r5, SPRN_PID1 + mfspr r6, SPRN_PID2 + + stw r4, SS_PID+0(r10) + stw r5, SS_PID+4(r10) + stw r6, SS_PID+8(r10) + + mfspr r4, SPRN_SPRG0 + mfspr r5, SPRN_SPRG1 + mfspr r6, SPRN_SPRG2 + mfspr r7, SPRN_SPRG3 + + stw r4, SS_SPRG+0x00(r10) + stw r5, SS_SPRG+0x04(r10) + stw r6, SS_SPRG+0x08(r10) + stw r7, SS_SPRG+0x0c(r10) + + mfspr r4, SPRN_SPRG4 + mfspr r5, SPRN_SPRG5 + mfspr r6, SPRN_SPRG6 + mfspr r7, SPRN_SPRG7 + + stw r4, SS_SPRG+0x10(r10) + stw r5, SS_SPRG+0x14(r10) + stw r6, SS_SPRG+0x18(r10) + stw r7, SS_SPRG+0x1c(r10) + + mfspr r4, SPRN_IVPR + stw r4, SS_IVPR(r10) + + mfspr r4, SPRN_IVOR0 + mfspr r5, SPRN_IVOR1 + mfspr r6, SPRN_IVOR2 + mfspr r7, SPRN_IVOR3 + + stw r4, SS_IVOR+0x00(r10) + stw r5, SS_IVOR+0x04(r10) + stw r6, SS_IVOR+0x08(r10) + stw r7, SS_IVOR+0x0c(r10) + + mfspr r4, SPRN_IVOR4 + mfspr r5, SPRN_IVOR5 + mfspr r6, SPRN_IVOR6 + mfspr r7, SPRN_IVOR7 + + stw r4, SS_IVOR+0x10(r10) + stw r5, SS_IVOR+0x14(r10) + stw r6, SS_IVOR+0x18(r10) + stw r7, SS_IVOR+0x1c(r10) + + mfspr r4, SPRN_IVOR8 + mfspr r5, SPRN_IVOR9 + mfspr r6, SPRN_IVOR10 + mfspr r7, SPRN_IVOR11 + + stw r4, SS_IVOR+0x20(r10) + stw r5, SS_IVOR+0x24(r10) + stw r6, SS_IVOR+0x28(r10) + stw r7, SS_IVOR+0x2c(r10) + + mfspr r4, SPRN_IVOR12 + mfspr r5, SPRN_IVOR13 + mfspr r6, SPRN_IVOR14 + mfspr r7, SPRN_IVOR15 + + stw r4, SS_IVOR+0x30(r10) + stw r5, SS_IVOR+0x34(r10) + stw r6, SS_IVOR+0x38(r10) + stw r7, SS_IVOR+0x3c(r10) + + mfspr r4, SPRN_IVOR32 + mfspr r5, SPRN_IVOR33 + mfspr r6, SPRN_IVOR34 + mfspr r7, SPRN_IVOR35 + + stw r4, SS_IVOR+0x40(r10) + stw r5, SS_IVOR+0x44(r10) + stw r6, SS_IVOR+0x48(r10) + stw r7, SS_IVOR+0x4c(r10) + + mfspr r4, SPRN_TCR + mfspr r5, SPRN_BUCSR + mfspr r6, SPRN_L1CSR0 + mfspr r7, SPRN_L1CSR1 + mfspr r8, SPRN_USPRG0 + + stw r4, SS_TCR(r10) + stw r5, SS_BUCSR(r10) + stw r6, SS_L1CSR+0(r10) + stw r7, SS_L1CSR+4(r10) + stw r8, SS_USPRG+0(r10) + + stmw r12, SS_GPREG(r10) + + mfmsr r4 + mflr r5 + mfcr r6 + + stw r4, SS_MSR(r10) + stw r5, SS_LR(r10) + stw r6, SS_CR(r10) + stw r1, SS_SP(r10) + stw r2, SS_CURRENT(r10) + +1: mftbu r4 + mftb r5 + mftbu r6 + cmpw r4, r6 + bne 1b + + stw r4, SS_TB+0(r10) + stw r5, SS_TB+4(r10) + + lis r5, ccsrbase_low@ha + lwz r4, ccsrbase_low@l(r5) + lis r5, ccsrbase_high@ha + lwz r3, ccsrbase_high@l(r5) + + /* Disable machine checks and critical exceptions */ + mfmsr r5 + rlwinm r5, r5, 0, ~MSR_CE + rlwinm r5, r5, 0, ~MSR_ME + mtmsr r5 + isync + + /* Use TLB1[15] to map the CCSR at 0xf0000000 */ + lis r5, 0x100f + mtspr SPRN_MAS0, r5 + lis r5, 0xc000 + ori r5, r5, 0x0500 + mtspr SPRN_MAS1, r5 + lis r5, 0xf000 + ori r5, r5, 0x000a + mtspr SPRN_MAS2, r5 + rlwinm r5, r4, 0, 0xfffff000 + ori r5, r5, 0x0005 + mtspr SPRN_MAS3, r5 + mtspr SPRN_MAS7, r3 + isync + tlbwe + isync + + lis r3, 0xf000 + lwz r4, 0x20(r3) + stw r4, SS_BPTR(r10) + + lis r3, 0xf002 /* L2 cache controller at CCSR+0x20000 */ + bl flush_disable_L2 + bl __flush_disable_L1 + + /* Enable I-cache, so as not to upset the bus + * with our loop. + */ + + mfspr r4, SPRN_L1CSR1 + ori r4, r4, 1 + mtspr SPRN_L1CSR1, r4 + isync + + /* Set boot page translation */ + lis r3, 0xf000 + lis r4, (mpc85xx_deep_resume - PAGE_OFFSET)@h + ori r4, r4, (mpc85xx_deep_resume - PAGE_OFFSET)@l + rlwinm r4, r4, 20, 0x000fffff + oris r4, r4, 0x8000 + stw r4, 0x20(r3) + lwz r4, 0x20(r3) /* read-back to flush write */ + twi 0, r4, 0 + isync + + /* Disable the decrementer */ + mfspr r4, SPRN_TCR + rlwinm r4, r4, 0, ~TCR_DIE + mtspr SPRN_TCR, r4 + + mfspr r4, SPRN_TSR + oris r4, r4, TSR_DIS@h + mtspr SPRN_TSR, r4 + + /* set PMRCCR[VRCNT] to wait power stable for 40ms */ + lis r3, 0xf00e + lwz r4, 0x84(r3) + clrlwi r4, r4, 16 + oris r4, r4, 0x12a3 + stw r4, 0x84(r3) + lwz r4, 0x84(r3) + + /* set deep sleep bit in POWMGTSCR */ + lis r3, powmgtreq@ha + lwz r8, powmgtreq@l(r3) + + lis r3, 0xf00e + lwz r4, 0x80(r3) + or r4, r4, r8 + stw r4, 0x80(r3) + lwz r4, 0x80(r3) /* read-back to flush write */ + twi 0, r4, 0 + isync + + mftb r5 +1: /* spin until either we enter deep sleep, or the sleep process is + * aborted due to a pending wakeup event. Wait some time between + * accesses, so we don't flood the bus and prevent the pmc from + * detecting an idle system. + */ + + mftb r4 + subf r7, r5, r4 + cmpwi r7, 1000 + blt 1b + mr r5, r4 + + lwz r6, 0x80(r3) + andis. r6, r6, 0x0010 + bne 1b + b 2f + +2: mfspr r4, SPRN_PIR + andi. r4, r4, 1 +99: bne 99b + + /* Establish a temporary 64MB 0->0 mapping in TLB1[1]. */ + lis r4, 0x1001 + mtspr SPRN_MAS0, r4 + lis r4, 0xc000 + ori r4, r4, 0x0800 + mtspr SPRN_MAS1, r4 + li r4, 0 + mtspr SPRN_MAS2, r4 + li r4, 0x0015 + mtspr SPRN_MAS3, r4 + li r4, 0 + mtspr SPRN_MAS7, r4 + isync + tlbwe + isync + + lis r3, (3f - PAGE_OFFSET)@h + ori r3, r3, (3f - PAGE_OFFSET)@l + mtctr r3 + bctr + + /* Locate the resume vector in the last word of the current page. */ + . = mpc85xx_enter_deep_sleep + 0xffc +mpc85xx_deep_resume: + b 2b + +3: + /* Restore the contents of TLB1[0]. It is assumed that it covers + * the currently executing code and the sleep save area, and that + * it does not alias our temporary mapping (which is at virtual zero). + */ + lis r3, (TLBCAM - PAGE_OFFSET)@h + ori r3, r3, (TLBCAM - PAGE_OFFSET)@l + + lwz r4, 0(r3) + lwz r5, 4(r3) + lwz r6, 8(r3) + lwz r7, 12(r3) + lwz r8, 16(r3) + + mtspr SPRN_MAS0, r4 + mtspr SPRN_MAS1, r5 + mtspr SPRN_MAS2, r6 + mtspr SPRN_MAS3, r7 + mtspr SPRN_MAS7, r8 + + isync + tlbwe + isync + + /* Access the ccsrbase address with TLB1[0] */ + lis r5, ccsrbase_low@ha + lwz r4, ccsrbase_low@l(r5) + lis r5, ccsrbase_high@ha + lwz r3, ccsrbase_high@l(r5) + + /* Use TLB1[15] to map the CCSR at 0xf0000000 */ + lis r5, 0x100f + mtspr SPRN_MAS0, r5 + lis r5, 0xc000 + ori r5, r5, 0x0500 + mtspr SPRN_MAS1, r5 + lis r5, 0xf000 + ori r5, r5, 0x000a + mtspr SPRN_MAS2, r5 + rlwinm r5, r4, 0, 0xfffff000 + ori r5, r5, 0x0005 + mtspr SPRN_MAS3, r5 + mtspr SPRN_MAS7, r3 + isync + tlbwe + isync + + lis r3, 0xf002 /* L2 cache controller at CCSR+0x20000 */ + bl invalidate_enable_L2 + + /* Access the MEM(r10) with TLB1[0] */ + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + lis r3, 0xf000 + lwz r4, SS_BPTR(r10) + stw r4, 0x20(r3) /* restore BPTR */ + + /* Program shift running space to PAGE_OFFSET */ + mfmsr r3 + lis r4, 1f@h + ori r4, r4, 1f@l + + mtsrr1 r3 + mtsrr0 r4 + rfi + +1: /* Restore the rest of TLB1, in ascending order so that + * the TLB1[1] gets invalidated first. + * + * XXX: It's better to invalidate the temporary mapping + * TLB1[15] for CCSR before restore any TLB1 entry include 0. + */ + lis r4, 0x100f + mtspr SPRN_MAS0, r4 + lis r4, 0 + mtspr SPRN_MAS1, r4 + isync + tlbwe + isync + + lis r3, (TLBCAM + 5*4 - 4)@h + ori r3, r3, (TLBCAM + 5*4 - 4)@l + li r4, 15 + mtctr r4 + +2: + lwz r5, 4(r3) + lwz r6, 8(r3) + lwz r7, 12(r3) + lwz r8, 16(r3) + lwzu r9, 20(r3) + + mtspr SPRN_MAS0, r5 + mtspr SPRN_MAS1, r6 + mtspr SPRN_MAS2, r7 + mtspr SPRN_MAS3, r8 + mtspr SPRN_MAS7, r9 + + isync + tlbwe + isync + bdnz 2b + + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + lwz r5, SS_HID+0(r10) + lwz r6, SS_HID+4(r10) + + isync + mtspr SPRN_HID0, r5 + isync + + msync + mtspr SPRN_HID1, r6 + isync + + lwz r4, SS_IAC+0(r10) + lwz r5, SS_IAC+4(r10) + lwz r6, SS_DAC+0(r10) + lwz r7, SS_DAC+4(r10) + + mtspr SPRN_IAC1, r4 + mtspr SPRN_IAC2, r5 + mtspr SPRN_DAC1, r6 + mtspr SPRN_DAC2, r7 + + lwz r4, SS_DBCR+0(r10) + lwz r5, SS_DBCR+4(r10) + lwz r6, SS_DBCR+8(r10) + + mtspr SPRN_DBCR0, r4 + mtspr SPRN_DBCR1, r5 + mtspr SPRN_DBCR2, r6 + + lwz r4, SS_PID+0(r10) + lwz r5, SS_PID+4(r10) + lwz r6, SS_PID+8(r10) + + mtspr SPRN_PID0, r4 + mtspr SPRN_PID1, r5 + mtspr SPRN_PID2, r6 + + lwz r4, SS_SPRG+0x00(r10) + lwz r5, SS_SPRG+0x04(r10) + lwz r6, SS_SPRG+0x08(r10) + lwz r7, SS_SPRG+0x0c(r10) + + mtspr SPRN_SPRG0, r4 + mtspr SPRN_SPRG1, r5 + mtspr SPRN_SPRG2, r6 + mtspr SPRN_SPRG3, r7 + + lwz r4, SS_SPRG+0x10(r10) + lwz r5, SS_SPRG+0x14(r10) + lwz r6, SS_SPRG+0x18(r10) + lwz r7, SS_SPRG+0x1c(r10) + + mtspr SPRN_SPRG4, r4 + mtspr SPRN_SPRG5, r5 + mtspr SPRN_SPRG6, r6 + mtspr SPRN_SPRG7, r7 + + lwz r4, SS_IVPR(r10) + mtspr SPRN_IVPR, r4 + + lwz r4, SS_IVOR+0x00(r10) + lwz r5, SS_IVOR+0x04(r10) + lwz r6, SS_IVOR+0x08(r10) + lwz r7, SS_IVOR+0x0c(r10) + + mtspr SPRN_IVOR0, r4 + mtspr SPRN_IVOR1, r5 + mtspr SPRN_IVOR2, r6 + mtspr SPRN_IVOR3, r7 + + lwz r4, SS_IVOR+0x10(r10) + lwz r5, SS_IVOR+0x14(r10) + lwz r6, SS_IVOR+0x18(r10) + lwz r7, SS_IVOR+0x1c(r10) + + mtspr SPRN_IVOR4, r4 + mtspr SPRN_IVOR5, r5 + mtspr SPRN_IVOR6, r6 + mtspr SPRN_IVOR7, r7 + + lwz r4, SS_IVOR+0x20(r10) + lwz r5, SS_IVOR+0x24(r10) + lwz r6, SS_IVOR+0x28(r10) + lwz r7, SS_IVOR+0x2c(r10) + + mtspr SPRN_IVOR8, r4 + mtspr SPRN_IVOR9, r5 + mtspr SPRN_IVOR10, r6 + mtspr SPRN_IVOR11, r7 + + lwz r4, SS_IVOR+0x30(r10) + lwz r5, SS_IVOR+0x34(r10) + lwz r6, SS_IVOR+0x38(r10) + lwz r7, SS_IVOR+0x3c(r10) + + mtspr SPRN_IVOR12, r4 + mtspr SPRN_IVOR13, r5 + mtspr SPRN_IVOR14, r6 + mtspr SPRN_IVOR15, r7 + + lwz r4, SS_IVOR+0x40(r10) + lwz r5, SS_IVOR+0x44(r10) + lwz r6, SS_IVOR+0x48(r10) + lwz r7, SS_IVOR+0x4c(r10) + + mtspr SPRN_IVOR32, r4 + mtspr SPRN_IVOR33, r5 + mtspr SPRN_IVOR34, r6 + mtspr SPRN_IVOR35, r7 + + lwz r4, SS_TCR(r10) + lwz r5, SS_BUCSR(r10) + lwz r6, SS_L1CSR+0(r10) + lwz r7, SS_L1CSR+4(r10) + lwz r8, SS_USPRG+0(r10) + + mtspr SPRN_TCR, r4 + mtspr SPRN_BUCSR, r5 + + msync + isync + mtspr SPRN_L1CSR0, r6 + isync + + mtspr SPRN_L1CSR1, r7 + isync + + mtspr SPRN_USPRG0, r8 + + lmw r12, SS_GPREG(r10) + + lwz r1, SS_SP(r10) + lwz r2, SS_CURRENT(r10) + lwz r4, SS_MSR(r10) + lwz r5, SS_LR(r10) + lwz r6, SS_CR(r10) + + msync + mtmsr r4 + isync + + mtlr r5 + mtcr r6 + + li r4, 0 + mtspr SPRN_TBWL, r4 + + lwz r4, SS_TB+0(r10) + lwz r5, SS_TB+4(r10) + + mtspr SPRN_TBWU, r4 + mtspr SPRN_TBWL, r5 + + lis r3, 1 + mtdec r3 + + blr + +#else /* CONFIG_PPC_E500MC */ + + .section .data + .align 6 +regs_buffer: + .space BUFFER_SIZE + + .section .text +/* + * Save CPU registers + * r3 : the base address of the buffer which stores the values of registers + */ +e5500_cpu_state_save: + /* store the base address to r10 */ + mr r10, r3 + + SAVE_ALL_GPR + SAVE_ALL_SPRG + SAVE_ALL_IVOR + + SAVE_SPR(SPRN_IVPR, BOOKE_IVPR_OFF) + SAVE_SPR(SPRN_PID0, BOOKE_PID0_OFF) + SAVE_SPR(SPRN_EPCR, BOOKE_EPCR_OFF) + SAVE_SPR(SPRN_HID0, BOOKE_HID0_OFF) + SAVE_SPR(SPRN_PIR, BOOKE_PIR_OFF) + SAVE_SPR(SPRN_BUCSR, BOOKE_BUCSR_OFF) +1: + mfspr r5, SPRN_TBRU + mfspr r4, SPRN_TBRL + SAVE_GPR(r5, BOOKE_TBU_OFF) + SAVE_GPR(r4, BOOKE_TBL_OFF) + mfspr r3, SPRN_TBRU + cmpw r3, r5 + bne 1b + + blr + +/* + * Restore CPU registers + * r3 : the base address of the buffer which stores the values of registers + */ +e5500_cpu_state_restore: + /* store the base address to r10 */ + mr r10, r3 + + RESTORE_ALL_GPR + RESTORE_ALL_SPRG + RESTORE_ALL_IVOR + + RESTORE_SPR(SPRN_IVPR, BOOKE_IVPR_OFF) + RESTORE_SPR(SPRN_PID0, BOOKE_PID0_OFF) + RESTORE_SPR(SPRN_EPCR, BOOKE_EPCR_OFF) + RESTORE_SPR(SPRN_HID0, BOOKE_HID0_OFF) + RESTORE_SPR(SPRN_PIR, BOOKE_PIR_OFF) + RESTORE_SPR(SPRN_BUCSR, BOOKE_BUCSR_OFF) + + li r0, 0 + mtspr SPRN_TBWL, r0 + RESTORE_SPR(SPRN_TBWU, BOOKE_TBU_OFF) + RESTORE_SPR(SPRN_TBWL, BOOKE_TBL_OFF) + + blr + +#define CPC_CPCCSR0 0x0 +#define CPC_CPCCSR0_CPCFL 0x800 + +/* + * Flush the CPC cache. + * r3 : the base address of CPC + */ +flush_cpc_cache: + lwz r6, CPC_CPCCSR0(r3) + ori r6, r6, CPC_CPCCSR0_CPCFL + stw r6, CPC_CPCCSR0(r3) + sync + + /* Wait until completing the flush */ +1: lwz r6, CPC_CPCCSR0(r3) + andi. r6, r6, CPC_CPCCSR0_CPCFL + bne 1b + + blr + +/* + * the last stage to enter deep sleep + * + */ + .align 6 +_GLOBAL(fsl_dp_enter_low) +deepsleep_start: + LOAD_REG_ADDR(r9, buf_tmp) + /* save the return address and MSR */ + mflr r8 + PPC_STL r8, 0(r9) + mfmsr r8 + PPC_STL r8, 8(r9) + mfspr r8, SPRN_TCR + PPC_STL r8, 16(r9) + mfcr r8 + PPC_STL r8, 24(r9) + li r8, 0 + mtspr SPRN_TCR, r8 + + /* save the parameters */ + PPC_STL r3, 32(r9) + PPC_STL r4, 40(r9) + PPC_STL r5, 48(r9) + PPC_STL r6, 56(r9) + + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_save + + /* restore the parameters */ + LOAD_REG_ADDR(r9, buf_tmp) + PPC_LL r31, 32(r9) + PPC_LL r30, 40(r9) + PPC_LL r29, 48(r9) + PPC_LL r28, 56(r9) + + /* flush caches inside CPU */ + LOAD_REG_ADDR(r3, cur_cpu_spec) + PPC_LL r3, 0(r3) + PPC_LL r3, CPU_FLUSH_CACHES(r3) + PPC_LCMPI 0, r3, 0 + beq 6f +#ifdef CONFIG_PPC64 + PPC_LL r3, 0(r3) +#endif + mtctr r3 + bctrl +6: + /* Flush the CPC cache */ +#define CPC_OFFSET 0x10000 + mr r3, r31 + addis r3, r3, CPC_OFFSET@h + bl flush_cpc_cache + + /* prefecth TLB */ +#define CCSR_GPIO1_GPDAT 0x130008 +#define CCSR_GPIO1_GPDAT_29 0x4 + LOAD_REG_IMMEDIATE(r11, CCSR_GPIO1_GPDAT) + add r11, r31, r11 + lwz r10, 0(r11) + +#define CCSR_RCPM_PCPH15SETR 0xe20b4 +#define CCSR_RCPM_PCPH15SETR_CORE0 0x1 + LOAD_REG_IMMEDIATE(r12, CCSR_RCPM_PCPH15SETR) + add r12, r31, r12 + lwz r10, 0(r12) + +#define CCSR_DDR_SDRAM_CFG_2 0x8114 +#define CCSR_DDR_SDRAM_CFG_2_FRC_SR 0x80000000 + LOAD_REG_IMMEDIATE(r13, CCSR_DDR_SDRAM_CFG_2) + add r13, r31, r13 + lwz r10, 0(r13) + +#define DCSR_EPU_EPGCR 0x000 +#define DCSR_EPU_EPGCR_GCE 0x80000000 + li r14, DCSR_EPU_EPGCR + add r14, r30, r14 + lwz r10, 0(r14) + +#define DCSR_EPU_EPECR15 0x33C +#define DCSR_EPU_EPECR15_IC0 0x80000000 + li r15, DCSR_EPU_EPECR15 + add r15, r30, r15 + lwz r10, 0(r15) + +#define CCSR_SCFG_QMIFRSTCR 0xfc40c +#define CCSR_SCFG_QMIFRSTCR_QMIFRST 0x80000000 + LOAD_REG_IMMEDIATE(r16, CCSR_SCFG_QMIFRSTCR) + add r16, r31, r16 + lwz r10, 0(r16) + +/* + * There are two kind of register maps, one for T1040QDS and + * the other for T104xRDB. + */ +#define T104XRDB_CPLD_MISCCSR 0x17 +#define T104XRDB_CPLD_MISCCSR_SLEEPEN 0x40 +#define T1040QDS_QIXIS_PWR_CTL2 0x21 +#define T1040QDS_QIXIS_PWR_CTL2_PCTL 0x2 + li r3, T1040QDS_QIXIS_PWR_CTL2 + PPC_LCMPI 0, r28, T1040QDS_TETRA_FLAG + beq 20f + li r3, T104XRDB_CPLD_MISCCSR +20: add r29, r29, r3 + lbz r10, 0(r29) + sync + + LOAD_REG_ADDR(r8, deepsleep_start) + LOAD_REG_ADDR(r9, deepsleep_end) + + /* prefecth code to cache so that executing code after disable DDR */ +1: icbtls 2, 0, r8 + addi r8, r8, 64 + cmpw r8, r9 + blt 1b + sync + + FSL_DIS_ALL_IRQ + + /* + * Place DDR controller in self refresh mode. + * From here on, can't access DDR any more. + */ + lwz r10, 0(r13) + oris r10, r10, CCSR_DDR_SDRAM_CFG_2_FRC_SR@h + stw r10, 0(r13) + lwz r10, 0(r13) + sync + + DELAY(500) + + /* + * Enable deep sleep signals by write external CPLD/FPGA register. + * The bootloader will disable them when wakeup from deep sleep. + */ + lbz r10, 0(r29) + li r3, T1040QDS_QIXIS_PWR_CTL2_PCTL + PPC_LCMPI 0, r28, T1040QDS_TETRA_FLAG + beq 22f + li r3, T104XRDB_CPLD_MISCCSR_SLEEPEN +22: or r10, r10, r3 + stb r10, 0(r29) + lbz r10, 0(r29) + sync + + /* + * Set GPIO1_29 to lock the signal MCKE down during deep sleep. + * The bootloader will clear it when wakeup. + */ + lwz r10, 0(r11) + ori r10, r10, CCSR_GPIO1_GPDAT_29 + stw r10, 0(r11) + lwz r10, 0(r11) + + DELAY(100) + + /* Reset QMan system bus interface */ + lwz r10, 0(r16) + oris r10, r10, CCSR_SCFG_QMIFRSTCR_QMIFRST@h + stw r10, 0(r16) + lwz r10, 0(r16) + + /* Enable all EPU Counters */ + li r10, 0 + oris r10, r10, DCSR_EPU_EPGCR_GCE@h + stw r10, 0(r14) + lwz r10, 0(r14) + + /* Enable SCU15 to trigger on RCPM Concentrator 0 */ + lwz r10, 0(r15) + oris r10, r10, DCSR_EPU_EPECR15_IC0@h + stw r10, 0(r15) + lwz r10, 0(r15) + + /* put Core0 in PH15 mode, trigger EPU FSM */ + lwz r10, 0(r12) + ori r10, r10, CCSR_RCPM_PCPH15SETR_CORE0 + stw r10, 0(r12) +2: + b 2b + + /* + * Leave some space to prevent prefeching instruction + * beyond deepsleep_end. The space also can be used as heap. + */ +buf_tmp: + .space 128 + .align 6 +deepsleep_end: + + .align 12 +#ifdef CONFIG_PPC32 +_GLOBAL(fsl_booke_deep_sleep_resume) + /* disable interrupts */ + FSL_DIS_ALL_IRQ + +#define ENTRY_DEEPSLEEP_SETUP +#define ENTRY_MAPPING_BOOT_SETUP +#include <../../kernel/fsl_booke_entry_mapping.S> +#undef ENTRY_DEEPSLEEP_SETUP +#undef ENTRY_MAPPING_BOOT_SETUP + + li r3, 0 + mfspr r4, SPRN_PIR + bl call_setup_cpu + + /* Load each CAM entry */ + LOAD_REG_ADDR(r3, tlbcam_index) + lwz r3, 0(r3) + mtctr r3 + li r9, 0 +3: mr r3, r9 + bl loadcam_entry + addi r9, r9, 1 + bdnz 3b + + /* restore cpu registers */ + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_restore + + /* restore return address */ + LOAD_REG_ADDR(r3, buf_tmp) + lwz r4, 16(r3) + mtspr SPRN_TCR, r4 + lwz r4, 0(r3) + mtlr r4 + lwz r4, 8(r3) + mtmsr r4 + lwz r4, 24(r3) + mtcr r4 + + blr + +#else /* CONFIG_PPC32 */ + +_GLOBAL(fsl_booke_deep_sleep_resume) + /* disable interrupts */ + FSL_DIS_ALL_IRQ + + /* switch to 64-bit mode */ + bl .enable_64b_mode + + /* set TOC pointer */ + bl .relative_toc + + /* setup initial TLBs, switch to kernel space ... */ + bl .start_initialization_book3e + + /* address space changed, set TOC pointer again */ + bl .relative_toc + + /* call a cpu state restore handler */ + LOAD_REG_ADDR(r23, cur_cpu_spec) + ld r23,0(r23) + ld r23,CPU_SPEC_RESTORE(r23) + cmpdi 0,r23,0 + beq 1f + ld r23,0(r23) + mtctr r23 + bctrl +1: + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_restore + + /* Load each CAM entry */ + LOAD_REG_ADDR(r3, tlbcam_index) + lwz r3, 0(r3) + mtctr r3 + li r0, 0 +3: mr r3, r0 + bl loadcam_entry + addi r0, r0, 1 + bdnz 3b + + /* restore return address */ + LOAD_REG_ADDR(r3, buf_tmp) + ld r4, 16(r3) + mtspr SPRN_TCR, r4 + ld r4, 0(r3) + mtlr r4 + ld r4, 8(r3) + mtmsr r4 + ld r4, 24(r3) + mtcr r4 + + blr + +#endif /* CONFIG_PPC32 */ + +#endif diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 720b0c0f03ba..b099f5607120 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -19,7 +19,6 @@ #include <asm/udbg.h> #include <asm/mpic.h> #include <soc/fsl/qe/qe.h> -#include <soc/fsl/qe/qe_ic.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> @@ -31,26 +30,12 @@ static void __init twr_p1025_pic_init(void) { struct mpic *mpic; -#ifdef CONFIG_QUICC_ENGINE - struct device_node *np; -#endif - mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); BUG_ON(mpic == NULL); mpic_init(mpic); - -#ifdef CONFIG_QUICC_ENGINE - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (np) { - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - of_node_put(np); - } else - pr_err("Could not find qe-ic node\n"); -#endif } /* ************************************************************************ diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index 07a9d60c618a..76965a9e6481 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -5,6 +5,7 @@ menuconfig PPC_86xx depends on PPC_BOOK3S_32 select FSL_SOC select ALTIVEC + select FSL_PMC if SUSPEND help The Freescale E600 SoCs have 74xx cores. diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c index 76896de970ca..e72c03d32702 100644 --- a/arch/powerpc/sysdev/fsl_pmc.c +++ b/arch/powerpc/sysdev/fsl_pmc.c @@ -16,54 +16,192 @@ #include <linux/device.h> #include <linux/of_address.h> #include <linux/of_platform.h> +#include <linux/pm.h> +#include <asm/cacheflush.h> + +#include <sysdev/fsl_soc.h> +#include <asm/switch_to.h> +#include <asm/fsl_pm.h> struct pmc_regs { __be32 devdisr; __be32 devdisr2; - __be32 :32; - __be32 :32; - __be32 pmcsr; -#define PMCSR_SLP (1 << 17) + __be32 res1; + __be32 res2; + __be32 powmgtcsr; +#define POWMGTCSR_SLP 0x00020000 +#define POWMGTCSR_DPSLP 0x00100000 +#define POWMGTCSR_LOSSLESS 0x00400000 + __be32 res3[2]; + __be32 pmcdr; }; -static struct device *pmc_dev; static struct pmc_regs __iomem *pmc_regs; +static unsigned int pmc_flag; + +#define PMC_SLEEP 0x1 +#define PMC_DEEP_SLEEP 0x2 +#define PMC_LOSSLESS 0x4 + +/** + * mpc85xx_pmc_set_wake - enable devices as wakeup event source + * @dev: a device affected + * @enable: True to enable event generation; false to disable + * + * This enables the device as a wakeup event source, or disables it. + * + * RETURN VALUE: + * 0 is returned on success. + * -EINVAL is returned if device is not supposed to wake up the system. + * -ENODEV is returned if PMC is unavailable. + * Error code depending on the platform is returned if both the platform and + * the native mechanism fail to enable the generation of wake-up events + */ +int mpc85xx_pmc_set_wake(struct device *dev, bool enable) +{ + int ret = 0; + struct device_node *clk_np; + const u32 *prop; + u32 pmcdr_mask; + + if (!pmc_regs) { + dev_err(dev, "%s: PMC is unavailable\n", __func__); + return -ENODEV; + } + + if (enable && !device_may_wakeup(dev)) + return -EINVAL; + + clk_np = of_parse_phandle(dev->of_node, "fsl,pmc-handle", 0); + if (!clk_np) + return -EINVAL; + + prop = of_get_property(clk_np, "fsl,pmcdr-mask", NULL); + if (!prop) { + ret = -EINVAL; + goto out; + } + pmcdr_mask = be32_to_cpup(prop); + + if (enable) + /* clear to enable clock in low power mode */ + clrbits32(&pmc_regs->pmcdr, pmcdr_mask); + else + setbits32(&pmc_regs->pmcdr, pmcdr_mask); + +out: + of_node_put(clk_np); + return ret; +} +EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_wake); + +/** + * mpc85xx_pmc_set_lossless_ethernet - enable lossless ethernet + * in (deep) sleep mode + * @enable: True to enable event generation; false to disable + */ +void mpc85xx_pmc_set_lossless_ethernet(int enable) +{ + if (pmc_flag & PMC_LOSSLESS) { + if (enable) + setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_LOSSLESS); + else + clrbits32(&pmc_regs->powmgtcsr, POWMGTCSR_LOSSLESS); + } +} +EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_lossless_ethernet); static int pmc_suspend_enter(suspend_state_t state) { - int ret; + int ret = 0; + int result; + + switch (state) { +#ifdef CONFIG_PPC_85xx + case PM_SUSPEND_MEM: +#ifdef CONFIG_SPE + enable_kernel_spe(); +#endif +#ifdef CONFIG_PPC_FPU + enable_kernel_fp(); +#endif + + pr_debug("%s: Entering deep sleep\n", __func__); + + local_irq_disable(); + mpc85xx_enter_deep_sleep(get_immrbase(), POWMGTCSR_DPSLP); + + pr_debug("%s: Resumed from deep sleep\n", __func__); + break; +#endif - setbits32(&pmc_regs->pmcsr, PMCSR_SLP); - /* At this point, the CPU is asleep. */ + case PM_SUSPEND_STANDBY: + local_irq_disable(); + flush_dcache_L1(); - /* Upon resume, wait for SLP bit to be clear. */ - ret = spin_event_timeout((in_be32(&pmc_regs->pmcsr) & PMCSR_SLP) == 0, - 10000, 10) ? 0 : -ETIMEDOUT; - if (ret) - dev_err(pmc_dev, "tired waiting for SLP bit to clear\n"); + setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_SLP); + /* At this point, the CPU is asleep. */ + + /* Upon resume, wait for SLP bit to be clear. */ + result = spin_event_timeout( + (in_be32(&pmc_regs->powmgtcsr) & POWMGTCSR_SLP) == 0, + 10000, 10); + if (!result) { + pr_err("%s: timeout waiting for SLP bit " + "to be cleared\n", __func__); + ret = -ETIMEDOUT; + } + break; + + default: + ret = -EINVAL; + + } return ret; } static int pmc_suspend_valid(suspend_state_t state) { - if (state != PM_SUSPEND_STANDBY) - return 0; - return 1; + set_pm_suspend_state(state); + + if (((pmc_flag & PMC_SLEEP) && (state == PM_SUSPEND_STANDBY)) || + ((pmc_flag & PMC_DEEP_SLEEP) && (state == PM_SUSPEND_MEM))) + return 1; + + set_pm_suspend_state(PM_SUSPEND_ON); + return 0; +} + +static void pmc_suspend_end(void) +{ + set_pm_suspend_state(PM_SUSPEND_ON); } static const struct platform_suspend_ops pmc_suspend_ops = { .valid = pmc_suspend_valid, .enter = pmc_suspend_enter, + .end = pmc_suspend_end, }; -static int pmc_probe(struct platform_device *ofdev) +static int pmc_probe(struct platform_device *pdev) { - pmc_regs = of_iomap(ofdev->dev.of_node, 0); + struct device_node *np = pdev->dev.of_node; + + pmc_regs = of_iomap(np, 0); if (!pmc_regs) return -ENOMEM; - pmc_dev = &ofdev->dev; + pmc_flag = PMC_SLEEP; + if (of_device_is_compatible(np, "fsl,mpc8536-pmc")) + pmc_flag |= PMC_DEEP_SLEEP; + + if (of_device_is_compatible(np, "fsl,p1022-pmc")) + pmc_flag |= PMC_DEEP_SLEEP | PMC_LOSSLESS; + suspend_set_ops(&pmc_suspend_ops); + set_pm_suspend_state(PM_SUSPEND_ON); + + pr_info("Freescale PMC driver\n"); return 0; } diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 90ad16161604..21af6d5c075a 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -42,6 +42,37 @@ extern void init_fcc_ioports(struct fs_platform_info*); extern void init_fec_ioports(struct fs_platform_info*); extern void init_smc_ioports(struct fs_uart_platform_info*); static phys_addr_t immrbase = -1; +static phys_addr_t dcsrbase = -1; + +phys_addr_t get_dcsrbase(void) +{ + struct device_node *np; + const __be32 *prop; + int size; + u32 naddr; + + if (dcsrbase != -1) + return dcsrbase; + + np = of_find_compatible_node(NULL, NULL, "fsl,dcsr"); + if (!np) + return -1; + + prop = of_get_property(np, "#address-cells", &size); + if (prop && size == 4) + naddr = be32_to_cpup(prop); + else + naddr = 2; + + prop = of_get_property(np, "ranges", NULL); + if (prop) + dcsrbase = of_translate_address(np, prop + naddr); + + of_node_put(np); + + return dcsrbase; +} +EXPORT_SYMBOL(get_dcsrbase); phys_addr_t get_immrbase(void) { diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h index db11b06eb38f..674ed672bd62 100644 --- a/arch/powerpc/sysdev/fsl_soc.h +++ b/arch/powerpc/sysdev/fsl_soc.h @@ -7,6 +7,7 @@ struct spi_device; +extern phys_addr_t get_dcsrbase(void); extern phys_addr_t get_immrbase(void); #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) extern u32 get_brgfreq(void); @@ -44,5 +45,22 @@ extern struct platform_diu_data_ops diu_ops; void __noreturn fsl_hv_restart(char *cmd); void __noreturn fsl_hv_halt(void); +/* + * Cast the ccsrbar to 64-bit parameter so that the assembly + * code can be compatible with both 32-bit & 36-bit. + */ +extern void mpc85xx_enter_deep_sleep(u64 ccsrbar, u32 powmgtreq); + +#ifdef CONFIG_FSL_PMC +int mpc85xx_pmc_set_wake(struct device *dev, bool enable); +void mpc85xx_pmc_set_lossless_ethernet(int enable); +#else +static inline int mpc85xx_pmc_set_wake(struct device *dev, bool enable) +{ + return -ENODEV; +} +#define mpc85xx_pmc_set_lossless_ethernet(enable) do { } while (0) +#endif + #endif #endif |