diff options
Diffstat (limited to 'arch/arm64/boot/dts')
343 files changed, 54928 insertions, 1178 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 93fce8f0c66d..3e9642a8514f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,34 +1,167 @@ # SPDX-License-Identifier: GPL-2.0 + +# required for overlay support +DTC_FLAGS_fsl-ls1028a-qds := -@ +DTC_FLAGS_fsl-ls1028a-qds-13bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-65bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-7777 := -@ +DTC_FLAGS_fsl-ls1028a-qds-85bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-899b := -@ +DTC_FLAGS_fsl-ls1028a-qds-9999 := -@ + +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb-dpdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \ + imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \ + imx8mm-ddr4-evk-rm67191.dtb imx8mm-evk-revb-qca-wifi.dtb imx8mm-ddr4-evk-revb.dtb \ + imx8mm-ddr4-evk-revb-rm67191.dtb imx8mm-ddr3l-val.dtb \ + imx8mm-evk-pcie-ep.dtb imx8mm-ddr4-evk-pcie-ep.dtb \ + imx8mm-evk-usd-wifi.dtb \ + imx8mm-evk-qca-wifi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb \ + imx8mm-evk-iqaudio-dacplus.dtb imx8mm-evk-iqaudio-dacpro.dtb imx8mm-evk-hifiberry-dacplus.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb imx8mm-ab2-m4.dtb imx8mm-ddr4-ab2.dtb imx8mm-ddr4-ab2-m4.dtb \ + imx8mm-ddr4-ab2-revb.dtb imx8mm-ddr4-ab2-m4-revb.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb \ + imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb \ + imx8mn-evk-ak5558.dtb imx8mn-evk-rpmsg.dtb imx8mn-evk-8mic-revE.dtb imx8mn-ddr3l-evk.dtb \ + imx8mn-ddr3l-evk-ak5558.dtb imx8mn-ddr3l-evk-rpmsg.dtb \ + imx8mn-evk-iqaudio-dacplus.dtb imx8mn-evk-iqaudio-dacpro.dtb imx8mn-evk-hifiberry-dacplus.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb imx8mn-evk-root.dtb imx8mn-evk-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ab2.dtb imx8mn-ddr4-ab2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-rpmsg.dtb \ + imx8mp-evk-rm67191.dtb imx8mp-evk-flexcan2.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \ + imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-ab2.dtb imx8mp-evk-sof-wm8960.dtb \ + imx8mp-evk-dsp.dtb imx8mp-evk-ov2775.dtb imx8mp-evk-basler.dtb imx8mp-evk-pcie-ep.dtb \ + imx8mp-evk-spdif-lb.dtb imx8mp-evk-dsp-lpa.dtb imx8mp-evk-ov2775-ov5640.dtb \ + imx8mp-evk-basler-ov5640.dtb imx8mp-evk-dual-ov2775.dtb \ + imx8mp-evk-basler-ov2775.dtb imx8mp-evk-dual-basler.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ + imx8mq-evk-usdhc2-m2.dtb imx8mq-evk-pcie-ep.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67191.dtb imx8mq-evk-lcdif-adv7535.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67199.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dcss-rm67191.dtb imx8mq-evk-dcss-adv7535.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dcss-rm67199.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dual-display.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-ddr3l-val.dtb imx8mq-ddr4-val.dtb imx8mq-ddr4-val-gpmi-nand.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ + imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-rpmsg.dtb \ + imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \ + imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8qm-mek-usdhc3-m2.dtb imx8qm-mek-usd-wifi.dtb \ + imx8qm-mek-dp.dtb \ + imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \ + imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \ + imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \ + imx8qm-lpddr4-val-ca72.dtb imx8qm-ddr4-val.dtb \ + imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \ + imx8qm-mek-dsi-rm67191.dtb imx8qm-lpddr4-val-dp.dtb\ + imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb \ + imx8qm-mek-esai.dtb imx8qm-mek-vop.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \ + imx8qm-mek-root.dtb imx8qm-mek-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb \ + imx8dxl-phantom-mek-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640.dtb \ + imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb \ + imx8qxp-mek-sof-cs42888.dtb imx8qxp-mek-sof-wm8960.dtb \ + imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb \ + imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb \ + imx8qxp-mek-it6263-lvds0-dual-channel.dtb \ + imx8qxp-mek-it6263-lvds1-dual-channel.dtb \ + imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ + imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ + imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \ + imx8qxp-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ + imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8qxp-mek-dsi-rm67191.dtb \ + imx8qxp-mek-dsi-rm67191-rpmsg.dtb \ + imx8qxp-mek-dpu-lcdif.dtb \ + imx8qxp-mek-dpu-lcdif-rpmsg.dtb \ + imx8qxp-mek-ov5640-rpmsg.dtb \ + imx8qxp-mek-pcie-ep.dtb \ + imx8qm-mek-pcie-ep.dtb \ + imx8dx-mek.dtb imx8dx-mek-dsp.dtb imx8dx-mek-rpmsg.dtb \ + imx8dx-mek-enet2-tja1100.dtb \ + imx8dx-mek-ov5640.dtb \ + imx8dx-mek-ov5640-rpmsg.dtb \ + imx8dx-mek-it6263-lvds0-dual-channel.dtb \ + imx8dx-mek-it6263-lvds1-dual-channel.dtb \ + imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ + imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ + imx8dx-mek-jdi-wuxga-lvds0-panel.dtb \ + imx8dx-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ + imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8dx-mek-dsi-rm67191.dtb \ + imx8dx-mek-dsi-rm67191-rpmsg.dtb \ + imx8qxp-mek-lcdif.dtb \ + imx8qxp-mek-lcdif-rpmsg.dtb \ + imx8qxp-lpddr4-val-a0.dtb \ + imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \ + imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \ + imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \ + imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \ + imx8qxp-lpddr4-val-mlb.dtb imx8qxp-mek-vop.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \ + imx8qxp-mek-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-rpmsg.dtb \ + imx8dxl-evk-enet0.dtb imx8dxl-evk-enet0-tja1100.dtb \ + imx8dxl-evk-lpspi-slave.dtb \ + imx8dxl-evk-pcie-ep.dtb \ + imx8dxl-evk-lcdif.dtb \ + imx8dxl-ddr3-evk.dtb imx8dxl-ddr3-evk-rpmsg.dtb \ + imx8dxl-evk-root.dtb imx8dxl-evk-inmate.dtb +dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \ + s32v234-sbc.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts new file mode 100644 index 000000000000..119bf4b388c6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS1012A 2G5RDB Board. + * + * Copyright 2017 NXP + * + * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com> + */ +/dts-v1/; + +#include "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A 2G5RDB Board"; + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; +}; + +&duart0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi { + num-cs = <2>; + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts index f90c040fd5e8..fcc3c271a4d2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts @@ -13,6 +13,11 @@ model = "LS1012A Freedom Board"; compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; + sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -74,6 +79,45 @@ }; }; +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + &sai2 { status = "okay"; }; @@ -81,3 +125,18 @@ &sata { status = "okay"; }; + +&qspi { + status = "okay"; + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts index 8749634c55ee..55806119a8a3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts @@ -14,6 +14,58 @@ / { model = "LS1012A FRWY Board"; compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + system-clock-frequency = <25000000>; + }; + }; +}; + +&pcie { + status = "okay"; }; &duart0 { @@ -22,4 +74,72 @@ &i2c0 { status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0xa>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + clocks = <&sys_mclk>; + }; +}; + +&qspi { + num-cs = <1>; + bus-num = <0>; + status = "okay"; + + qflash0: w25q16dw@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,gemac-bus-id = <0x0>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + +&sai2 { + status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index 2fb1cb1f7d8f..a4fed83900ea 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -13,6 +13,11 @@ model = "LS1012A QDS Board"; compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; + sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -57,6 +62,10 @@ }; }; +&pcie { + status = "okay"; +}; + &dspi { bus-num = <0>; status = "okay"; @@ -128,6 +137,47 @@ }; }; +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x2>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x3>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + }; +}; + &sai2 { status = "okay"; }; @@ -135,3 +185,18 @@ &sata { status = "okay"; }; + +&qspi { + status = "okay"; + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts index 5edb1e137a52..57a1e0d9b5e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -12,6 +12,15 @@ / { model = "LS1012A RDB Board"; compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; +}; + +&pcie { + status = "okay"; }; &duart0 { @@ -38,3 +47,57 @@ &sata { status = "okay"; }; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "rgmii-txid"; + phy-handle = <&rgmii_phy>; + }; + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy: ethernet-phy@2 { + reg = <0x2>; + }; + + rgmii_phy: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ec141c985289..0a020a355508 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1012A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * */ @@ -22,13 +23,14 @@ rtic-c = &rtic_c; rtic-d = &rtic_d; sec-mon = &sec_mon; + rtc1 = &ftm_alarm0; }; cpus { #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; @@ -100,36 +102,7 @@ mask = <0x02>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" soc { compatible = "simple-bus"; @@ -261,7 +234,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1012a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -318,13 +291,29 @@ #thermal-sensor-cells = <1>; }; + rcpm: rcpm@1ee2140 { + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x4>; + #fsl,rcpm-wakeup-cells = <1>; + }; + + ftm_alarm0: timer@29d0000 { + compatible = "fsl,ls1012a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x20000>; + interrupts = <0 86 0x4>; + big-endian; + }; + + i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 3>; + scl-gpios = <&gpio0 13 0>; status = "disabled"; }; @@ -396,14 +385,28 @@ big-endian; }; + qspi: spi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 0>, <&clockgen 4 0>; + status = "disabled"; + }; + sai1: sai@2b50000 { #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0x2b50000 0x0 0x10000>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 3>, <&clockgen 4 3>, + <&clockgen 4 3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, <&edma0 1 46>; @@ -416,8 +419,9 @@ reg = <0x0 0x2b60000 0x0 0x10000>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 3>, <&clockgen 4 3>, + <&clockgen 4 3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, <&edma0 1 44>; @@ -441,13 +445,15 @@ }; usb0: usb3@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1012a-dwc3", "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; }; sata: sata@3200000 { @@ -502,6 +508,35 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pfe_reserved: packetbuffer@83400000 { + reg = <0 0x83400000 0 0xc00000>; + }; + }; + + pfe: pfe@4000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ + reg-names = "pfe", "pfe-ddr"; + fsl,pfe-num-interfaces = <0x2>; + interrupts = <0 172 0x4>, /* HIF interrupt */ + <0 173 0x4>, /*HIF_NOCPY interrupt */ + <0 174 0x4>; /* WoL interrupt */ + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; + memory-region = <&pfe_reserved>; + fsl,pfe-scfg = <&scfg 0>; + fsl,rcpm-wakeup = <&rcpm 0xf0000020>; + clocks = <&clockgen 4 0>; + clock-names = "pfe"; + + status = "okay"; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -509,3 +544,9 @@ }; }; }; + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts new file mode 100644 index 000000000000..2755ff204e8b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 13bb + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts new file mode 100644 index 000000000000..fb718a57b520 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 69xx + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts new file mode 100644 index 000000000000..fa47f5466a81 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 7777 + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing + * disabled, plugged in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts new file mode 100644 index 000000000000..88c415644b29 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85bb + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts new file mode 100644 index 000000000000..578e913c4bfe --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + }; + }; + + fragment@2 { + target = <&mscc_felix_ports>; + __overlay__ { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts new file mode 100644 index 000000000000..5c8b3c6b43ab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + fragment@1 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 078a5010228c..c893dcc16c51 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1028A QDS Board. * - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Harninder Rai <harninder.rai@nxp.com> * @@ -104,9 +104,41 @@ reg = <5>; }; }; + + mdio_slot1: mdio@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + mdio_slot2: mdio@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + mdio_slot3: mdio@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + mdio_slot4: mdio@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + &duart0 { status = "okay"; }; @@ -161,11 +193,6 @@ vcc-supply = <&sb_3v3>; }; - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - eeprom@56 { compatible = "atmel,24c512"; reg = <0x56>; @@ -209,11 +236,34 @@ }; +&i2c1 { + status = "okay"; + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; +}; + &enetc_port1 { phy-handle = <&qds_phy1>; phy-connection-type = "rgmii-id"; }; +&fspi { + status = "okay"; + mt35xu02g: flash@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <20000000>; + reg = <0>; + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ + spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + }; +}; + &sai1 { status = "okay"; }; @@ -221,3 +271,8 @@ &sata { status = "okay"; }; + +&hdptx0 { + lane-mapping = <0x4e>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts new file mode 100644 index 000000000000..4767d0dd0a77 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * NXP LS1028A RDB Board device tree file for DPDK + * + * Copyright 2018-2020 NXP + */ + +/dts-v1/; +#include "fsl-ls1028a-rdb.dts" + +&enetc_port0 { + status = "okay"; + /delete-property/ phy-handle; + /delete-property/ phy-connection-type; + /delete-node/ mdio; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/delete-node/ &enetc_mdio_pf3; + +/* l2switch ports */ +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@2 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@3 { + status = "okay"; + phy-mode = "qsgmii"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@5 { + status = "okay"; + /delete-property/ managed; + /delete-property/ phy-handle; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; +}; + +&enetc_port3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 1a69221d9a1b..d4e6ef40a149 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1028A RDB Board. * - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Harninder Rai <harninder.rai@nxp.com> * @@ -93,9 +93,15 @@ &esdhc1 { mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; status = "okay"; }; +&usb1 { + dr_mode = "otg"; +}; + &i2c0 { status = "okay"; @@ -152,6 +158,37 @@ }; }; +&can0 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&fspi { + status = "okay"; + mt35xu02g: flash@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <20000000>; + reg = <0>; + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ + spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + }; +}; + &duart0 { status = "okay"; }; @@ -177,6 +214,55 @@ status = "disabled"; }; +&enetc_mdio_pf3 { + qsgmii_phy1: ethernet-phy@10 { + reg = <0x10>; + }; + + qsgmii_phy2: ethernet-phy@11 { + reg = <0x11>; + }; + + qsgmii_phy3: ethernet-phy@12 { + reg = <0x12>; + }; + + qsgmii_phy4: ethernet-phy@13 { + reg = <0x13>; + }; +}; + +/* l2switch ports */ +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&qsgmii_phy1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&qsgmii_phy2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&qsgmii_phy3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&qsgmii_phy4>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; +}; + &sai4 { status = "okay"; }; @@ -184,3 +270,8 @@ &sata { status = "okay"; }; + +&hdptx0 { + lane-mapping = <0x4e>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5716ac20bddd..0d88dfa846db 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Include file for NXP Layerscape-1028A family SoC. * - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Harninder Rai <harninder.rai@nxp.com> * @@ -17,6 +17,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + rtc1 = &ftm_alarm0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -82,22 +86,8 @@ dpclk: clock-controller@f1f0000 { compatible = "fsl,ls1028a-plldig"; reg = <0x0 0xf1f0000 0x0 0xffff>; - #clock-cells = <1>; - clocks = <&osc_27m>; - }; - - aclk: clock-axi { - compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <650000000>; - clock-output-names= "aclk"; - }; - - pclk: clock-apb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <650000000>; - clock-output-names= "pclk"; + clocks = <&osc_27m>; }; reboot { @@ -180,6 +170,18 @@ clocks = <&sysclk>; }; + fspi: spi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; @@ -287,6 +289,26 @@ status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,ls1028ar1-flexcan", + "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,ls1028ar1-flexcan", + "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; @@ -305,7 +327,7 @@ edma0: dma-controller@22c0000 { #dma-cells = <2>; - compatible = "fsl,vf610-edma"; + compatible = "fsl,ls1028a-edma"; reg = <0x0 0x22c0000 0x0 0x10000>, <0x0 0x22d0000 0x0 0x10000>, <0x0 0x22e0000 0x0 0x10000>; @@ -359,6 +381,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + dma-coherent; }; usb1: usb@3110000 { @@ -369,6 +392,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + dma-coherent; }; sata: sata@3200000 { @@ -506,14 +530,25 @@ clock-names = "apb_pclk", "wdog_clk"; }; + gpu@f0c0000 { + compatible = "fsl,ls1028a-gpu"; + reg = <0x0 0x0f0c0000 0x0 0x10000>, + <0x0 0x80000000 0x0 0x80000000>, + <0x0 0x0 0x0 0x3000000>; + reg-names = "base", "phys_baseaddr", + "contiguous_mem"; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + }; + sai1: audio-controller@f100000 { #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0xf100000 0x0 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 4>, <&edma0 1 3>; @@ -526,8 +561,9 @@ reg = <0x0 0xf110000 0x0 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 6>, <&edma0 1 5>; @@ -540,8 +576,9 @@ reg = <0x0 0xf130000 0x0 0x10000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 10>, <&edma0 1 9>; @@ -631,12 +668,63 @@ }; }; + pcie@3400000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pcie@1f0000000 { /* Integrated Endpoint Root Complex */ compatible = "pci-host-ecam-generic"; reg = <0x01 0xf0000000 0x0 0x100000>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; msi-parent = <&its>; device_type = "pci"; bus-range = <0x0 0x0>; @@ -654,7 +742,9 @@ /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; + 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 + /* BAR4 (PF5) - non-prefetchable memory */ + 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; enetc_port0: ethernet@0,0 { compatible = "fsl,enetc"; @@ -670,12 +760,111 @@ #address-cells = <1>; #size-cells = <0>; }; + enetc_port2: ethernet@0,2 { + compatible = "fsl,enetc"; + reg = <0x000200 0 0 0 0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; ethernet@0,4 { compatible = "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; clocks = <&clockgen 2 3>; little-endian; }; + + ethernet-switch@0,5 { + reg = <0x000500 0 0 0 0>; + /* IEP INT_B */ + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + + mscc_felix_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* external ports */ + mscc_felix_port0: port@0 { + reg = <0>; + status = "disabled"; + label = "swp0"; + }; + + mscc_felix_port1: port@1 { + reg = <1>; + status = "disabled"; + label = "swp1"; + }; + + mscc_felix_port2: port@2 { + reg = <2>; + status = "disabled"; + label = "swp2"; + }; + + mscc_felix_port3: port@3 { + reg = <3>; + status = "disabled"; + label = "swp3"; + }; + + /* internal to-cpu ports */ + mscc_felix_port4: port@4 { + reg = <4>; + ethernet = <&enetc_port2>; + phy-mode = "gmii"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + mscc_felix_port5: port@5 { + reg = <5>; + phy-mode = "gmii"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + enetc_port3: ethernet@0,6 { + compatible = "fsl,enetc"; + reg = <0x000600 0 0 0 0>; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + rcpm: rcpm@1e34040 { + compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x1c>; + #fsl,rcpm-wakeup-cells = <7>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1028a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; }; }; @@ -685,14 +874,31 @@ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, <0 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "DE", "SE"; - clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>; + clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, + <&clockgen 2 2>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; arm,malidp-arqos-value = <0xd000d000>; port { dp0_out: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; + hdptx0: display@f200000 { + compatible = "cdn,ls1028a-dp"; + reg = <0x0 0xf200000 0x0 0xfffff>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>, + <&clockgen 2 2>, <&clockgen 2 2>, <&dpclk>; + clock-names = "clk_core", "pclk", "sclk", + "cclk", "clk_vif", "clk_pxl"; + + port { + dp1_out: endpoint { + remote-endpoint = <&dp0_out>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts new file mode 100644 index 000000000000..43bafb51515e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts @@ -0,0 +1,263 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1043a-qds.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3500000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3600000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +/delete-node/ iommu@9000000; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + dma-coherent; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi0 { + dma-coherent; +}; + +&dspi1 { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&gpio4 { + dma-coherent; +}; + +&uqe { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index 1aac81da7e37..219a987800fb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1043A family SoC. * * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Mingkai Hu <Mingkai.hu@freescale.com> */ @@ -24,6 +24,22 @@ serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; + sgmii-riser-s1-p1 = &sgmii_phy_s1_p1; + sgmii-riser-s2-p1 = &sgmii_phy_s2_p1; + sgmii-riser-s3-p1 = &sgmii_phy_s3_p1; + sgmii-riser-s4-p1 = &sgmii_phy_s4_p1; + qsgmii-s1-p1 = &qsgmii_phy_s1_p1; + qsgmii-s1-p2 = &qsgmii_phy_s1_p2; + qsgmii-s1-p3 = &qsgmii_phy_s1_p3; + qsgmii-s1-p4 = &qsgmii_phy_s1_p4; + qsgmii-s2-p1 = &qsgmii_phy_s2_p1; + qsgmii-s2-p2 = &qsgmii_phy_s2_p2; + qsgmii-s2-p3 = &qsgmii_phy_s2_p3; + qsgmii-s2-p4 = &qsgmii_phy_s2_p4; + emi1-slot1 = &ls1043mdio_s1; + emi1-slot2 = &ls1043mdio_s2; + emi1-slot3 = &ls1043mdio_s3; + emi1-slot4 = &ls1043mdio_s4; }; chosen { @@ -62,8 +78,11 @@ }; fpga: board-control@2,0 { - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus"; reg = <0x2 0x0 0x0000100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 2 0 0x100>; }; }; @@ -149,3 +168,147 @@ }; #include "fsl-ls1043-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy_s2_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&qsgmii_phy_s2_p2>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&qsgmii_phy_s2_p3>; + phy-connection-type = "sgmii"; + }; + + ethernet@ea000 { + phy-handle = <&qsgmii_phy_s2_p4>; + phy-connection-type = "sgmii"; + }; + + ethernet@f0000 { /* DTSEC9/10GEC1 */ + fixed-link = <1 1 10000 0 0>; + phy-connection-type = "xgmii"; + }; +}; + +&fpga { + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1 */ + + /* On-board RGMII1 PHY */ + ls1043mdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { /* MAC3 */ + reg = <0x1>; + }; + }; + + /* On-board RGMII2 PHY */ + ls1043mdio1: mdio@1 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { /* MAC4 */ + reg = <0x2>; + }; + }; + + /* Slot 1 */ + ls1043mdio_s1: mdio@2 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s1_p1: ethernet-phy@4 { + reg = <0x4>; + }; + qsgmii_phy_s1_p2: ethernet-phy@5 { + reg = <0x5>; + }; + qsgmii_phy_s1_p3: ethernet-phy@6 { + reg = <0x6>; + }; + qsgmii_phy_s1_p4: ethernet-phy@7 { + reg = <0x7>; + }; + + sgmii_phy_s1_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + /* Slot 2 */ + ls1043mdio_s2: mdio@3 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s2_p1: ethernet-phy@8 { + reg = <0x8>; + }; + qsgmii_phy_s2_p2: ethernet-phy@9 { + reg = <0x9>; + }; + qsgmii_phy_s2_p3: ethernet-phy@a { + reg = <0xa>; + }; + qsgmii_phy_s2_p4: ethernet-phy@b { + reg = <0xb>; + }; + + sgmii_phy_s2_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + /* Slot 3 */ + ls1043mdio_s3: mdio@4 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s3_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + /* Slot 4 */ + ls1043mdio_s4: mdio@5 { + reg = <0xa0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s4_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts new file mode 100644 index 000000000000..210bc9f25c47 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts @@ -0,0 +1,262 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1043a-rdb.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3500000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3600000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +/delete-node/ iommu@9000000; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi0 { + dma-coherent; +}; + +&dspi1 { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&gpio4 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts new file mode 100644 index 000000000000..7beb9985add2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts @@ -0,0 +1,140 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2014-2015, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "fsl-ls1043a-rdb-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@0 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; + }; + + ethernet@1 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; + }; + + ethernet@2 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@3 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>; + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>; + }; + + ethernet@8 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; + + }; + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* <OH Rx error, OH Rx default> */ + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index dde50c88f5e3..06d12ba8ac0f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -49,6 +49,10 @@ compatible = "pericom,pt7c4338"; reg = <0x68>; }; + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; }; &ifc { @@ -94,6 +98,38 @@ reg = <0>; spi-max-frequency = <1000000>; /* input clock */ }; + + slic@2 { + compatible = "maxim,ds26522"; + reg = <2>; + spi-max-frequency = <2000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; + }; + + slic@3 { + compatible = "maxim,ds26522"; + reg = <3>; + spi-max-frequency = <2000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; + }; +}; + +&uqe { + ucc_hdlc: ucc@2000 { + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "clk8"; + tx-clock-name = "clk9"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot-mask = <0xfffffffe>; + fsl,rx-timeslot-mask = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + fsl,tdm-interface; + }; }; &duart0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index b611d835dc25..b5c647be6857 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -27,6 +27,7 @@ ethernet4 = &enet4; ethernet5 = &enet5; ethernet6 = &enet6; + rtc1 = &ftm_alarm0; }; cpus { @@ -39,7 +40,7 @@ * * Currently supported enable-method is psci v0.2 */ - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; @@ -148,38 +149,7 @@ mask = <0x02>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&tmu 3>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" timer { compatible = "arm,armv8-timer"; @@ -218,6 +188,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + dma-coherent; clockgen: clocking@1ee1000 { compatible = "fsl,ls1043a-clockgen"; @@ -226,6 +198,49 @@ clocks = <&sysclk>; }; + smmu: iommu@9000000 { + compatible = "arm,mmu-500"; + reg = <0 0x9000000 0 0x400000>; + dma-coherent; + stream-match-mask = <0x7f00>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1043a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; @@ -278,7 +293,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1043a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -412,7 +427,7 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; @@ -422,6 +437,7 @@ dmas = <&edma0 1 39>, <&edma0 1 38>; dma-names = "tx", "rx"; + scl-gpios = <&gpio4 12 0>; status = "disabled"; }; @@ -526,6 +542,72 @@ #interrupt-cells = <2>; }; + uqe: uqe@2400000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe", "simple-bus"; + ranges = <0x0 0x0 0x2400000 0x40000>; + reg = <0x0 0x2400000 0x0 0x480>; + brg-frequency = <100000000>; + bus-frequency = <200000000>; + + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + + qeic: qeic@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #address-cells = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <0 77 0x04 0 77 0x04>; + }; + + si1: si@700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,ls1043-qe-si", + "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1043-qe-siram", + "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + ucc@2000 { + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + }; + + ucc@2200 { + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; + }; + lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; @@ -605,44 +687,66 @@ <&clockgen 4 0>; }; - usb0: usb3@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb3@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = <0 61 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb2: usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 63 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 0x4>; - clocks = <&clockgen 4 0>; - dma-coherent; + aux_bus: aux_bus { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; + + usb0: usb3@2f00000 { + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 0x4>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + configure-gfladj; + dma-coherent; + }; + + usb1: usb3@3000000 { + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + configure-gfladj; + dma-coherent; + }; + + usb2: usb3@3100000 { + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 0x4>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + configure-gfladj; + dma-coherent; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1043a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x0 0x20140520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = <0 69 0x4>; + clocks = <&clockgen 4 0>; + }; }; msi1: msi-controller1@1571000 { @@ -671,13 +775,13 @@ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ + <0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -697,13 +801,13 @@ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, - <0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, + <0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -723,13 +827,13 @@ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, - <0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, + <0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -765,6 +869,19 @@ big-endian; }; + rcpm: rcpm@1ee2140 { + compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x4>; + #fsl,rcpm-wakeup-cells = <1>; + }; + + ftm_alarm0: timer@29d0000 { + compatible = "fsl,ls1043a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x20000>; + interrupts = <0 86 0x4>; + big-endian; + }; }; firmware { @@ -778,3 +895,29 @@ #include "qoriq-qman-portals.dtsi" #include "qoriq-bman-portals.dtsi" + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; + + thermal-zone1 { + status = "okay"; + }; + + thermal-zone2 { + status = "okay"; + }; + + thermal-zone3 { + status = "okay"; + }; + + thermal-zone4 { + status = "okay"; + }; + + thermal-zone5 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts new file mode 100644 index 000000000000..8c0e8aaddc2f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2019 NXP. + * + */ + +#include "fsl-ls1046a-frwy.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@1 { + status = "disabled"; + }; + ethernet@2 { + status = "disabled"; + }; + ethernet@3 { + status = "disabled"; + }; + ethernet@6 { + status = "disabled"; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts new file mode 100644 index 000000000000..bd4f884eb945 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2019 NXP. + * + */ + +#include "fsl-ls1046a-frwy-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@0 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@9 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* <OH Rx error, OH Rx default> */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts index 2d6c73d7d397..b647da3d6585 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts @@ -106,6 +106,23 @@ }; + +&qspi { + num-cs = <1>; + bus-num = <0>; + status = "okay"; + + qflash0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + #include "fsl-ls1046-post.dtsi" &fman0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts new file mode 100644 index 000000000000..d5de7ea92c5b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts @@ -0,0 +1,264 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1046a-qds.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; +}; + +pcie@3500000 { + /delete-property/ iommu-map; +}; + +pcie@3600000 { + /delete-property/ iommu-map; +}; + +/delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + dma-coherent; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index eec62c63dafe..35fa10a5d594 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * Shaohui Xie <Shaohui.Xie@nxp.com> */ @@ -25,6 +25,20 @@ serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; + + emi1-slot1 = &ls1046mdio_s1; + emi1-slot2 = &ls1046mdio_s2; + emi1-slot4 = &ls1046mdio_s4; + + sgmii-s1-p1 = &sgmii_phy_s1_p1; + sgmii-s1-p2 = &sgmii_phy_s1_p2; + sgmii-s1-p3 = &sgmii_phy_s1_p3; + sgmii-s1-p4 = &sgmii_phy_s1_p4; + sgmii-s4-p1 = &sgmii_phy_s4_p1; + qsgmii-s2-p1 = &qsgmii_phy_s2_p1; + qsgmii-s2-p2 = &qsgmii_phy_s2_p2; + qsgmii-s2-p3 = &qsgmii_phy_s2_p3; + qsgmii-s2-p4 = &qsgmii_phy_s2_p4; }; chosen { @@ -153,8 +167,9 @@ }; fpga: board-control@2,0 { - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus"; reg = <0x2 0x0 0x0000100>; + ranges = <0 2 0 0x100>; }; }; @@ -169,7 +184,7 @@ compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; reg = <0>; @@ -177,3 +192,137 @@ }; #include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy_s2_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmii_phy_s4_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&sgmii_phy_s1_p3>; + phy-connection-type = "sgmii"; + }; + + ethernet@ea000 { + phy-handle = <&sgmii_phy_s1_p4>; + phy-connection-type = "sgmii"; + }; + + ethernet@f0000 { /* DTSEC9/10GEC1 */ + phy-handle = <&sgmii_phy_s1_p1>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { /* DTSEC10/10GEC2 */ + phy-handle = <&sgmii_phy_s1_p2>; + phy-connection-type = "xgmii"; + }; +}; + +&fpga { + #address-cells = <1>; + #size-cells = <1>; + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1 */ + + /* On-board RGMII1 PHY */ + ls1046mdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { /* MAC3 */ + reg = <0x1>; + }; + }; + + /* On-board RGMII2 PHY */ + ls1046mdio1: mdio@1 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { /* MAC4 */ + reg = <0x2>; + }; + }; + + /* Slot 1 */ + ls1046mdio_s1: mdio@2 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s1_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + + sgmii_phy_s1_p2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy_s1_p3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy_s1_p4: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + + /* Slot 2 */ + ls1046mdio_s2: mdio@3 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s2_p1: ethernet-phy@8 { + reg = <0x8>; + }; + qsgmii_phy_s2_p2: ethernet-phy@9 { + reg = <0x9>; + }; + qsgmii_phy_s2_p3: ethernet-phy@a { + reg = <0xa>; + }; + qsgmii_phy_s2_p4: ethernet-phy@b { + reg = <0xb>; + }; + }; + + /* Slot 4 */ + ls1046mdio_s4: mdio@5 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s4_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts new file mode 100644 index 000000000000..d9ae081b4f3b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts @@ -0,0 +1,273 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1046a-rdb.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; +}; + +pcie@3500000 { + /delete-property/ iommu-map; +}; + +pcie@3600000 { + /delete-property/ iommu-map; +}; + +/delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@0 { + status = "disabled"; + }; + ethernet@1 { + status = "disabled"; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts new file mode 100644 index 000000000000..343c9d81a83f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts @@ -0,0 +1,133 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "fsl-ls1046a-rdb-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@2 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@3 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>; + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>; + }; + + ethernet@8 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; + }; + + ethernet@9 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>; + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* <OH Rx error, OH Rx default> */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 8858c1e92f23..c5a4e2193f3b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * * Mingkai Hu <mingkai.hu@nxp.com> */ @@ -43,6 +44,10 @@ sd-uhs-sdr12; }; +&usb1 { + dr_mode = "otg"; +}; + &i2c0 { status = "okay"; @@ -96,23 +101,23 @@ &qspi { status = "okay"; - qflash0: flash@0 { - compatible = "spansion,m25p80"; + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; reg = <0>; }; - qflash1: flash@1 { - compatible = "spansion,m25p80"; + s25fs512s: flash@1 { + compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index ca087918c250..f4d0d2ad2d67 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -28,13 +28,14 @@ ethernet5 = &enet5; ethernet6 = &enet6; ethernet7 = &enet7; + rtc1 = &ftm_alarm0; }; cpus { #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; @@ -116,38 +117,7 @@ mask = <0x02>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 3>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" timer { compatible = "arm,armv8-timer"; @@ -190,6 +160,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + dma-coherent; ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; @@ -229,6 +201,49 @@ bus-width = <4>; }; + smmu: iommu@9000000 { + compatible = "arm,mmu-500"; + reg = <0 0x9000000 0 0x400000>; + dma-coherent; + stream-match-mask = <0x7f00>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1046a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; @@ -377,7 +392,7 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; @@ -386,6 +401,7 @@ dmas = <&edma0 1 39>, <&edma0 1 38>; dma-names = "tx", "rx"; + scl-gpios = <&gpio3 12 0>; status = "disabled"; }; @@ -410,12 +426,13 @@ }; i2c3: i2c@21b0000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21b0000 0x0 0x10000>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 1>; + scl-gpios = <&gpio3 12 0>; status = "disabled"; }; @@ -569,43 +586,63 @@ <&clockgen 4 1>; }; - usb0: usb@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb2: usb@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1046a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 1>; + aux_bus: aux_bus { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; + + usb0: usb@2f00000 { + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,host-vbus-glitches; + dma-coherent; + }; + + usb1: usb@3000000 { + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,host-vbus-glitches; + dma-coherent; + }; + + usb2: usb@3100000 { + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; + snps,host-vbus-glitches; + dma-coherent; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1046a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x0 0x20140520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 1>; + }; }; msi1: msi-controller@1580000 { @@ -650,6 +687,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -686,6 +724,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -722,6 +761,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -766,6 +806,20 @@ queue-sizes = <64 64>; big-endian; }; + + rcpm: rcpm@1ee208c { + compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee208c 0x0 0x4>; + #fsl,rcpm-wakeup-cells = <1>; + }; + + ftm_alarm0: timer@29d0000 { + compatible = "fsl,ls1046a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x20000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + }; }; reserved-memory { @@ -805,3 +859,25 @@ #include "qoriq-qman-portals.dtsi" #include "qoriq-bman-portals.dtsi" + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; + + thermal-zone1 { + status = "okay"; + }; + + thermal-zone2 { + status = "okay"; + }; + + thermal-zone3 { + status = "okay"; + }; + + thermal-zone4 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts index 120e62dad154..38e3bed55047 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts @@ -131,6 +131,30 @@ }; }; +&qspi { + status = "okay"; + fsl,qspi-has-second-chip; + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; + + qflash1: s25fs512s@1 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &duart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 8e925df6c01c..c8c73e29ca0d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -74,6 +74,31 @@ }; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; + + s25fs512s1: flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <1>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; + +}; + &duart0 { status = "okay"; }; @@ -95,5 +120,85 @@ }; &usb1 { + dr_mode = "otg"; status = "okay"; }; + +&emdio1 { + /* Freescale F104 PHY1 */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x1c>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x1d>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x1e>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x1f>; + phy-connection-type = "qsgmii"; + }; + /* F104 PHY2 */ + mdio1_phy5: emdio1_phy@5 { + reg = <0x0c>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy6: emdio1_phy@6 { + reg = <0x0d>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy7: emdio1_phy@7 { + reg = <0x0e>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy8: emdio1_phy@8 { + reg = <0x0f>; + phy-connection-type = "qsgmii"; + }; +}; + +&emdio2 { + /* Aquantia AQR105 10G PHY */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; + reg = <0x0>; + phy-connection-type = "xfi"; + }; +}; + +/* DPMAC connections to external PHYs + * based on LS1088A RM RevC - $24.1.2 SerDes Options + */ +/* DPMAC1 is 10G SFP+, fixed link */ +&dpmac2 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac3 { + phy-handle = <&mdio1_phy5>; +}; +&dpmac4 { + phy-handle = <&mdio1_phy6>; +}; +&dpmac5 { + phy-handle = <&mdio1_phy7>; +}; +&dpmac6 { + phy-handle = <&mdio1_phy8>; +}; +&dpmac7 { + phy-handle = <&mdio1_phy1>; +}; +&dpmac8 { + phy-handle = <&mdio1_phy2>; +}; +&dpmac9 { + phy-handle = <&mdio1_phy3>; +}; +&dpmac10 { + phy-handle = <&mdio1_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index c676d0771762..217d98ba1c41 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Include file for NXP Layerscape-1088A family SoC. * - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * * Harninder Rai <harninder.rai@nxp.com> * @@ -18,6 +18,7 @@ aliases { crypto = &crypto; + rtc1 = &ftm_alarm0; }; cpus { @@ -25,7 +26,7 @@ #size-cells = <0>; /* We have 2 clusters having 4 Cortex-A53 cores each */ - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; @@ -61,7 +62,7 @@ #cooling-cells = <2>; }; - cpu4: cpu@100 { + cooling_map1: cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; @@ -128,42 +129,7 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; + #include "fsl-tmu.dtsi" timer { compatible = "arm,armv8-timer"; @@ -185,6 +151,19 @@ clock-output-names = "sysclk"; }; + rstcr: syscon@1e60000 { + compatible = "fsl,ls1088a-rstcr", "syscon"; + reg = <0x0 0x1e60000 0x0 0x4>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rstcr>; + offset = <0x0>; + mask = <0x02>; + }; + + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -325,6 +304,32 @@ #interrupt-cells = <2>; }; + /* TODO: WRIOP (CCSR?) */ + emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO1: 0x1_6000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + device_type = "mdio"; + little-endian; /* force the driver in LE mode */ + + /* Not necessary on the QDS, but needed on the RDB */ + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO2: 0x1_7000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + device_type = "mdio"; + little-endian; /* force the driver in LE mode */ + + #address-cells = <1>; + #size-cells = <0>; + }; + ifc: ifc@2240000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>; @@ -336,12 +341,13 @@ }; i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 7>; + scl-gpios = <&gpio3 30 0>; status = "disabled"; }; @@ -388,23 +394,28 @@ }; usb0: usb3@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb1: usb3@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; @@ -418,6 +429,17 @@ dma-coherent; status = "disabled"; }; + qspi: spi@20c0000 { + compatible = "fsl,ls2080a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "qspi_en", "qspi"; + }; crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; @@ -474,6 +496,7 @@ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, @@ -499,6 +522,7 @@ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, @@ -524,6 +548,7 @@ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, @@ -764,6 +789,20 @@ }; }; }; + + rcpm: rcpm@1e34040 { + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1088a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <0 44 4>; + }; }; firmware { @@ -773,3 +812,15 @@ }; }; }; + +#include "fsl-tmu-map1.dtsi" + +&thermal_zones { + thermal-zone0 { + status = "okay"; + }; + + thermal-zone1 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts index f6c3ee78ace0..20157fd69530 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts @@ -23,3 +23,65 @@ stdout-path = "serial0:115200n8"; }; }; + +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; + reg = <3 0 0x300>; /* TODO check address */ + ranges = <0 3 0 0x300>; + + mdio_mux_emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + phy-connection-type = "sgmii"; + }; + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + phy-connection-type = "sgmii"; + }; + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + phy-connection-type = "sgmii"; + }; + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + phy-connection-type = "sgmii"; + }; + }; + }; + }; +}; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; +}; +&dpmac10 { + phy-handle = <&mdio0_phy13>; +}; +&dpmac11 { + phy-handle = <&mdio0_phy14>; +}; +&dpmac12 { + phy-handle = <&mdio0_phy15>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts index 44894356059c..2ed99e98f59d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts @@ -23,3 +23,83 @@ stdout-path = "serial1:115200n8"; }; }; + +&emdio1 { + status = "disabled"; + /* CS4340 PHYs */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x10>; + phy-connection-type = "xfi"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x11>; + phy-connection-type = "xfi"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x12>; + phy-connection-type = "xfi"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x13>; + phy-connection-type = "xfi"; + }; +}; + +&emdio2 { + /* AQR405 PHYs */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 1 0x4>; /* Level high type */ + reg = <0x0>; + phy-connection-type = "xfi"; + }; + mdio2_phy2: emdio2_phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; /* Level high type */ + reg = <0x1>; + phy-connection-type = "xfi"; + }; + mdio2_phy3: emdio2_phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 4 0x4>; /* Level high type */ + reg = <0x2>; + phy-connection-type = "xfi"; + }; + mdio2_phy4: emdio2_phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 5 0x4>; /* Level high type */ + reg = <0x3>; + phy-connection-type = "xfi"; + }; +}; + +/* Update DPMAC connections to external PHYs, under the assumption of + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. + */ +/* Leave Cortina nodes commented out until driver is integrated + *&dpmac1 { + * phy-handle = <&mdio1_phy1>; + *}; + *&dpmac2 { + * phy-handle = <&mdio1_phy2>; + *}; + *&dpmac3 { + * phy-handle = <&mdio1_phy3>; + *}; + *&dpmac4 { + * phy-handle = <&mdio1_phy4>; + *}; + */ + +&dpmac5 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac6 { + phy-handle = <&mdio2_phy2>; +}; +&dpmac7 { + phy-handle = <&mdio2_phy3>; +}; +&dpmac8 { + phy-handle = <&mdio2_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index f9c1d30cf4a7..3b00e6f1b243 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -12,7 +12,7 @@ #include "fsl-ls208xa.dtsi" &cpu { - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0>; @@ -32,7 +32,7 @@ #cooling-cells = <2>; }; - cpu2: cpu@100 { + cooling_map1: cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x100>; @@ -52,7 +52,7 @@ #cooling-cells = <2>; }; - cpu4: cpu@200 { + cooling_map2: cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x200>; @@ -72,7 +72,7 @@ #cooling-cells = <2>; }; - cpu6: cpu@300 { + cooling_map3: cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x300>; @@ -118,6 +118,18 @@ }; }; +&timer { + fsl,erratum-a008585; +}; + +&usb0 { + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +}; + +&usb1 { + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; +}; + &pcie1 { reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts new file mode 100644 index 000000000000..0e240a97f589 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS2081A RDB Board. + * + * Copyright 2017 NXP + * + * Priyanka Jain <priyanka.jain@nxp.com> + * + */ + +/dts-v1/; + +#include "fsl-ls2088a.dtsi" + +/ { + model = "NXP Layerscape 2081A RDB Board"; + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&esdhc { + status = "okay"; +}; + +&ifc { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + pca9547@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01>; + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + adt7481@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + }; +}; + +&dspi { + status = "okay"; + dflash0: n25q512a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <3000000>; + reg = <0>; + }; +}; + +&qspi { + status = "okay"; + fsl,qspi-has-second-chip; + flash0: s25fs512s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <20000000>; + reg = <0>; + }; + flash1: s25fs512s@1 { + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + compatible = "spansion,m25p80"; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts index 7c17b1bd4529..01a3775528dd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts @@ -22,3 +22,65 @@ stdout-path = "serial0:115200n8"; }; }; + +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; + reg = <3 0 0x300>; /* TODO check address */ + ranges = <0 3 0 0x300>; + + mdio_mux_emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + phy-connection-type = "sgmii"; + }; + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + phy-connection-type = "sgmii"; + }; + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + phy-connection-type = "sgmii"; + }; + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + phy-connection-type = "sgmii"; + }; + }; + }; + }; +}; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; +}; +&dpmac10 { + phy-handle = <&mdio0_phy13>; +}; +&dpmac11 { + phy-handle = <&mdio0_phy14>; +}; +&dpmac12 { + phy-handle = <&mdio0_phy15>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index f6b4d75a258b..a32b0f6e9238 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -22,3 +22,83 @@ stdout-path = "serial1:115200n8"; }; }; + +&emdio1 { + status = "disabled"; + /* CS4340 PHYs */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x10>; + phy-connection-type = "xfi"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x11>; + phy-connection-type = "xfi"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x12>; + phy-connection-type = "xfi"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x13>; + phy-connection-type = "xfi"; + }; +}; + +&emdio2 { + /* AQR405 PHYs */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 1 0x4>; /* Level high type */ + reg = <0x0>; + phy-connection-type = "xfi"; + }; + mdio2_phy2: emdio2_phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; /* Level high type */ + reg = <0x1>; + phy-connection-type = "xfi"; + }; + mdio2_phy3: emdio2_phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 4 0x4>; /* Level high type */ + reg = <0x2>; + phy-connection-type = "xfi"; + }; + mdio2_phy4: emdio2_phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 5 0x4>; /* Level high type */ + reg = <0x3>; + phy-connection-type = "xfi"; + }; +}; + +/* Update DPMAC connections to external PHYs, under the assumption of + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. + */ +/* Leave Cortina PHYs commented out until proper driver is integrated + *&dpmac1 { + * phy-handle = <&mdio1_phy1>; + *}; + *&dpmac2 { + * phy-handle = <&mdio1_phy2>; + *}; + *&dpmac3 { + * phy-handle = <&mdio1_phy3>; + *}; + *&dpmac4 { + * phy-handle = <&mdio1_phy4>; + *}; + */ + +&dpmac5 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac6 { + phy-handle = <&mdio2_phy2>; +}; +&dpmac7 { + phy-handle = <&mdio2_phy3>; +}; +&dpmac8 { + phy-handle = <&mdio2_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index a5f668d786b8..c699b65dbfe3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -12,7 +12,7 @@ #include "fsl-ls208xa.dtsi" &cpu { - cpu0: cpu@0 { + cooling_map0: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; @@ -32,7 +32,7 @@ #cooling-cells = <2>; }; - cpu2: cpu@100 { + cooling_map1: cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x100>; @@ -52,7 +52,7 @@ #cooling-cells = <2>; }; - cpu4: cpu@200 { + cooling_map2: cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x200>; @@ -72,7 +72,7 @@ #cooling-cells = <2>; }; - cpu6: cpu@300 { + cooling_map3: cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x300>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index 10d2fe091965..2d05e840fd24 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -129,6 +129,7 @@ &qspi { status = "okay"; + fsl,qspi-has-second-chip; flash0: s25fl256s1@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi index 6fd7f63085c9..4c4fde6b6d31 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi @@ -49,6 +49,7 @@ reg = <0x75>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-never-disable; i2c@1 { #address-cells = <1>; #size-cells = <0>; @@ -108,7 +109,15 @@ }; &qspi { - status = "disabled"; + status = "okay"; + + s25fs512s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; }; &sata0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index cdb2fa47637d..331c72672ed9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-2080A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * * Abhimanyu Saini <abhimanyu.saini@nxp.com> * @@ -24,6 +24,7 @@ serial1 = &serial1; serial2 = &serial2; serial3 = &serial3; + rtc1 = &ftm_alarm0; }; cpu: cpus { @@ -77,50 +78,14 @@ mask = <0x2>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; + #include "fsl-tmu.dtsi" - thermal-sensors = <&tmu 4>; - - trips { - cpu_alert: cpu-alert { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <85000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { + timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ <1 14 4>, /* Physical Non-Secure PPI, active-low */ <1 11 4>, /* Virtual PPI, active-low */ <1 10 4>; /* Hypervisor PPI, active-low */ - fsl,erratum-a008585; }; pmu { @@ -559,15 +524,42 @@ #interrupt-cells = <2>; }; + /* TODO: WRIOP (CCSR?) */ + emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO1: 0x1_6000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + device_type = "mdio"; /* TODO: is this necessary? */ + little-endian; /* force the driver in LE mode */ + + /* Not necessary on the QDS, but needed on the RDB */ + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO2: 0x1_7000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + device_type = "mdio"; /* TODO: is this necessary? */ + little-endian; /* force the driver in LE mode */ + + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0: i2c@2000000 { status = "disabled"; - compatible = "fsl,vf610-i2c"; + compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; + scl-gpios = <&gpio3 10 0>; }; i2c1: i2c@2010000 { @@ -578,7 +570,7 @@ reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; i2c2: i2c@2020000 { @@ -589,7 +581,7 @@ reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; i2c3: i2c@2030000 { @@ -600,7 +592,7 @@ reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen 4 1>; }; ifc: ifc@2240000 { @@ -617,23 +609,23 @@ }; qspi: spi@20c0000 { - status = "disabled"; - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; + compatible = "fsl,ls2080a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 25 0x4>; /* Level high type */ + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "qspi_en", "qspi"; + status = "disabled"; }; pcie1: pcie@3400000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 108 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -641,6 +633,7 @@ num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, @@ -653,8 +646,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 113 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -662,6 +655,7 @@ num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, @@ -674,8 +668,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 118 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 118 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -683,6 +677,7 @@ num-viewport = <256>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, @@ -695,8 +690,8 @@ pcie4: pcie@3700000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 123 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 123 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -704,6 +699,7 @@ num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, @@ -733,24 +729,26 @@ usb0: usb3@3100000 { status = "disabled"; - compatible = "snps,dwc3"; + compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; usb1: usb3@3110000 { status = "disabled"; - compatible = "snps,dwc3"; + compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; ccn@4000000 { @@ -758,6 +756,20 @@ reg = <0x0 0x04000000 0x0 0x01000000>; interrupts = <0 12 4>; }; + + rcpm: rcpm@1e34040 { + compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls208xa-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <0 44 4>; + }; }; ddr1: memory-controller@1080000 { @@ -781,3 +793,36 @@ }; }; }; + +#include "fsl-tmu-map1.dtsi" +#include "fsl-tmu-map2.dtsi" +#include "fsl-tmu-map3.dtsi" +&thermal_zones { + thermal-zone1 { + status = "okay"; + }; + + thermal-zone2{ + status = "okay"; + }; + + thermal-zone3{ + status = "okay"; + }; + + thermal-zone4{ + status = "okay"; + }; + + thermal-zone5{ + status = "okay"; + }; + + thermal-zone6{ + status = "okay"; + }; + + thermal-zone7 { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 1a5acf62f23c..a0c27b5bac0d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -2,7 +2,7 @@ // // Device Tree file for LX2160AQDS // -// Copyright 2018 NXP +// Copyright 2018-2019 NXP /dts-v1/; @@ -29,12 +29,188 @@ regulator-boot-on; regulator-always-on; }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* On-board PHY #1 RGMI1*/ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { /* On-board PHY #2 RGMI2*/ + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@18 { /* Slot #1 */ + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@19 { /* Slot #2 */ + reg = <0x19>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1a { /* Slot #3 */ + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1b { /* Slot #4 */ + reg = <0x1b>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1c { /* Slot #5 */ + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1d { /* Slot #6 */ + reg = <0x1d>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1e { /* Slot #7 */ + reg = <0x1e>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1f { /* Slot #8 */ + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* Slot #1 (secondary EMI) */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { /* Slot #2 (secondary EMI) */ + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* Slot #3 (secondary EMI) */ + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* Slot #4 (secondary EMI) */ + reg = <0x03>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@4 { /* Slot #5 (secondary EMI) */ + reg = <0x04>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@5 { /* Slot #6 (secondary EMI) */ + reg = <0x05>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@6 { /* Slot #7 (secondary EMI) */ + reg = <0x06>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@7 { /* Slot #8 (secondary EMI) */ + reg = <0x07>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; }; &crypto { status = "okay"; }; +&dspi0 { + status = "okay"; + + dflash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi1 { + status = "okay"; + + dflash1: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi2 { + status = "okay"; + + dflash2: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -46,6 +222,19 @@ &i2c0 { status = "okay"; + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ + }; + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; @@ -126,3 +315,19 @@ &usb1 { status = "okay"; }; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index c2817b784232..2ec43c6fbc98 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -2,7 +2,7 @@ // // Device Tree file for LX2160ARDB // -// Copyright 2018 NXP +// Copyright 2018-2019 NXP /dts-v1/; @@ -31,10 +31,34 @@ }; }; +&can0 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + &crypto { status = "okay"; }; +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { sd-uhs-sdr104; sd-uhs-sdr50; @@ -159,3 +183,65 @@ &usb1 { status = "okay"; }; + +&emdio1 { + rgmii_phy1: ethernet-phy@1 { + /* AR8035 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x1>; + /* Poll mode - no "interrupts" property defined */ + }; + rgmii_phy2: ethernet-phy@2 { + /* AR8035 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x2>; + /* Poll mode - no "interrupts" property defined */ + }; + aquantia_phy1: ethernet-phy@4 { + /* AQR107 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x4>; + }; + aquantia_phy2: ethernet-phy@5 { + /* AQR107 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5>; + }; +}; + +&emdio2 { + inphi_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; +}; + +&dpmac3 { + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + phy-handle = <&inphi_phy>; +}; + +&dpmac6 { + phy-handle = <&inphi_phy>; +}; + +&dpmac17 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index b032f3890c8c..cab7468c3df0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -2,10 +2,11 @@ // // Device Tree Include file for Layerscape-LX2160A family SoC. // -// Copyright 2018 NXP +// Copyright 2018-2019 NXP #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> /memreserve/ 0x80000000 0x00010000; @@ -15,12 +16,16 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + rtc1 = &ftm_alarm0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; // 8 clusters having 2 Cortex-A72 cores each - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -34,9 +39,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -50,9 +56,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@100 { + cpu100: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -66,9 +73,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@101 { + cpu101: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -82,9 +90,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@200 { + cpu200: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -98,9 +107,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@201 { + cpu201: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -114,9 +124,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@300 { + cpu300: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -130,9 +141,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@301 { + cpu301: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -146,9 +158,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@400 { + cpu400: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -162,9 +175,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@401 { + cpu401: cpu@401 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -178,9 +192,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@500 { + cpu500: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -194,9 +209,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@501 { + cpu501: cpu@501 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -210,9 +226,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@600 { + cpu600: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -226,9 +243,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@601 { + cpu601: cpu@601 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -242,9 +260,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@700 { + cpu700: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -258,9 +277,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; - cpu@701 { + cpu701: cpu@701 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -274,6 +294,7 @@ i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw15>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { @@ -418,6 +439,51 @@ clock-output-names = "sysclk"; }; + thermal-zones { + core_thermal1: core-thermal1 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core_cluster_crit: core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -478,6 +544,28 @@ little-endian; }; + /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + little-endian; /* force the driver in LE mode */ + status = "disabled"; + }; + + /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + little-endian; /* force the driver in LE mode */ + status = "disabled"; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; @@ -486,7 +574,7 @@ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -531,7 +619,7 @@ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -581,6 +669,45 @@ status = "disabled"; }; + dspi0: spi@2100000 { + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 7>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + status = "disabled"; + }; + + dspi1: spi@2110000 { + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 7>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <1>; + status = "disabled"; + }; + + dspi2: spi@2120000 { + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 4 7>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <2>; + status = "disabled"; + }; + esdhc0: esdhc@2140000 { compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; @@ -606,6 +733,38 @@ status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>, <&clockgen 4 7>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>, <&clockgen 4 7>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0x800000E6 0x8001017D>; + fsl,tmu-calibration = + /* Calibration data group 1 */ + <0x00000000 0x00000035 + /* Calibration data group 2 */ + 0x00010001 0x00000154>; + little-endian; + #thermal-sensor-cells = <1>; + }; + uart0: serial@21c0000 { compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21c0000 0x0 0x1000>; @@ -690,25 +849,46 @@ timeout-sec = <30>; }; + rcpm: rcpm@1e34040 { + compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x1c>; + #fsl,rcpm-wakeup-cells = <7>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,lx2160a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = <0 44 4>; + }; + usb0: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb1: usb@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; + snps,dis-u1u2-when-u3-quirk; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; status = "disabled"; }; @@ -756,6 +936,230 @@ status = "disabled"; }; + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3400000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3500000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + + pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3600000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x90 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + max-functions = <2>; + status = "disabled"; + }; + + pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3700000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03700000 0x0 0x00100000 + 0x98 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + + pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3800000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03800000 0x0 0x00100000 + 0xa0 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + max-functions = <2>; + status = "disabled"; + }; + + pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie_ep@3900000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03900000 0x0 0x00100000 + 0xa8 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; @@ -978,4 +1382,11 @@ }; }; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi new file mode 100644 index 000000000000..87e0d2ea5879 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian <andy.tang@nxp.com> + * + */ + +&thermal_zones { + thermal-zone0 { + cooling-maps { + map1 { + trip = <&alert0>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + cooling-maps { + map1 { + trip = <&alert1>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + cooling-maps { + map1 { + trip = <&alert2>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + cooling-maps { + map1 { + trip = <&alert3>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + cooling-maps { + map1 { + trip = <&alert4>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + cooling-maps { + map1 { + trip = <&alert5>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + cooling-maps { + map1 { + trip = <&alert6>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + cooling-maps { + map1 { + trip = <&alert7>; + cooling-device = + <&cooling_map1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi new file mode 100644 index 000000000000..7e350736821c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian <andy.tang@nxp.com> + * + */ + +&thermal_zones { + thermal-zone0 { + cooling-maps { + map2 { + trip = <&alert0>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + cooling-maps { + map2 { + trip = <&alert1>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + cooling-maps { + map2 { + trip = <&alert2>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + cooling-maps { + map2 { + trip = <&alert3>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + cooling-maps { + map2 { + trip = <&alert4>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + cooling-maps { + map2 { + trip = <&alert5>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + cooling-maps { + map2 { + trip = <&alert6>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + cooling-maps { + map2 { + trip = <&alert7>; + cooling-device = + <&cooling_map2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi new file mode 100644 index 000000000000..dcde9432fd2a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian <andy.tang@nxp.com> + * + */ + +&thermal_zones { + thermal-zone0 { + cooling-maps { + map3 { + trip = <&alert0>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + cooling-maps { + map3 { + trip = <&alert1>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + cooling-maps { + map3 { + trip = <&alert2>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + cooling-maps { + map3 { + trip = <&alert3>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + cooling-maps { + map3 { + trip = <&alert4>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + cooling-maps { + map3 { + trip = <&alert5>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + cooling-maps { + map3 { + trip = <&alert6>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + cooling-maps { + map3 { + trip = <&alert7>; + cooling-device = + <&cooling_map3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi b/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi new file mode 100644 index 000000000000..133d2dc8e61b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Thermal Monitor Unit. + * + * Copyright 2018 NXP + * + * Tang Yuantian <andy.tang@nxp.com> + * + */ + +thermal_zones: thermal-zones { + thermal_zone0: thermal-zone0 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + status = "disabled"; + + trips { + alert0: alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit0: crit0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert0>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone1 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + status = "disabled"; + + trips { + alert1: alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit1: crit1 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert1>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone2 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 2>; + status = "disabled"; + + trips { + alert2: alert2 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit2: crit2 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert2>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 3>; + status = "disabled"; + + trips { + alert3: alert3 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit3: crit3 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert3>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone4 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 4>; + status = "disabled"; + + trips { + alert4: alert4 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit4: crit4 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert4>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone5 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 5>; + status = "disabled"; + + trips { + alert5: alert5 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit5: crit5 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert5>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone6 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 6>; + status = "disabled"; + + trips { + alert6: alert6 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit6: crit6 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert6>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + thermal-zone7 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 7>; + status = "disabled"; + + trips { + alert7: alert7 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + crit7: crit7 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert7>; + cooling-device = + <&cooling_map0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi new file mode 100644 index 000000000000..841758bd2c8c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include "imx8-ss-audio.dtsi" +#include "imx8-ss-dma.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi new file mode 100644 index 000000000000..8698c5566e93 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -0,0 +1,668 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +audio_subsys: bus@59000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x59000000 0x0 0x59000000 0x1000000>; + + audio_ipg_clk: clock-audio-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <175000000>; + clock-output-names = "audio_ipg_clk"; + }; + + edma0: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59260000 0x10000>, /* esai0 rx */ + <0x59270000 0x10000>, /* esai0 tx */ + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <18>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan6", "edma0-chan7", + "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan21", "edma0-chan23"; + status = "okay"; + }; + + edma1: dma-controller@599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59A00000 0x10000>, /* asrc1 */ + <0x59A10000 0x10000>, + <0x59A20000 0x10000>, + <0x59A30000 0x10000>, + <0x59A40000 0x10000>, + <0x59A50000 0x10000>, + <0x59A80000 0x10000>, /* sai4 rx */ + <0x59A90000 0x10000>, /* sai4 tx */ + <0x59AA0000 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ + "edma1-chan2-rx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ + "edma1-chan10-tx"; /* sai5 */ + power-domains = <&pd IMX_SC_R_DMA_1_CH0>, + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH8>, + <&pd IMX_SC_R_DMA_1_CH9>, + <&pd IMX_SC_R_DMA_1_CH10>; + power-domain-names = "edma1-chan0", "edma1-chan1", + "edma1-chan2", "edma1-chan3", + "edma1-chan4", "edma1-chan5", + "edma1-chan8", "edma1-chan9", + "edma1-chan10"; + status = "okay"; + }; + + acm: acm@59e00000 { + compatible = "nxp,imx8qxp-acm"; + reg = <0x59e00000 0x1D0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x59000000 0x10000>; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&asrc0_lpcg 0>, + <&asrc0_lpcg 0>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, + <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd IMX_SC_R_ASRC_0>; + status = "disabled"; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; + reg = <0x59010000 0x10000>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&esai0_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 1>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59020000 0x10000>; + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&spdif0_lpcg 1>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg 0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + status = "disabled"; + }; + + spdif1: spdif@59030000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59030000 0x10000>; + interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&spdif1_lpcg 1>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif1_lpcg 0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 10 0 5>, <&edma0 11 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59040000 0x10000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai0_lpcg 1>, + <&clk_dummy>, + <&sai0_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + power-domains = <&pd IMX_SC_R_SAI_0>; + status = "disabled"; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59050000 0x10000>; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai1_lpcg 1>, + <&clk_dummy>, + <&sai1_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + power-domains = <&pd IMX_SC_R_SAI_1>; + status = "disabled"; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59060000 0x10000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai2_lpcg 1>, + <&clk_dummy>, + <&sai2_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + power-domains = <&pd IMX_SC_R_SAI_2>; + status = "disabled"; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59070000 0x10000>; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai3_lpcg 1>, + <&clk_dummy>, + <&sai3_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + power-domains = <&pd IMX_SC_R_SAI_3>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x59800000 0x10000>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&asrc1_lpcg 0>, + <&asrc1_lpcg 0>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>, + <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd IMX_SC_R_ASRC_1>; + status = "disabled"; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai4_lpcg 1>, + <&clk_dummy>, + <&sai4_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai5_lpcg 1>, + <&clk_dummy>, + <&sai5_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-audmix"; + reg = <0x59840000 0x10000>; + clocks = <&amix_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_AMIX>; + dais = <&sai4>, <&sai5>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x59850000 0x10000>; + clocks = <&mqs0_lpcg 1>, + <&mqs0_lpcg 0>; + clock-names = "core", "mclk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + status = "disabled"; + }; + + asrc0_lpcg: clock-controller@59400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59400000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "asrc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_0>; + }; + + esai0_lpcg: clock-controller@59410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59410000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + }; + + spdif0_lpcg: clock-controller@59420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59420000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + }; + + spdif1_lpcg: clock-controller@59430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59430000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + + sai0_lpcg: clock-controller@59440000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59440000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_0>; + }; + + sai1_lpcg: clock-controller@59450000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59450000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_1>; + }; + + sai2_lpcg: clock-controller@59460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59460000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_2>; + }; + + sai3_lpcg: clock-controller@59470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59470000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_3>; + }; + + dsp_lpcg: clock-controller@59580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59580000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <16 20 28>; + clock-output-names = "dsp_lpcg_adb_aclk", + "dsp_lpcg_ipg_clk", + "dsp_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_DSP>; + }; + + dsp_ram_lpcg: clock-controller@59590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59590000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "dsp_ram_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_DSP_RAM>; + }; + + asrc1_lpcg: clock-controller@59c00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c00000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "asrc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_1>; + }; + + sai4_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + }; + + sai5_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + }; + + amix_lpcg: clock-controller@59c40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c40000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <0>; + clock-output-names = "amix_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_AMIX>; + }; + + mqs0_lpcg: clock-controller@59c50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + }; + + aud_rec0_lpcg: clock-controller@59d00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + bit-offset = <0>; + clock-output-names = "aud_rec_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_rec1_lpcg: clock-controller@59d10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; + bit-offset = <0>; + clock-output-names = "aud_rec_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + aud_pll_div0_lpcg: clock-controller@59d20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; + bit-offset = <0>; + clock-output-names = "aud_pll_div_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_pll_div1_lpcg: clock-controller@59d30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; + bit-offset = <0>; + clock-output-names = "aud_pll_div_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + mclkout0_lpcg: clock-controller@59d50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; + bit-offset = <0>; + clock-output-names = "mclkout0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; + }; + + mclkout1_lpcg: clock-controller@59d60000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d60000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; + bit-offset = <0>; + clock-output-names = "mclkout1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi new file mode 100644 index 000000000000..5d853a93c1cb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +cm40_subsys: bus@34000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x34000000 0x0 0x34000000 0x4000000>; + + cm40_ipg_clk: clock-cm40-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm40_ipg_clk"; + }; + + cm40_i2c: i2c@37230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x37230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&cm40_intmux>; + clocks = <&cm40_i2c_lpcg 0>, + <&cm40_i2c_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + status = "disabled"; + }; + + cm40_i2c_lpcg: clock-controller@37630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "cm40_lpcg_i2c_clk", + "cm40_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + }; + + cm40_intmux: intmux@37400000 { + compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&cm40_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; + status = "disabled"; + }; + + cm40_lpuart: serial@37220000 { + compatible = "fsl,imx8qxp-lpuart"; + reg = <0x37220000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&cm40_intmux>; + clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + status = "disabled"; + }; + + cm40_uart_lpcg: clock-controller@37620000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37620000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + bit-offset = <0 4>; + clock-output-names = "cm40_lpcg_uart_clk", + "cm40_lpcg_uart_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi new file mode 100644 index 000000000000..19c38af5563c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +cm41_subsys: bus@38000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x38000000 0x0 0x38000000 0x4000000>; + + cm41_ipg_clk: clock-cm41-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm41_ipg_clk"; + }; + + cm41_i2c: i2c@3b230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x3b230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&cm41_intmux>; + clocks = <&cm41_i2c_lpcg 0>, + <&cm41_i2c_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + status = "disabled"; + }; + + cm41_i2c_lpcg: clock-controller@3b630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x3b630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>, + <&cm41_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "cm41_lpcg_i2c_clk", + "cm41_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + }; + + cm41_intmux: intmux@3b400000 { + compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux"; + reg = <0x3b400000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&cm41_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_1_INTMUX>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi new file mode 100644 index 000000000000..4eb51cad186d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +conn_subsys: bus@5b000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; + + conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; + }; + + conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; + }; + + conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; + }; + + conn_bch_clk: clock-conn-bch { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "conn_bch_clk"; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x5b0d0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + power-domains = <&pd IMX_SC_R_USB_0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0d0200 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", + "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x5b100000 0x1000>; + clocks = <&usb2_lpcg 1>; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "disabled"; + }; + + usdhc1: mmc@5b010000 { + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5b010000 0x10000>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; + power-domains = <&pd IMX_SC_R_SDHC_0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@5b020000 { + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5b020000 0x10000>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 0>, + <&sdhc1_lpcg 2>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@5b030000 { + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5b030000 0x10000>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 0>, + <&sdhc2_lpcg 2>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + reg = <0x5b040000 0x10000>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&enet0_lpcg 3>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + reg = <0x5b050000 0x10000>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&enet1_lpcg 3>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_1>; + status = "disabled"; + }; + + mlb: mlb@5b060000 { + compatible = "fsl,imx8qxp-mlb150"; + reg = <0x5B060000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mlb_lpcg 0>, + <&mlb_lpcg 1>, + <&mlb_lpcg 2>; + clock-names = "mlb", "hclk", "ipg"; + power-domains = <&pd IMX_SC_R_MLB_0>; + status = "disabled"; + }; + + usb3phynop1: usb3-phy { + compatible = "usb-nop-xceiv"; + clocks = <&usb3_lpcg 4>; + clock-names = "main_clk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + status = "disabled"; + }; + + usbotg3: usb3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x5B110000 0x10000>, + <0x5B130000 0x10000>, + <0x5B140000 0x10000>, + <0x5B160000 0x40000>, + <0x5B120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb3_lpcg 1>, + <&usb3_lpcg 0>, + <&usb3_lpcg 5>, + <&usb3_lpcg 2>, + <&usb3_lpcg 3>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <125000000>, <12000000>, <250000000>; + power-domains = <&pd IMX_SC_R_USB_2>; + cdns3,usbphy = <&usb3phynop1>; + status = "disabled"; + }; + + /* LPCG clocks */ + sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; + + sdhc1_lpcg: clock-controller@5b210000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b210000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc1_lpcg_per_clk", + "sdhc1_lpcg_ipg_clk", + "sdhc1_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_1>; + }; + + sdhc2_lpcg: clock-controller@5b220000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b220000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc2_lpcg_per_clk", + "sdhc2_lpcg_ipg_clk", + "sdhc2_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_2>; + }; + + enet0_lpcg: clock-controller@5b230000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b230000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; + bit-offset = <0 4 8 12 16 20>; + clock-output-names = "enet0_lpcg_timer_clk", + "enet0_lpcg_txc_sampling_clk", + "enet0_lpcg_ahb_clk", + "enet0_lpcg_rgmii_txc_clk", + "enet0_lpcg_ipg_clk", + "enet0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_0>; + }; + + enet1_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; + bit-offset = <0 4 8 12 16 20>; + clock-output-names = "enet1_lpcg_timer_clk", + "enet1_lpcg_txc_sampling_clk", + "enet1_lpcg_ahb_clk", + "enet1_lpcg_rgmii_txc_clk", + "enet1_lpcg_ipg_clk", + "enet1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; + + mlb_lpcg: clock-controller@5b260000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b260000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_axi_clk>, + <&conn_axi_clk>, + <&conn_ipg_clk>; + bit-offset = <0 20 16>; + clock-output-names = "mlb_lpcg_clk", + "mlb_lpcg_hclk", + "mlb_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MLB_0>; + }; + + usb2_lpcg: clock-controller@5b270000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b270000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; + bit-offset = <24 28>; + clock-output-names = "usboh3_ahb_clk", + "usboh3_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + }; + + usb3_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + bit-offset = <0 4 16 20 24 28>; + clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + clock-output-names = "usb3_app_clk", + "usb3_lpm_clk", + "usb3_ipg_clk", + "usb3_core_pclk", + "usb3_phy_clk", + "usb3_aclk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + }; + + rawnand_0_lpcg: clock-controller@5b290000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>, + <&conn_axi_clk>, + <&conn_axi_clk>; + bit-offset = <0 4 16 20>; + clock-output-names = "bch_clk", + "gpmi_clk", + "gpmi_apb_clk", + "bch_apb_clk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + rawnand_4_lpcg: clock-controller@5b290004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290004 0x10000>; + #clock-cells = <1>; + clocks = <&conn_axi_clk>; + bit-offset = <16>; + clock-output-names = "apbhdma_hclk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x5b810000 0x2000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&rawnand_4_lpcg 0>; + clock-names = "apbhdma_hclk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&rawnand_0_lpcg 1>, + <&rawnand_0_lpcg 2>, + <&rawnand_0_lpcg 0>, + <&rawnand_0_lpcg 3>; + clock-names = "gpmi_clk", "gpmi_apb_clk", + "bch_clk", "bch_apb_clk"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd IMX_SC_R_NAND>; + assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi new file mode 100644 index 000000000000..eef051915fcc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019,2020 NXP + */ + +dc0_subsys: bus@56000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x0 0x56000000 0x300000>; + + dc0_cfg_clk: clock-dc-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "dc0_cfg_clk"; + }; + + dc0_axi_int_clk: clock-dc-axi-int { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "dc0_axi_int_clk"; + }; + + dc0_axi_ext_clk: clock-dc-axi-ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "dc0_axi_ext_clk"; + }; + + dc0_disp_lpcg: clock-controller@56010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_dpr0_lpcg: clock-controller@56010018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010018 0x4>; + #clock-cells = <1>; + clocks = <&dc0_cfg_clk>, + <&dc0_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc0_dpr0_lpcg_apb_clk", + "dc0_dpr0_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_rtram0_lpcg: clock-controller@5601001c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601001c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc0_rtram0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + + dc0_prg0_lpcg: clock-controller@56010020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010020 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg0_lpcg_rtram_clk", + "dc0_prg0_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg1_lpcg: clock-controller@56010024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010024 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg1_lpcg_rtram_clk", + "dc0_prg1_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg2_lpcg: clock-controller@56010028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010028 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg2_lpcg_rtram_clk", + "dc0_prg2_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_dpr1_lpcg: clock-controller@5601002c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601002c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_cfg_clk>, + <&dc0_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc0_dpr1_lpcg_apb_clk", + "dc0_dpr1_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_rtram1_lpcg: clock-controller@56010030 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010030 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc0_rtram1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg3_lpcg: clock-controller@56010034 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010034 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg3_lpcg_rtram_clk", + "dc0_prg3_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg4_lpcg: clock-controller@56010038 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010038 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg4_lpcg_rtram_clk", + "dc0_prg4_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg5_lpcg: clock-controller@5601003c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601003c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg5_lpcg_rtram_clk", + "dc0_prg5_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg6_lpcg: clock-controller@56010040 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010040 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg6_lpcg_rtram_clk", + "dc0_prg6_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg7_lpcg: clock-controller@56010044 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010044 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg7_lpcg_rtram_clk", + "dc0_prg7_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg8_lpcg: clock-controller@56010048 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010048 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg8_lpcg_rtram_clk", + "dc0_prg8_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_irqsteer: irqsteer@56000000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56000000 0x10000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dc0_cfg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_pc: pixel-combiner@56020000 { + compatible = "fsl,imx8qxp-pixel-combiner", + "fsl,imx8qm-pixel-combiner"; + reg = <0x56020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg1: prg@56040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg 0>, + <&dc0_prg0_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg2: prg@56050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56050000 0x10000>; + clocks = <&dc0_prg1_lpcg 0>, + <&dc0_prg1_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg3: prg@56060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56060000 0x10000>; + clocks = <&dc0_prg2_lpcg 0>, + <&dc0_prg2_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg4: prg@56070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56070000 0x10000>; + clocks = <&dc0_prg3_lpcg 0>, + <&dc0_prg3_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg5: prg@56080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56080000 0x10000>; + clocks = <&dc0_prg4_lpcg 0>, + <&dc0_prg4_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg6: prg@56090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56090000 0x10000>; + clocks = <&dc0_prg5_lpcg 0>, + <&dc0_prg5_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg7: prg@560a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560a0000 0x10000>; + clocks = <&dc0_prg6_lpcg 0>, + <&dc0_prg6_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg8: prg@560b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560b0000 0x10000>; + clocks = <&dc0_prg7_lpcg 0>, + <&dc0_prg7_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg9: prg@560c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560c0000 0x10000>; + clocks = <&dc0_prg8_lpcg 0>, + <&dc0_prg8_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel1: dpr-channel@560d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560d0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_BLIT0>; + fsl,prgs = <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel2: dpr-channel@560e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560e0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>; + fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel3: dpr-channel@560f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560f0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_FRAC0>; + fsl,prgs = <&dc0_prg3>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel1: dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56100000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>; + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel2: dpr-channel@56110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56110000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO1>; + fsl,prgs = <&dc0_prg6>, <&dc0_prg7>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel3: dpr-channel@56120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56120000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_WARP>; + fsl,prgs = <&dc0_prg8>, <&dc0_prg9>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <5>, + <0>, <1>, <2>, <3>, + <4>, <82>, <83>, <84>, + <85>, <209>, <210>, <211>, + <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "reserved", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>, + <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + fsl,pixel-combiner = <&dc0_pc>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi new file mode 100644 index 000000000000..c05a3eb7f9e5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +dc1_subsys: bus@57000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57000000 0x0 0x57000000 0x300000>; + + dc1_cfg_clk: clock-dc-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "dc1_cfg_clk"; + }; + + dc1_axi_int_clk: clock-dc-axi-int { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "dc1_axi_int_clk"; + }; + + dc1_axi_ext_clk: clock-dc-axi-ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "dc1_axi_ext_clk"; + }; + + dc1_disp_lpcg: clock-controller@57010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc1_disp0_lpcg_clk", "dc1_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_dpr0_lpcg: clock-controller@57010018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010018 0x4>; + #clock-cells = <1>; + clocks = <&dc1_cfg_clk>, + <&dc1_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc1_dpr0_lpcg_apb_clk", + "dc1_dpr0_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_rtram0_lpcg: clock-controller@5701001c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701001c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc1_rtram0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + + dc1_prg0_lpcg: clock-controller@57010020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010020 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg0_lpcg_rtram_clk", + "dc1_prg0_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg1_lpcg: clock-controller@57010024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010024 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg1_lpcg_rtram_clk", + "dc1_prg1_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg2_lpcg: clock-controller@57010028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010028 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg2_lpcg_rtram_clk", + "dc1_prg2_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_dpr1_lpcg: clock-controller@5701002c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701002c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_cfg_clk>, + <&dc1_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc1_dpr1_lpcg_apb_clk", + "dc1_dpr1_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_rtram1_lpcg: clock-controller@57010030 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010030 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc1_rtram1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg3_lpcg: clock-controller@57010034 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010034 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg3_lpcg_rtram_clk", + "dc1_prg3_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg4_lpcg: clock-controller@57010038 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010038 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg4_lpcg_rtram_clk", + "dc1_prg4_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg5_lpcg: clock-controller@5701003c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701003c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg5_lpcg_rtram_clk", + "dc1_prg5_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg6_lpcg: clock-controller@57010040 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010040 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg6_lpcg_rtram_clk", + "dc1_prg6_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg7_lpcg: clock-controller@57010044 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010044 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg7_lpcg_rtram_clk", + "dc1_prg7_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg8_lpcg: clock-controller@57010048 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010048 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg8_lpcg_rtram_clk", + "dc1_prg8_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_irqsteer: irqsteer@57000000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57000000 0x10000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dc1_cfg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_pc: pixel-combiner@57020000 { + compatible = "fsl,imx8qxp-pixel-combiner", + "fsl,imx8qm-pixel-combiner"; + reg = <0x57020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg1: prg@57040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57040000 0x10000>; + clocks = <&dc1_prg0_lpcg 0>, + <&dc1_prg0_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg2: prg@57050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57050000 0x10000>; + clocks = <&dc1_prg1_lpcg 0>, + <&dc1_prg1_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg3: prg@57060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57060000 0x10000>; + clocks = <&dc1_prg2_lpcg 0>, + <&dc1_prg2_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg4: prg@57070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57070000 0x10000>; + clocks = <&dc1_prg3_lpcg 0>, + <&dc1_prg3_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg5: prg@57080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57080000 0x10000>; + clocks = <&dc1_prg4_lpcg 0>, + <&dc1_prg4_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg6: prg@57090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57090000 0x10000>; + clocks = <&dc1_prg5_lpcg 0>, + <&dc1_prg5_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg7: prg@570a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570a0000 0x10000>; + clocks = <&dc1_prg6_lpcg 0>, + <&dc1_prg6_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg8: prg@570b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570b0000 0x10000>; + clocks = <&dc1_prg7_lpcg 0>, + <&dc1_prg7_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg9: prg@570c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570c0000 0x10000>; + clocks = <&dc1_prg8_lpcg 0>, + <&dc1_prg8_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel1: dpr-channel@570d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570d0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_BLIT0>; + fsl,prgs = <&dc1_prg1>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel2: dpr-channel@570e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570e0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_BLIT1>; + fsl,prgs = <&dc1_prg2>, <&dc1_prg1>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel3: dpr-channel@570f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570f0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_FRAC0>; + fsl,prgs = <&dc1_prg3>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel1: dpr-channel@57100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57100000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_VIDEO0>; + fsl,prgs = <&dc1_prg4>, <&dc1_prg5>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel2: dpr-channel@57110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57110000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_VIDEO1>; + fsl,prgs = <&dc1_prg6>, <&dc1_prg7>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel3: dpr-channel@57120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57120000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_WARP>; + fsl,prgs = <&dc1_prg8>, <&dc1_prg9>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dpu2: dpu@57180000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x57180000 0x40000>; + interrupt-parent = <&dc1_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <5>, + <0>, <1>, <2>, <3>, + <4>, <82>, <83>, <84>, + <85>, <209>, <210>, <211>, + <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "reserved", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>, + <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; + power-domains = <&pd IMX_SC_R_DC_1>, + <&pd IMX_SC_R_DC_1_PLL_0>, + <&pd IMX_SC_R_DC_1_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc1_dpr1_channel1>, + <&dc1_dpr1_channel2>, + <&dc1_dpr1_channel3>, + <&dc1_dpr2_channel1>, + <&dc1_dpr2_channel2>, + <&dc1_dpr2_channel3>; + fsl,pixel-combiner = <&dc1_pc>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi new file mode 100644 index 000000000000..89dd105b2c44 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +ddr_subsys: bus@5c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; + + ddr_pmu0: ddr-pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c020000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi new file mode 100644 index 000000000000..fd1faaca1909 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -0,0 +1,611 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +dma_subsys: bus@5a000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + dma_ipg_clk: clock-dma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dma_ipg_clk"; + }; + + lpspi0: spi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi0_lpcg 0>, + <&spi0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <20000000>; + power-domains = <&pd IMX_SC_R_SPI_0>; + dma-names = "tx","rx"; + dmas = <&edma2 1 0 0>, <&edma2 0 0 1>; + status = "disabled"; + }; + + lpspi2: spi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi2_lpcg 0>, + <&spi2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_2>; + dma-names = "tx","rx"; + dmas = <&edma2 5 0 0>, <&edma2 4 0 1>; + status = "disabled"; + }; + + lpspi3: spi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi3_lpcg 0>, + <&spi3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_3>; + dma-names = "tx","rx"; + dmas = <&edma2 7 0 0>, <&edma2 6 0 1>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + reg = <0x5a060000 0x1000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + reg = <0x5a070000 0x1000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_1>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + reg = <0x5a080000 0x1000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_2>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, + <&edma2 12 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + reg = <0x5a090000 0x1000>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_3>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; + status = "disabled"; + }; + + emvsim0: sim0@5a0d0000 { + compatible = "fsl,imx8-emvsim"; + reg = <0x5a0d0000 0x10000>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&emvsim0_lpcg 0>, + <&emvsim0_lpcg 1>; + clock-names = "sim", "ipg"; + assigned-clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_EMVSIM_0>, <&pd IMX_SC_R_BOARD_R2>; + power-domain-names = "sim_pd", "sim_aux_pd"; + status = "disabled"; + }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ + <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ + <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ + <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a280000 0x10000>, /* channel8 UART0 rx */ + <0x5a290000 0x10000>, /* channel9 UART0 tx */ + <0x5a2a0000 0x10000>, /* channel10 UART1 rx */ + <0x5a2b0000 0x10000>, /* channel11 UART1 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART2 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART2 tx */ + <0x5a2e0000 0x10000>, /* channel14 UART3 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <16>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx", + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-rx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", + "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>; + power-domain-names = "edma2-chan0", "edma2-chan1", + "edma2-chan2", "edma2-chan3", + "edma2-chan4", "edma2-chan5", + "edma2-chan6", "edma2-chan7", + "edma2-chan8", "edma2-chan9", + "edma2-chan10", "edma2-chan11", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15"; + status = "disabled"; + }; + + spi0_lpcg: clock-controller@5a400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi0_lpcg_clk", + "spi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_0>; + }; + + spi1_lpcg: clock-controller@5a410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi1_lpcg_clk", + "spi1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_1>; + }; + + spi2_lpcg: clock-controller@5a420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi2_lpcg_clk", + "spi2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_2>; + }; + + spi3_lpcg: clock-controller@5a430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi3_lpcg_clk", + "spi3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_3>; + }; + + uart0_lpcg: clock-controller@5a460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_0>; + }; + + uart1_lpcg: clock-controller@5a470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_1>; + }; + + uart2_lpcg: clock-controller@5a480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_2>; + }; + + uart3_lpcg: clock-controller@5a490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_3>; + }; + + emvsim0_lpcg: clock-controller@5a4d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a4d0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "emvsim0_lpcg_clk", + "emvsim0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_EMVSIM_0>; + }; + + adc0: adc@5a880000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x5a880000 0x10000>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adc0_lpcg 0>, + <&adc0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + status = "disabled"; + }; + + adc1: adc@5a890000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x5a890000 0x10000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adc1_lpcg 0>, + <&adc1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_1>; + status = "disabled"; + }; + + + i2c0: i2c@5a800000 { + reg = <0x5a800000 0x4000>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&i2c0_lpcg 0>, + <&i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + reg = <0x5a810000 0x4000>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&i2c1_lpcg 0>, + <&i2c1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + reg = <0x5a820000 0x4000>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&i2c2_lpcg 0>, + <&i2c2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + reg = <0x5a830000 0x4000>; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&i2c3_lpcg 0>, + <&i2c3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_3>; + status = "disabled"; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source= <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = <0>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = <0>; + status = "disabled"; + }; + + adc0_lpcg: clock-controller@5ac80000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac80000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adc0_lpcg_clk", + "adc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_0>; + }; + + adc1_lpcg: clock-controller@5ac90000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac90000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adc1_lpcg_clk", + "adc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_1>; + }; + + i2c0_lpcg: clock-controller@5ac00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_0>; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_1>; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_2>; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_3>; + }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; + + i2c_rpbus_0: i2c-rpbus-0 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_5: i2c-rpbus-5 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_12: i2c-rpbus-12 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_13: i2c-rpbus-13 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_14: i2c-rpbus-14 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_15: i2c-rpbus-15 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + adma_pwm: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x5a190000 0x1000>; + clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + status = "disabled"; + }; + + adma_pwm_lpcg: clock-controller@5a590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a590000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adma_pwm_lpcg_clk", + "adma_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi new file mode 100644 index 000000000000..28aeeecb1832 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +gpu0_subsys: bus@53100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53100000 0x0 0x53100000 0x40000>, + <0x80000000 0x0 0x80000000 0x80000000>, + <0x0 0x0 0x0 0x10000000>; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x53100000 0x40000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi new file mode 100644 index 000000000000..0e84e5199a8f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +gpu1_subsys: bus@54100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x54100000 0x0 0x54100000 0x40000>, + <0x80000000 0x0 0x80000000 0x80000000>, + <0x0 0x0 0x0 0x10000000>; + + gpu_3d1: gpu@54100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x54100000 0x40000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = <IMX_SC_R_GPU_1_PID0>; + power-domains = <&pd IMX_SC_R_GPU_1_PID0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi new file mode 100644 index 000000000000..c6629e048777 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Richard Zhu <hongxing.zhu@nxp.com> + */ +#include <dt-bindings/soc/imx8_hsio.h> + +hsio_subsys: bus@5f000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */ + dma-ranges = <0x80000000 0 0x80000000 0x80000000>; + ranges = <0x5f000000 0x0 0x5f000000 0x21000000>; + + xtal100m: clock-xtal100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "xtal_100MHz"; + }; + + hsio_refa_clk: clock-hsio-refa { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + }; + + hsio_refb_clk: clock-hsio-refb { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + }; + + hsio_axi_clk: clock-hsio-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "hsio_axi_clk"; + }; + + hsio_per_clk: clock-hsio-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + clock-output-names = "hsio_per_clk"; + }; + + pcieb_lpcg: clock-controller@5f060000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f060000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + bit-offset = <16 20 24>; + clock-output-names = "hsio_pcieb_mstr_axi_clk", + "hsio_pcieb_slv_axi_clk", + "hsio_pcieb_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + phyx1_crr1_lpcg: clock-controller@5f0b0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0b0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_phyx1_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + pcieb_crr3_lpcg: clock-controller@5f0d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0d0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_pcieb_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + misc_crr5_lpcg: clock-controller@5f0f0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0f0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_misc_per_clk"; + power-domains = <&pd IMX_SC_R_HSIO_GPIO>; + }; + + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f010000 0x10000>, /* Controller reg */ + <0x7ff00000 0x80000>, /* PCI cfg space */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "dbi", "config", "hsio"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX2PCIEBX1>; + local-addr = <0x80000000>; + status = "disabled"; + }; + + pcieb_ep: pcie_ep@0x5f010000 { + compatible = "fsl,imx8qxp-pcie-ep"; + reg = <0x5f010000 0x00010000>, + <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */ + <0x70000000 0x10000000>; + reg-names = "regs", "hsio", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX2PCIEBX1>; + local-addr = <0x80000000>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi new file mode 100644 index 000000000000..c7be9fdc4df0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2020 NXP + * Zhou Guoniu <guoniu.zhou@nxp.com> + */ +img_subsys: bus@58000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x58000000 0x0 0x58000000 0x1000000>; + + img_ipg_clk: clock-img-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "img_ipg_clk"; + }; + + img_axi_clk: clock-img-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "img_axi_clk"; + }; + + img_pxl_clk: clock-img-pxl { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "img_pxl_clk"; + }; + + csi0_core_lpcg: clock-controller@58223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58223018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "csi0_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi0_esc_lpcg: clock-controller@5822301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5822301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; + bit-offset = <16>; + clock-output-names = "csi0_lpcg_esc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi1_core_lpcg: clock-controller@58243018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58243018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "csi1_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi1_esc_lpcg: clock-controller@5824301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5824301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; + bit-offset = <16>; + clock-output-names = "csi1_lpcg_esc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_pxl_lpcg: clock-controller@58263018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <0>; + clock-output-names = "pi0_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_ipg_lpcg: clock-controller@58263004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263004 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "pi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_misc_lpcg: clock-controller@5826301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5826301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "pi0_lpcg_misc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pdma0_lpcg: clock-controller@58500000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58500000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pdma1_lpcg: clock-controller@58510000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58510000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH1>; + }; + + pdma2_lpcg: clock-controller@58520000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58520000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma2_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH2>; + }; + + pdma3_lpcg: clock-controller@58530000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58530000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma3_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH3>; + }; + + pdma4_lpcg: clock-controller@58540000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58540000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma4_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH4>; + }; + + pdma5_lpcg: clock-controller@58550000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58550000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma5_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH5>; + }; + + pdma6_lpcg: clock-controller@58560000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58560000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma6_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH6>; + }; + + pdma7_lpcg: clock-controller@58570000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58570000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma7_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH7>; + }; + + csi0_pxl_lpcg: clock-controller@58580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58580000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "csi0_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_CSI_0>; + }; + + csi1_pxl_lpcg: clock-controller@58590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58590000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "csi1_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_CSI_1>; + }; + + img_jpeg_dec_clk: clock-controller@585d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x585d0000 0x10000>; + #clock-cells = <1>; + clocks = <&img_ipg_clk>, <&img_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_dec_clk", + "img_jpeg_dec_ipg_clk"; + power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; + }; + + img_jpeg_enc_clk: clock-controller@585f0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x585f0000 0x10000>; + #clock-cells = <1>; + clocks = <&img_ipg_clk>, <&img_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_enc_clk", + "img_jpeg_enc_ipg_clk"; + power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; + }; + + irqsteer_csi0: irqsteer@58220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58220000 0x1000>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&img_ipg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + irqsteer_csi1: irqsteer@58240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58240000 0x1000>; + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&img_ipg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + irqsteer_parallel: irqsteer@58260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58260000 0x1000>; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&clk_dummy>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + status = "disabled"; + }; + + gpio0_mipi_csi0: gpio@58222000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x58222000 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + }; + + i2c_mipi_csi0: i2c@58226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>; + status = "disabled"; + }; + + i2c0_parallel: i2c@58266000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58266000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_parallel>; + clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; + status = "disabled"; + }; + + gpio0_mipi_csi1: gpio@58242000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x58242000 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + }; + + i2c_mipi_csi1: i2c@58246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_csi1>; + clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma0_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + interface = <2 0 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + + m2m_device{ + compatible = "imx-isi-m2m"; + status = "disabled"; + }; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x58110000 0x10000>; + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma1_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH1>; + interface = <2 1 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x58120000 0x10000>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma2_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH2>; + interface = <2 2 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x58130000 0x10000>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma3_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH3>; + interface = <2 3 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x58140000 0x10000>; + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma4_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH4>; + interface = <3 0 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x58150000 0x10000>; + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma5_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH5>; + interface = <3 1 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x58160000 0x10000>; + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma6_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH6>; + interface = <3 2 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x58170000 0x10000>; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&pdma7_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH7>; + interface = <3 3 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58227000 0x1000>, + <0x58221000 0x1000>; + clocks = <&csi0_core_lpcg 0>, + <&csi0_esc_lpcg 0>, + <&csi0_pxl_lpcg 0>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi0_core_lpcg 0>, + <&csi0_esc_lpcg 0>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + mipi_csi_1: csi@58247000{ + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58247000 0x1000>, + <0x58241000 0x1000>; + clocks = <&csi1_core_lpcg 0>, + <&csi1_esc_lpcg 0>, + <&csi1_pxl_lpcg 0>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi1_core_lpcg 0>, + <&csi1_esc_lpcg 0>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + parallel_csi: pcsi@58261000 { + compatible = "fsl,mxc-parallel-csi"; + reg = <0x58261000 0x1000>; + clocks = <&pi0_pxl_lpcg 0>, + <&pi0_ipg_lpcg 0>, + <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; + clock-names = "pixel", "ipg", "div", "dpll"; + assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-rates = <160000000>; /* 160MHz */ + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + status = "disabled"; + }; + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + power-domain-names = "pd_isi_ch0", "pd_dec_mp", + "pd_dec_s0", "pd_dec_s1", + "pd_dec_s2", "pd_dec_s3"; + status = "disabled"; + }; + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + power-domain-names = "pd_isi_ch0", "pd_enc_mp", + "pd_enc_s0", "pd_enc_s1", + "pd_enc_s2", "pd_enc_s3"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi new file mode 100644 index 000000000000..4bf058106fec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +lcdif_subsys: bus@5a180000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a180000 0x0 0x5a180000 0x500000>; + + ipg_dma_clk: clock-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "ipg_dma_clk"; + }; + + lcd_clk_lpcg: clock-controller@5a580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a580000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&ipg_dma_clk>; + bit-offset = <0 16>; + clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0>; + }; + + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x5a180000 0x10000>; + clocks = <&lcd_clk_lpcg 0>, + <&lcd_clk_lpcg 1>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + assigned-clock-rates = <0>, <24000000>, <804000000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi new file mode 100644 index 000000000000..ff196f39949c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +lsio_subsys: bus@5d000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, + <0x08000000 0x0 0x08000000 0x10000000>; + + lsio_mem_clk: clock-lsio-mem { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "lsio_mem_clk"; + }; + + lsio_bus_clk: clock-lsio-bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "lsio_bus_clk"; + }; + + lsio_gpio0: gpio@5d080000 { + reg = <0x5d080000 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_0>; + }; + + lsio_gpio1: gpio@5d090000 { + reg = <0x5d090000 0x10000>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_1>; + }; + + lsio_gpio2: gpio@5d0a0000 { + reg = <0x5d0a0000 0x10000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_2>; + }; + + lsio_gpio3: gpio@5d0b0000 { + reg = <0x5d0b0000 0x10000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_3>; + }; + + lsio_gpio4: gpio@5d0c0000 { + reg = <0x5d0c0000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_4>; + }; + + lsio_gpio5: gpio@5d0d0000 { + reg = <0x5d0d0000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_5>; + }; + + lsio_gpio6: gpio@5d0e0000 { + reg = <0x5d0e0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_6>; + }; + + lsio_gpio7: gpio@5d0f0000 { + reg = <0x5d0f0000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_7>; + }; + + flexspi0: spi@5d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd IMX_SC_R_FSPI_0>; + status = "disabled"; + }; + + lsio_mu0: mailbox@5d1b0000 { + reg = <0x5d1b0000 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu1: mailbox@5d1c0000 { + reg = <0x5d1c0000 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + lsio_mu2: mailbox@5d1d0000 { + reg = <0x5d1d0000 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu3: mailbox@5d1e0000 { + reg = <0x5d1e0000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu4: mailbox@5d1f0000 { + reg = <0x5d1f0000 0x10000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu5: mailbox@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x5d200000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + }; + + lsio_mu8: mic_intr@5d230000 { + compatible = "fsl,imx-mic-intr"; + reg = <0x5d230000 0x10000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + /* Also enable MU8B pd since MIC host need touch it's registers */ + power-domains = <&pd IMX_SC_R_MU_8A>, <&pd IMX_SC_R_MU_8B>; + power-domain-names = "pd_a", "pd_b"; + status = "disabled"; + }; + + lsio_mu13: mailbox@5d280000 { + compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; + reg = <0x5d280000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_13A>; + fsl,dsp_ap_mu_id = <13>; + }; + + /* LPCG clocks */ + pwm0_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm0_lpcg_ipg_clk", + "pwm0_lpcg_ipg_hf_clk", + "pwm0_lpcg_ipg_s_clk", + "pwm0_lpcg_ipg_slv_clk", + "pwm0_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_0>; + }; + + pwm1_lpcg: clock-controller@5d410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm1_lpcg_ipg_clk", + "pwm1_lpcg_ipg_hf_clk", + "pwm1_lpcg_ipg_s_clk", + "pwm1_lpcg_ipg_slv_clk", + "pwm1_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_1>; + }; + + pwm2_lpcg: clock-controller@5d420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm2_lpcg_ipg_clk", + "pwm2_lpcg_ipg_hf_clk", + "pwm2_lpcg_ipg_s_clk", + "pwm2_lpcg_ipg_slv_clk", + "pwm2_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_2>; + }; + + pwm3_lpcg: clock-controller@5d430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm3_lpcg_ipg_clk", + "pwm3_lpcg_ipg_hf_clk", + "pwm3_lpcg_ipg_s_clk", + "pwm3_lpcg_ipg_slv_clk", + "pwm3_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_3>; + }; + + pwm4_lpcg: clock-controller@5d440000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d440000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm4_lpcg_ipg_clk", + "pwm4_lpcg_ipg_hf_clk", + "pwm4_lpcg_ipg_s_clk", + "pwm4_lpcg_ipg_slv_clk", + "pwm4_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_4>; + }; + + pwm5_lpcg: clock-controller@5d450000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d450000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm5_lpcg_ipg_clk", + "pwm5_lpcg_ipg_hf_clk", + "pwm5_lpcg_ipg_s_clk", + "pwm5_lpcg_ipg_slv_clk", + "pwm5_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_5>; + }; + + pwm6_lpcg: clock-controller@5d460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm6_lpcg_ipg_clk", + "pwm6_lpcg_ipg_hf_clk", + "pwm6_lpcg_ipg_s_clk", + "pwm6_lpcg_ipg_slv_clk", + "pwm6_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_6>; + }; + + pwm7_lpcg: clock-controller@5d470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5d470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm7_lpcg_ipg_clk", + "pwm7_lpcg_ipg_hf_clk", + "pwm7_lpcg_ipg_s_clk", + "pwm7_lpcg_ipg_slv_clk", + "pwm7_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_7>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi new file mode 100644 index 000000000000..57734ed8a922 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +security_subsys: bus@31400000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x31400000 0x0 0x31400000 0x410000>; + + crypto: crypto@31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0x31400000 0x90000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x31400000 0x90000>; + fsl,sec-era = <9>; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + power-domain-names = "jr"; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + power-domain-names = "jr"; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_CAAM_JR3>; + power-domain-names = "jr"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x31800000 0x10000>; + }; + + sec_mu2: mu@31560000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31560000 0x10000>; + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_2>; + status = "okay"; + }; + + sec_mu3: mu@31570000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31570000 0x10000>; + interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_3>; + status = "okay"; + }; + + sec_mu4: mu@31580000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31580000 0x10000>; + interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_4>; + status = "okay"; + }; +}; + +seco_mu1: seco_mu1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu2 2 0 + &sec_mu2 3 0>; + + fsl,seco_mu_id = <1>; + fsl,seco_max_users = <4>; + status = "okay"; +}; + +seco_mu2: seco_mu2 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu3 2 0 + &sec_mu3 3 0>; + + fsl,seco_mu_id = <2>; + fsl,seco_max_users = <4>; + status = "okay"; +}; + +seco_mu3: seco_mu3 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu4 2 0 + &sec_mu4 3 0>; + + fsl,seco_mu_id = <3>; + fsl,seco_max_users = <4>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi new file mode 100644 index 000000000000..78a6aeb49921 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +v2x_subsys: bus@2C000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x50000>; + + v2x_sv0: mu@2C000000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c000000 0x10000>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_0>; + status = "okay"; + }; + v2x_sv1: mu@2c010000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c010000 0x10000>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_1>; + status = "okay"; + }; + v2x_she: mu@2c020000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c020000 0x10000>; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_2>; + status = "okay"; + }; + v2x_sg0: mu@2c030000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c030000 0x10000>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_3>; + status = "okay"; + }; + v2x_sg1: mu@2c040000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c040000 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_4>; + status = "okay"; + }; +}; + +v2x_mu_sv0: v2x_mu_sv0 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sv0 2 0 + &v2x_sv0 3 0>; + + fsl,seco_mu_id = <4>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x18>; + fsl,rsp_tag = /bits/ 8 <0xe2>; + status = "okay"; +}; +v2x_mu_sv1: v2x_mu_sv1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sv1 2 0 + &v2x_sv1 3 0>; + + fsl,seco_mu_id = <5>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x19>; + fsl,rsp_tag = /bits/ 8 <0xe3>; + status = "okay"; +}; +v2x_mu_she: v2x_mu_she { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_she 2 0 + &v2x_she 3 0>; + + fsl,seco_mu_id = <6>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1a>; + fsl,rsp_tag = /bits/ 8 <0xe4>; + status = "okay"; +}; +v2x_mu_sg0: v2x_mu_sg0 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sg0 2 0 + &v2x_sg0 3 0>; + + fsl,seco_mu_id = <7>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1d>; + fsl,rsp_tag = /bits/ 8 <0xe7>; + status = "okay"; +}; +v2x_mu_sg1: v2x_mu_sg1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sg1 2 0 + &v2x_sg1 3 0>; + + fsl,seco_mu_id = <8>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1e>; + fsl,rsp_tag = /bits/ 8 <0xe8>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100755 index 000000000000..dd7df8174349 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +vpu_subsys: bus@2c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + + vpu_lpcg: clock-controller@2d000000 { + compatible = "fsl,imx8qxp-lpcg-vpu"; + reg = <0x2c000000 0x2000000>; + #clock-cells = <1>; + status = "disabled"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + reg = <0x2c000000 0x1000000>; + reg-names = "vpu_regs"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpudec", "vpu"; + + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qxp-b0-vpuenc"; + reg = <0x2d000000 0x1000000>, /*VPU Encoder*/ + <0x2c000000 0x2000000>; /*VPU*/ + reg-names = "vpu_regs"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpuenc1", "vpu"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + vpu_ts: vpu_ts@2c000000 { + compatible = "nxp,imx8qm-b0-vpu-ts"; + reg = <0x2c000000 0x1000000>; + reg-names = "vpu_ts"; + power-domains = <&pd IMX_SC_R_VPU_TS_0>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vputs", "vpu"; + mbox-names = "ts_tx0", "ts_tx1", "ts_tx2", "ts_tx3", + "ts_rx0", "ts_rx1", "ts_rx2", "ts_rx3"; + mboxes = <&mu3_m0 0 0 + &mu3_m0 0 1 + &mu3_m0 0 2 + &mu3_m0 0 3 + &mu3_m0 1 0 + &mu3_m0 1 1 + &mu3_m0 1 2 + &mu3_m0 1 3>; + status = "disabled"; + }; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + power-domain-names = "vpumu0"; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + power-domain-names = "vpumu1"; + status = "okay"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + power-domain-names = "vpumu2"; + status = "disabled"; + }; + + mu3_m0: mailbox@2d060000 { + compatible = "fsl,imx8-mu3-vpu-m0", "fsl,imx6sx-mu"; + reg = <0x2d060000 0x20000>; + interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <19>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_3>; + power-domain-names = "vpumu3"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts new file mode 100644 index 000000000000..ad663b2706ab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dm.dtsi" +#include "imx8q-val.dtsi" + +/ { + model = "Freescale i.MX8DM Validation Board"; + compatible = "fsl,imx8dm-val", "fsl,imx8dm", "fsl,imx8qm"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&dc1_prg1 { + status = "disabled"; +}; + +&dc1_prg2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dm.dtsi b/arch/arm64/boot/dts/freescale/imx8dm.dtsi new file mode 100644 index 000000000000..23cbfb330acf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dm.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8DM"; + compatible = "fsl, imx8dm", "fsl,imx8qm"; + +}; + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; + /delete-node/ l2-cache0; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts b/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts new file mode 100644 index 000000000000..8fff0b531b09 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dx.dtsi" +#include "imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8DX 17x17 Validation Board"; + compatible = "fsl,imx8dx-17x17-val", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts new file mode 100644 index 000000000000..0556fd01b2a7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dx.dtsi" +#include "imx8x-val.dtsi" + +/ { + model = "Freescale i.MX8DX VALIDATION"; + compatible = "fsl,imx8dx-val", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts new file mode 100644 index 000000000000..7696e3dc78b6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-dsi-rm67191.dts" +#include "imx8x-mek-rpmsg.dtsi" + diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..3157b4720fff --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dx-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&lvds_bridge0 { + status = "disabled"; +}; + +&lvds_bridge1 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsp.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsp.dts new file mode 100644 index 000000000000..953b510f8935 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsp.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8dx-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp-v1"; + reserved-region = <&dsp_reserved>; + reg = <0x596e8000 0x88000>; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&asrc0_lpcg 0>, + <&clk_dummy>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..67e9ba641c8c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8qxp-enet2-tja1100.dtsi" + +&esai0 { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts new file mode 100644 index 000000000000..6dde34436e38 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts new file mode 100644 index 000000000000..511d327845c1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts new file mode 100644 index 000000000000..e81c9510ca82 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts new file mode 100644 index 000000000000..b05ee54a35cc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts new file mode 100644 index 000000000000..88d31032b0bc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts new file mode 100644 index 000000000000..9ad1f1ed3fa1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts new file mode 100644 index 000000000000..631ab37190cf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..4349fc034e68 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts new file mode 100644 index 000000000000..e0271bc7cba9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 +#include "imx8dx-mek-ov5640.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts new file mode 100644 index 000000000000..62fa5eae3acc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8dx-mek.dts" + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts new file mode 100644 index 000000000000..a219f16323bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts new file mode 100644 index 000000000000..807d8cdc9a41 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "imx8dx.dtsi" +#include "imx8x-mek.dtsi" + +/ { + model = "Freescale i.MX8DX MEK"; + compatible = "fsl,imx8dx-mek", "fsl,imx8dx", "fsl,imx8qxp"; + + reserved-memory { +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x98000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&imx8_gpu_ss { + reg = <0x80000000 0x40000000>, <0x0 0x08000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx.dtsi b/arch/arm64/boot/dts/freescale/imx8dx.dtsi new file mode 100644 index 000000000000..05a7f593e717 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" + +&gpu_3d0 { + assigned-clock-rates = <372000000>, <372000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk-rpmsg.dts new file mode 100644 index 000000000000..c6a7d016fbbc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk-rpmsg.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-ddr3-evk.dts" + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&imx8dxl_cm4 { + /* Assume you have partitioned M4, so M4 is not controled by Linux */ + /delete-property/ power-domains; + status = "okay"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&cm40_lpuart { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts new file mode 100644 index 000000000000..10eaffa63148 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts @@ -0,0 +1,957 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model = "Freescale i.MX8DXL DDR3 EVK"; + compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x8000000>; + alloc-ranges = <0 0x98000000 0 0x8000000>; + linux,cma-default; + }; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3480>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960_1>; + asrc-controller = <&asrc0>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_2 11 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_2 11 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-wm8960-2 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-2"; + cpu-dai = <&sai2>; + audio-codec = <&wm8960_2>; + codec-master; + capture-only; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_2 12 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_2 12 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + sound-wm8960-3 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-3"; + cpu-dai = <&sai3>; + audio-codec = <&wm8960_3>; + codec-master; + capture-only; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_2 13 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_2 13 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + sound-wm8960-4 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-4"; + cpu-dai = <&sai0>; + audio-codec = <&wm8960_4>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_2 10 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_2 10 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6416_1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; + + pca9548_1: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + wm8960_1: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + wm8960_2: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + wm8960_3: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + wm8960_4: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9548_2: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-1 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&lsio_gpio4 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + max-cs = <1>; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "disabled"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&sai0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai2 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai2_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai3_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + max-frequency = <100000000>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <10 20 200000>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; + + pinctrl_usbotg1: otg1 { + fsl,pins = < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: otg2 { + fsl,pins = < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + IMX8DXL_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + + IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c + IMX8DXL_USDHC1_WP_CONN_NAND_ALE 0x0e00004c + IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x0600004c + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x0600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x0600004c + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x0600004c + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600004c + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600004c + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060 + IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_adc: adcgrp{ + fsl,pins = < + IMX8DXL_ADC_IN0_ADMA_ADC_IN0 0x06000021 + IMX8DXL_ADC_IN1_ADMA_ADC_IN1 0x06000021 + IMX8DXL_ADC_IN4_ADMA_ADC_IN4 0x06000021 + IMX8DXL_ADC_IN5_ADMA_ADC_IN5 0x06000021 + >; + }; +}; + +&imx8dxl_cm4 { + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts new file mode 100644 index 000000000000..b1de12136d68 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dxl-evk-enet0.dts" + +ðphy1 { + status = "disabled"; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_fec1_rmii>; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + tja110x,refclk_in; + }; + }; +}; + +&iomuxc { + pinctrl_fec1_rmii: fec1rmiigrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000060 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000060 + >; + }; +}; + +&max7322 { + status = "disabled"; +}; + +®_fec1_io { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts new file mode 100644 index 000000000000..394cdc8864e6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk.dts" + +®_fec1_sel { + status = "okay"; +}; + +®_fec1_io { + status = "okay"; +}; + +&eqos { + status = "disabled"; +}; + +&fec1 { + status = "okay"; +}; + +&max7322 { + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-inmate.dts new file mode 100644 index 000000000000..75a546eb0cf3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-inmate.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8dxl.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8DXL EVK"; + compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial4 = &cm40_lpuart; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8dxl-pd { + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8dxl-iomuxc"; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@bf700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbf700000 0x0 0x00100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-cm40.dtsi" +}; + +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&iomuxc { + pinctrl_cm40_lpuart: cm40_lpuartgrp { + fsl,pins = < + IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 + IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&cm40_intmux { + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&cm40_intmux { + status = "okay"; +}; + +&cm40_lpuart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_lpuart>; + status = "okay"; +}; + +/delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts new file mode 100644 index 000000000000..bb745408418f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8dxl-evk.dts" + +/ { + panel { + compatible = "wks,101wx001"; + blctr-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&pca6416_1 3 GPIO_ACTIVE_LOW>, + <&pca6416_1 4 GPIO_ACTIVE_LOW>, + <&pca6416_1 6 GPIO_ACTIVE_LOW>, + <&pca6416_1 7 GPIO_ACTIVE_LOW>, + <&pca6416_1 8 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; +}; + +&sai1 { + status = "disabled"; +}; + +&m2_uart1_sel { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&cm40_lpuart { + status = "disabled"; +}; + +&eqos { + status = "disabled"; +}; + +&wm8960_1 { + status = "disabled"; +}; + +&wm8960_2 { + status = "disabled"; +}; + +&wm8960_3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 0xe8000023 + IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 0xe8000023 + IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 0xe8000023 + IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 0xd0000023 + IMX8DXL_UART1_TX_ADMA_LCDIF_D04 0xe8000023 + IMX8DXL_UART1_RX_ADMA_LCDIF_D05 0xe8000023 + IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 0xe8000023 + IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 0xe8000023 + IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 0xe8000023 + IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 0xe8000023 + IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 0xe8000023 + IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 0xe8000023 + IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 0xe8000023 + IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 0xe8200003 + IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 0xe8200003 + IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 0xe8200003 + IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 0xe8200003 + IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 0xe8200003 + IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC 0xd0000023 + IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET 0xd0000023 + IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN 0xd0000023 + IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC 0xd0000023 + IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK 0xd0000023 + >; + }; +}; + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + assigned-clock-rates = <0>, <24000000>, <711000000>; + + port@0 { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts new file mode 100644 index 000000000000..d5689b172683 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dxl-evk.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts new file mode 100644 index 000000000000..4d7b4ad553ec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk-rpmsg.dts" + +&pcieb { + status = "disabled"; +}; + +&pcieb_ep { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-root.dts new file mode 100644 index 000000000000..a58637225117 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-root.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright NXP 2020 + */ + +#include "imx8dxl-evk.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_M4_0_INTMUX + IMX_SC_R_M4_0_UART + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8DXL_EMMC0_CLK + IMX8DXL_EMMC0_CMD + IMX8DXL_EMMC0_DATA0 + IMX8DXL_EMMC0_DATA1 + IMX8DXL_EMMC0_DATA2 + IMX8DXL_EMMC0_DATA3 + IMX8DXL_EMMC0_DATA4 + IMX8DXL_EMMC0_DATA5 + IMX8DXL_EMMC0_DATA6 + IMX8DXL_EMMC0_DATA7 + IMX8DXL_EMMC0_STROBE + /* cm40_lpuart */ + IMX8DXL_ADC_IN3 + IMX8DXL_ADC_IN2 + >; + }; + }; +}; + +&{/reserved-memory} { + + jh_reserved: jh@bfc00000 { + no-map; + reg = <0x0 0xbfc00000 0x0 0x400000>; + }; + + loader_reserved: loader@bfb00000 { + no-map; + reg = <0x0 0xbfb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@bf900000 { + no-map; + reg = <0x0 0xbf900000 0x0 0x00200000>; + }; + + pci_reserved: pci@bf700000 { + no-map; + reg = <0x0 0xbf700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@a1700000 { + no-map; + reg = <0x0 0xa1700000 0x0 0x1e000000>; + }; +}; + +&usdhc1 { + status = "disabled"; +}; + +&cm40_lpuart { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts new file mode 100644 index 000000000000..93f657e26499 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk.dts" + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&imx8dxl_cm4 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; + status = "okay"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&cm40_lpuart { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts new file mode 100644 index 000000000000..2df401327313 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -0,0 +1,1026 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model = "Freescale i.MX8DXL EVK"; + compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90200000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x98000000 0 0x14000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec1_sel: regfec1_sel { + compatible = "regulator-fixed"; + regulator-name = "fec1_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>; + regulator-always-on; + status = "disabled"; + }; + + reg_fec1_io: regfec1_io { + compatible = "regulator-fixed"; + regulator-name = "fec1_io_supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + status = "disabled"; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3480>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + m2_uart1_sel: fixedregulator@101 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "m2_uart1_sel"; + gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + mux3_en: fixedregulator@102 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "mux3_en"; + gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + pcie_clk_sel_ext: fixedregulator@103 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "clk_ext_sel"; + gpio = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960_1>; + asrc-controller = <&asrc0>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_3 2 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_3 2 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-wm8960-2 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-2"; + cpu-dai = <&sai2>; + audio-codec = <&wm8960_2>; + codec-master; + capture-only; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_3 3 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_3 3 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + sound-wm8960-3 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-3"; + cpu-dai = <&sai3>; + audio-codec = <&wm8960_3>; + codec-master; + capture-only; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&pca6416_3 4 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&pca6416_3 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; +}; + +&adc0 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&imx8dxl_cm4 { + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + status = "disabled"; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + fsl,spi-only-use-cs1-sel; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6416_1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd IMX_SC_R_BOARD_R1>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd IMX_SC_R_BOARD_R2>; + }; + + pca9548_1: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + power-domains = <&pd IMX_SC_R_BOARD_R0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + wm8960_1: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout1_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + wm8960_2: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout1_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + wm8960_3: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout1_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + power-domains = <&pd IMX_SC_R_BOARD_R4>; + }; + + pca9548_2: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + power-domains = <&pd IMX_SC_R_BOARD_R3>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&cm40_lpuart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_lpuart>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&lsio_gpio4 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + ext_osc = <0>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&pcieb_ep{ + compatible = "fsl,imx8qxp-pcie-ep"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + ext_osc = <0>; + status = "disabled"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai2 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai2_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai3_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + max-frequency = <100000000>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <10 20 200000>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&usbphy1 { + status = "okay"; + fsl,tx-d-cal=<114>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; + fsl,tx-d-cal=<111>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; + + pinctrl_usbotg1: otg1 { + fsl,pins = < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: otg2 { + fsl,pins = < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_cm40_lpuart: cm40_lpuartgrp { + fsl,pins = < + IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 + IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts new file mode 100755 index 000000000000..d336ff759b28 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxl-phantom-mek.dtsi" + +/delete-node/ &cm40_i2c; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&cm40_i2c_lpcg { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +®_can0_en { + status = "disabled"; +}; + +®_can0_stby { + status = "disabled"; +}; + +®_can1_en { + status = "disabled"; +}; + +®_can1_stby { + status = "disabled"; +}; + +&cm40_intmux { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts new file mode 100755 index 000000000000..d7702a2a87f8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxl-phantom-mek.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi new file mode 100755 index 000000000000..5a28a7ca7463 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8DXL Phantom MEK"; + compatible = "fsl,imx8dxl-phantom-mek", "fsl,imx8dxl-phantom", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio3 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can0_en: regulator-can0-gen { + compatible = "regulator-fixed"; + regulator-name = "can0-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_en: regulator-can1-gen { + compatible = "regulator-fixed"; + regulator-name = "can1-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can0_en>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can1_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /*gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; removing as i2c bus is changing in new board */ + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <3480>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio3 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_vbus>; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound: sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + asrc-controller = <&asrc0>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&lsio_gpio0 13 0>; + mic-det-gpios = <&lsio_gpio0 13 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; +}; + +&lvds_subsys { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "okay"; +}; + +&acm { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8dxl-phantom-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp { + fsl,pins = < + IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x07800021 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x07800021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC 0x06000040 + IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS 0x06000040 + IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 0x06000040 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + pinctrl_reg_usb_vbus: regusbvbusgrp { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x06000021 + IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x06000021 + >; + }; + + pinctrl_gpio3: gpio3grp{ + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x07800000 + >; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + phy-reset-gpio=<&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <4>; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <114>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&lsio_gpio3 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_gpio3>; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + cpu-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&a35_opp_table { + /delete-node/ opp-900000000; +}; + +&cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + ext_osc = <1>; + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi new file mode 100644 index 000000000000..77b5e35d91ae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &esai0; +/delete-node/ &asrc1; +/delete-node/ &spdif1; +/delete-node/ &amix; +/delete-node/ &adc1; +/delete-node/ &emvsim0; +/delete-node/ &edma1; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; +/delete-node/ &esai0_lpcg; +/delete-node/ &asrc1_lpcg; +/delete-node/ &spdif1_lpcg; +/delete-node/ &amix_lpcg; +/delete-node/ &emvsim0_lpcg; +/delete-node/ &adc1_lpcg; +/delete-node/ &dsp_lpcg; +/delete-node/ &dsp_ram_lpcg; + +&dma_ipg_clk { + clock-frequency = <160000000>; +}; + +&audio_ipg_clk { + clock-frequency = <160000000>; +}; + +&edma0 { + reg = <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59350000 0x10000>, /* gpt0 */ + <0x59360000 0x10000>, /* gpt1 */ + <0x59370000 0x10000>, /* gpt2 */ + <0x59380000 0x10000>; /* gpt3 */ + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ + "edma0-chan21-tx", /* gpt0 */ + "edma0-chan22-tx", /* gpt1 */ + "edma0-chan23-tx", /* gpt2 */ + "edma0-chan24-rx"; /* gpt3 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>, + <&pd IMX_SC_R_DMA_0_CH24>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan21", "edma0-chan22", + "edma0-chan23", "edma0-chan24"; +}; + +&acm { + compatible = "nxp,imx8dxl-acm"; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; +}; + +&edma2 { + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpuart0 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpuart1 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpuart2 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpuart3 { + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; +}; + +&i2c0 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&i2c1 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; +}; + +&i2c2 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; +}; + +&i2c3 { + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpspi3 { + compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; +}; + +&flexcan1 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; +}; + +&flexcan2 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; +}; + +&flexcan3 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; +}; + +&adc0 { + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai0 { + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai1 { + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai2 { + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai3 { + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; +}; + +&spdif0 { + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */ +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi new file mode 100644 index 000000000000..9fd0757b2c3b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/delete-node/ &enet1_lpcg; +/delete-node/ &fec2; +/delete-node/ &mlb; +/delete-node/ &mlb_lpcg; + +&usdhc1 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usdhc2 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usdhc3 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; +}; + +&enet0_lpcg { + clocks = <&conn_enet0_root_clk>, + <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; +}; + +&usbotg1 { + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + /* + * usbotg1 and usbotg2 share one clcok + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; +}; + +&fec1 { + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <125000000>; +}; + +&dma_apbh { + compatible = "fsl,imx28-dma-apbh"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpmi { + compatible = "fsl,imx8qxp-gpmi-nand"; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; +}; + +&conn_subsys { + + usb2_2_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + + bit-offset = <28>; + clocks = <&conn_ipg_clk>; + clock-output-names = "usboh3_2_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_1_PHY>; + }; + + conn_enet0_root_clk: clock-conn-enet0-root { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "conn_enet0_root_clk"; + }; + + eqos_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>; + bit-offset = <0 8 16 20 24>; + clock-output-names = "eqos_ptp", + "eqos_mem_clk", + "eqos_aclk", + "eqos_clk", + "eqos_csr_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; + + eqos: ethernet@5b050000 { + compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x5b050000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&eqos_lpcg 2>, + <&eqos_lpcg 4>, + <&eqos_lpcg 0>, + <&eqos_lpcg 3>, + <&eqos_lpcg 1>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <125000000>; + power-domains = <&pd IMX_SC_R_ENET_1>; + clk_csr = <0>; + status = "disabled"; + }; + + usbphy2: usbphy@0x5b110000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x5b110000 0x1000>; + clocks = <&usb2_2_lpcg 0>; + power-domains = <&pd IMX_SC_R_USB_1_PHY>; + status = "disabled"; + }; + + usbotg2: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb"; + reg = <0x5b0e0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc2 0>; + /* + * usbotg1 and usbotg2 share one clcok + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd IMX_SC_R_USB_1>; + status = "disabled"; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0e0200 0x200>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi new file mode 100644 index 000000000000..b2be8fa51ba8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&ddr_pmu0 { + compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ddr_subsys { + db_ipg_clk: clock-db-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>; + clock-names = "ipg", "cnt"; + power-domains = <&pd IMX_SC_R_PERF>; + }; + + db_pmu0_lpcg: clock-controller@5cae0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5cae0000 0x10000>; + #clock-cells = <1>; + clocks = <&db_ipg_clk>, <&db_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi new file mode 100644 index 000000000000..672c5e233974 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; +}; + +&pcieb { + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 47 4>, + <0 0 0 2 &gic 0 48 4>, + <0 0 0 3 &gic 0 49 4>, + <0 0 0 4 &gic 0 50 4>; +}; + +&pcieb_ep { + compatible = "fsl,imx8qxp-pcie-ep"; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi new file mode 100644 index 000000000000..156bb33e4dc9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +&flexspi0 { + compatible = "nxp,imx8dxl-fspi"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio0 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu0 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu1 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu2 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu3 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu4 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu5 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi new file mode 100644 index 000000000000..c6dfc52ac49c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +&sec_mu2 { + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sec_mu3 { + interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sec_mu4 { + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sec_jr2 { + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sec_jr3 { + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi new file mode 100644 index 000000000000..ceefcfafd388 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8dxl.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &eqos; + gpio0 = &lsio_gpio0; + gpio1 = &lsio_gpio1; + gpio2 = &lsio_gpio2; + gpio3 = &lsio_gpio3; + gpio4 = &lsio_gpio4; + gpio5 = &lsio_gpio5; + gpio6 = &lsio_gpio6; + gpio7 = &lsio_gpio7; + i2c2 = &i2c2; + i2c3 = &i2c3; + mu1 = &lsio_mu1; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &cm40_lpuart; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters with 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + status = "disabled"; + }; + + imx8dxl_cm4: imx8dxl_cm4@0 { + compatible = "fsl,imx8qxp-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + core-index = <0>; + core-id = <IMX_SC_R_M4_0_PID0>; + status = "disabled"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3 + &lsio_mu1 3 3>; + + pd: imx8dxl-pd { + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <160 163 235 236 237 228 229 230 231 238 + 239 240 166 169>; + }; + + clk: clock-controller { + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8dxl-iomuxc"; + }; + + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; + }; + + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; + + watchdog { + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal"; + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 355>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + + /* sorted in register address */ + #include "imx8-ss-v2x.dtsi" + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm40.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-lcdif.dtsi" +}; + +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-hsio.dtsi" +#include "imx8dxl-ss-ddr.dtsi" +#include "imx8dxl-ss-security.dtsi" + +&edma2 { + status = "okay"; +}; + +&cm40_intmux { + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts new file mode 100644 index 000000000000..15b28e151401 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" +#include "imx8x-val.dtsi" + +/ { + model = "Freescale i.MX8DXP VALIDATION"; + compatible = "fsl,imx8dxp-val", "fsl,imx8dxp", "fsl,imx8qxp"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxp.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp.dtsi new file mode 100644 index 000000000000..fba74a31184d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" + +&thermal_zones { + cpu-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts new file mode 100644 index 000000000000..105eae347da3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ab2.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + reg = <0 0x80000000 0 0x0101E400>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + leds { + panel { + status = "disabled"; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = < + IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB + IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB + IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT + >; +}; + +&i2c2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts new file mode 100755 index 000000000000..4897193a954d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts @@ -0,0 +1,973 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + panel { + label = "panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_adc_avdd_5v0: reg-adc-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DAC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_avdd_5v0: reg-dac-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "DAC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_cph_3v3: reg-cph-3v3 { + compatible = "regulator-fixed"; + regulator-name = "CPH_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + reg_cph_1v8: reg-cph-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CPH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_cph_3v3>; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <0>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec>; + }; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5552"; + model = "ak5552-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5552>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "disabled"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + vmmc-supply = <®_sd1_vmmc>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + }; + + ak4458_2: ak4458@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + }; + + ak4458_3: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + status = "disabled"; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_adc_avdd_5v0>; + DVDD-supply = <®_adc_dvdd_3v3>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */ + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch interrupt */ + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr3l-val.dts new file mode 100644 index 000000000000..37432b208554 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr3l-val.dts @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018-2020 NXP + */ + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM DDR3L Validation board"; + compatible = "fsl,imx8mm-ddr3l-val", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "okay"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + }; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gd25q16", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&mu { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts new file mode 100644 index 000000000000..6ff765cb4696 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2-m4.dts" + +/ { + model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0 { + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts new file mode 100644 index 000000000000..1d2991308d8a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + reg = <0 0x80000000 0 0x0101E400>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + leds { + panel { + status = "disabled"; + }; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = < + IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB + IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB + IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT + >; +}; + +&i2c2 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts new file mode 100644 index 000000000000..833c0f0a8cdd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2.dts" + +/ { + model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0 { + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts new file mode 100644 index 000000000000..3e5cec4e1359 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ab2.dts" + +/ { + model = "FSL i.MX8MM DDR4 Audio Board 2.0"; + + leds { + pinctrl-0 = <&pinctrl_gpio_led_2>; + + status { + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + + pinctrl_gpio_led_2: gpioled2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +®_sd1_vmmc { + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts new file mode 100644 index 000000000000..da61f5b76d26 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts new file mode 100644 index 000000000000..2373442639af --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-ddr4-evk-revb.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts new file mode 100644 index 000000000000..d442c9e8918e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK RevB board"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts new file mode 100644 index 000000000000..9df67a9b2667 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-ddr4-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts new file mode 100644 index 000000000000..05038e3a83fc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk-qca-wifi.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; + + leds { + pinctrl-0 = <&pinctrl_gpio_led_2>; + + status { + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + + pinctrl_gpio_led_2: gpioled2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts new file mode 100644 index 000000000000..ec4108c4c217 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 16 GPIO_ACTIVE_LOW>; + linux,code = <KEY_MUTE>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F9>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19 + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; +}; + +&i2c3 { + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; +}; + +&uart3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts new file mode 100644 index 000000000000..a21487449b07 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk-8mic-revE.dts" + +/ { + sound-micfil { + status = "disabled"; + }; + + sound-swpdm { + compatible = "fsl,imx-pdm-mic"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swpdm_mute_irq>; + mute-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + model = "imx-swpdm-audio"; + audio-cpu = <&sai5>; + decimation = <64>; + status = "okay"; + fixed-mclk; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + dmas = <&sdma2 8 7 2>, <&sdma2 9 8 2>; + assigned-clock-rates = <24576000>; + fsl,dataline,dsd = <0 0xf 0xf>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts new file mode 100644 index 000000000000..18aacba546f6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22579200>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts new file mode 100644 index 000000000000..4d3da8e33688 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + + +#include "imx8mm-evk.dts" + +/ { + sound-ak5558 { + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts new file mode 100644 index 000000000000..7e34cd63f83b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mm-evk-ak5558.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts new file mode 100644 index 000000000000..847ce29dbaf2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mm-evk.dts" + +/ { + ext_osc_22m: ext-osc-22m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + clock-output-names = "sclk0"; + }; + + ext_osc_24m: ext-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "sclk1"; + }; + + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-ak4458 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-cpu = <&sai5>; + audio-codec = <&pcm512x>; + format = "i2s"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + bitclock-master = <&pcm512x>; + frame-master = <&pcm512x>; + dac,24db_digital_gain; + dac,led_status; + }; +}; + +&i2c3 { + ak4458_1: ak4458@10 { + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + status = "disabled"; + }; + + ak5558: ak5558@13 { + status = "disabled"; + }; + + ak4497: ak4497@11 { + status = "disabled"; + }; + + pcm512x: pcm512x@4d { + compatible = "ti,pcm5122"; + reg = <0x4d>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + clocks = <&ext_osc_22m>, <&ext_osc_24m>; + clock-names = "sclk0", "sclk1"; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts new file mode 100644 index 000000000000..fe9d96131045 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Freescale i.MX8MM EVK"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips3: bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts new file mode 100644 index 000000000000..170db2331657 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mm-evk.dts" + +/ { + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-ak4458 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-cpu = <&sai5>; + audio-codec = <&pcm512x>; + format = "i2s"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + }; +}; + +&i2c3 { + ak4458_1: ak4458@10 { + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + status = "disabled"; + }; + + ak4497: ak4497@11 { + status = "disabled"; + }; + + pcm512x: pcm512x@4c { + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts new file mode 100644 index 000000000000..3d1398c1280b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mm-evk.dts" + +/ { + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-ak4458 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-cpu = <&sai5>; + audio-codec = <&pcm512x>; + format = "i2s"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + }; +}; + +&i2c3 { + ak4458_1: ak4458@10 { + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + status = "disabled"; + }; + + ak4497: ak4497@11 { + status = "disabled"; + }; + + pcm512x: pcm512x@4c { + compatible = "ti,pcm5142"; + reg = <0x4c>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts new file mode 100644 index 000000000000..2f96420e3230 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts new file mode 100755 index 000000000000..fb6d2a2d706f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM LPDDR4 EVK with QCA WIFI revC board "; +}; + +/delete-node/&pmic_nxp; + +&i2c1 { + pmic_rohm: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts new file mode 100644 index 000000000000..e9f23182dc57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk-qca-wifi.dts" + +/ { + model = "FSL i.MX8MM LPDDR4 EVK with QCA WIFI revB board "; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts new file mode 100644 index 000000000000..d7a2cedf7fc2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts @@ -0,0 +1,35 @@ +#include "imx8mm-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts new file mode 100644 index 000000000000..5a74d7d3a7f8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +&cpu_pd_wait { + /delete-property/ compatible; + /*arm,psci-suspend-param = <0x0>;*/ +}; + +&clk { + init-on-array = <IMX8MM_CLK_USDHC3_ROOT + IMX8MM_CLK_NAND_USDHC_BUS + IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_OCOTP_ROOT>; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&{/reserved-memory} { + + ivshmem_reserved: ivshmem@bbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; +}; + +&uart2 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc3 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts new file mode 100644 index 000000000000..402300b899cc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mq-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "ak4497-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = <IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB + IMX8MM_CLK_USB_BUS + IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB + IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT IMX8MM_CLK_DISP_AXI + IMX8MM_CLK_DISP_APB + >; +}; + +/* + * ATTENTION: M4 may use IPs like below + * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 + */ + +&i2c3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts new file mode 100644 index 000000000000..d6a5cfcf580a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 + >; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index b9f8b7aac8ff..d767cc4490a6 100644..100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -12,6 +12,17 @@ model = "FSL i.MX8MM EVK board"; compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + chosen { stdout-path = &uart2; }; @@ -28,6 +39,34 @@ }; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -36,9 +75,20 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -47,6 +97,30 @@ wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; }; + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -71,12 +145,60 @@ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-ak4497"; + model = "ak4497-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4497>; + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; }; &A53_0 { cpu-supply = <&buck2_reg>; }; +&csi1_bridge { + fsl,mipi-mode; + status = "okay"; + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -92,10 +214,53 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; }; }; }; +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; + ext_osc = <1>; + l1ss-disabled; + status = "okay"; +}; + +&pcie0_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; + ext_osc = <1>; + status = "disabled"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -105,22 +270,118 @@ status = "okay"; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&sai6 { + fsl,sai-monitor-spdif; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; srp-disable; adp-disable; usb-role-switch; + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; status = "okay"; port { @@ -130,6 +391,20 @@ }; }; +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + cap-power-off-card; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -158,115 +433,140 @@ status = "okay"; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; + pmic_nxp: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; - rohm,reset-snvs-powered; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { - buck1_reg: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck1-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck1-dvs-voltage = <850000>, <800000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; + regulator-ramp-delay = <3125>; }; - buck2_reg: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; + regulator-ramp-delay = <3125>; }; - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "BUCK3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; }; - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "BUCK5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "BUCK6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - ldo1_reg: LDO1 { - regulator-name = "LDO1"; + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo2_reg: LDO2 { - regulator-name = "LDO2"; + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1800000>; + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; }; }; @@ -278,6 +578,24 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -308,9 +626,95 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -331,6 +735,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 @@ -357,6 +772,33 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch int */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 @@ -369,6 +811,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 @@ -378,12 +829,87 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -391,6 +917,54 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2_gpio: usdhc2grpgpio { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 @@ -486,4 +1060,61 @@ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@1 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi1_mipi_ep: endpoint@2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&gpu { + status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 7b178a77cc71..ac0de23d850b 100644..100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,9 +4,11 @@ */ #include <dt-bindings/clock/imx8mm-clock.h> +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/imx8mm-dispmix.h> #include <dt-bindings/thermal/thermal.h> #include "imx8mm-pinfunc.h" @@ -38,6 +40,11 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + sai1 = &sai1; + sai2 = &sai2; + sai3 = &sai3; + sai5 = &sai5; + sai6 = &sai6; }; cpus { @@ -69,6 +76,7 @@ nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -81,6 +89,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -93,6 +102,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -105,6 +115,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -146,6 +157,22 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x60000000>; + linux,cma-default; + }; + }; + + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -200,6 +227,110 @@ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; + power-domains { + compatible = "simple-bus"; + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU SS */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "gpumix"; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + }; + + /* VPU SS */ + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "vpumix"; + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; + }; + + /* DISP SS */ + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "dispmix"; + clocks = <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ @@ -210,6 +341,38 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; @@ -226,12 +389,36 @@ clock-names = "main_clk"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>, <&clk IMX8MM_CLK_DRAM_APB>, + <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, + <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>, + <&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>, + <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -242,12 +429,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xff 0xff>; status = "disabled"; }; @@ -255,10 +443,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -269,10 +457,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -282,12 +470,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xf 0xf>; status = "disabled"; }; @@ -295,15 +484,58 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI6_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; dma-names = "rx", "tx"; status = "disabled"; }; + micfil: micfil@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>, + <&clk IMX8MM_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx8mm-spdif"; + reg = <0x30090000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -369,6 +601,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -421,12 +660,12 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon"; + ocotp: efuse@30350000 { + compatible = "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; /* For nvmem subnodes */ @@ -436,6 +675,10 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@640 { + reg = <0x90 6>; + }; }; anatop: anatop@30360000 { @@ -443,6 +686,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -461,6 +720,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "snvs"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; @@ -564,7 +825,21 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; + + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, + <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; ecspi1: spi@30820000 { compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; @@ -642,6 +917,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_AHB>, + <&clk IMX8MM_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; #address-cells = <1>; @@ -694,6 +999,15 @@ status = "disabled"; }; + mu: mu@30aa0000 { + compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; @@ -752,7 +1066,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, @@ -774,6 +1088,11 @@ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; @@ -785,6 +1104,100 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, <500000000>, <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + lcdif-gpr = <&dispmix_gpr>; + resets = <&lcdif_resets>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <12000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + dsi-gpr = <&dispmix_gpr>; + resets = <&mipi_dsi_resets>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + csi1_bridge: csi1_bridge@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x32e20000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&dispmix_pd>; + status = "disabled"; + }; + + mipi_csi_1: mipi_csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi"; + reg = <0x32e30000 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + bus-width = <4>; + power-domains = <&mipi_pd>; + status = "disabled"; + }; + + dispmix_gpr: display-gpr@32e28000 { + compatible = "fsl, imx8mm-iomuxc-gpr", "syscon"; + reg = <0x32e28000 0x100>; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; @@ -795,6 +1208,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&usb_otg1_pd>; status = "disabled"; }; @@ -814,6 +1228,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; + power-domains = <&usb_otg2_pd>; status = "disabled"; }; @@ -823,6 +1238,10 @@ reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx7d-pcie-phy"; + reg = <0x32f00000 0x10000>; + }; }; dma_apbh: dma-controller@33000000 { @@ -854,6 +1273,60 @@ status = "disabled"; }; + pcie0: pcie@33800000 { + compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x400000>, + <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; + + pcie0_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x000400000>, + <0x18000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ @@ -870,4 +1343,169 @@ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; }; + + dispmix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mm-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mm-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mm-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + }; + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>; + }; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; + + vpu_h1: vpu_h1@38320000 { + compatible = "nxp,imx8mm-hantro-h1"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_h1"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro_h1"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>,<&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_h1_pd>; + status = "disabled"; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; + + gpu: gpu@38000000 { + compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, + <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu3d_ahb_clk", + "gpu2d_clk", "gpu2d_axi_clk", + "gpu2d_ahb_clk"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, + <&clk IMX8MM_CLK_GPU2D_SRC>, + <&clk IMX8MM_CLK_GPU_AXI>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <0>,<400000000>,<1000000000>; + + power-domains = <&gpumix_pd>; + + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts new file mode 100644 index 000000000000..541d7f83453a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts @@ -0,0 +1,902 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + panel { + label = "panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_adc_avdd_5v0: reg-adc-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DAC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_avdd_5v0: reg-dac-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "DAC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_cph_3v3: reg-cph-3v3 { + compatible = "regulator-fixed"; + regulator-name = "CPH_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + reg_cph_1v8: reg-cph-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CPH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_cph_3v3>; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5552"; + model = "ak5552-audio"; + audio-cpu = <&sai3>; + audio-codec = <&ak5552>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8mn-ab2 { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_i2c4_gpio: i2c4grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_adc_avdd_5v0>; + DVDD-supply = <®_adc_dvdd_3v3>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts new file mode 100644 index 000000000000..0bac38fff084 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-ddr3l-evk.dts" + +/ { + sound-wm8524 { + asrc-controller = <0>; + }; + sound-ak5558 { + asrc-controller = <&easrc>; + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&ak5558 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts new file mode 100644 index 000000000000..36dd6bd7042e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr3l-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + + /* + * The following three is just a workaround + * to avoid Linux use the memory. + * This board only has 1GB memory, the 0xb8000000 + * exceeds the DRAM, and round back to 0x78000000, + * since we not modify Mcore image, so we need to avoid + * Linux touch 0x78000000 and mark Mcore ddr demo broken. + */ + vdev0vring0@78000000 { + reg = <0 0x78000000 0 0x8000>; + no-map; + }; + + vdev0vring1@78008000 { + reg = <0 0x78008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0x780ff000 0 0x1000>; + no-map; + }; + + vdevbuffer@78400000 { + reg = <0 0x78400000 0 0x100000>; + no-map; + }; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: wm8524{ + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mn-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8524-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + status = "okay"; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts new file mode 100644 index 000000000000..ea786a904028 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +/ { + model = "NXP i.MX8MNano DDR3L EVK board"; +}; + +&aips4 { + /delete-node/ display-subsystem; +}; + +/delete-node/ &adv_bridge; +/delete-node/ &gpu; +/delete-node/ &lcdif; +/delete-node/ &mipi_dsi; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts new file mode 100644 index 000000000000..442d34950e03 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts @@ -0,0 +1,907 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ddr4-ab2", "fsl,imx8mn"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + panel { + label = "panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_adc_avdd_5v0: reg-adc-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DAC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_avdd_5v0: reg-dac-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "DAC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_cph_3v3: reg-cph-3v3 { + compatible = "regulator-fixed"; + regulator-name = "CPH_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + reg_cph_1v8: reg-cph-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CPH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_cph_3v3>; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5552"; + model = "ak5552-audio"; + audio-cpu = <&sai6>; + audio-codec = <&ak5552>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; +}; + +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_i2c4_gpio: i2c4grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0xd6 + MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0xd6 + MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0xd6 + MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + ptn5110_1: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_adc_avdd_5v0>; + DVDD-supply = <®_adc_dvdd_3v3>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; + status= "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "disabled"; +}; + +&sai6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai6>; + assigned-clocks = <&clk IMX8MN_CLK_SAI6>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts new file mode 100644 index 000000000000..4db0e3418e60 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-ddr4-evk.dts" + +/ { + sound-wm8524 { + asrc-controller = <0>; + }; + sound-ak5558 { + asrc-controller = <&easrc>; + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&ak5558 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts new file mode 100644 index 000000000000..96a7616bb3e4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Freescale i.MX8MN EVK"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts new file mode 100644 index 000000000000..46f344ab67bf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-ddr4-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts new file mode 100644 index 000000000000..9e71421e4f4b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/* +TODO: need uncomment when linux ready +&cpu_pd_wait { + /delete-property/ compatible; +}; +*/ + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x93c00000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@0xbbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0xbba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0xbb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@0xbb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@0xb7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@0x93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; + }; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&clk { + init-on-array = <IMX8MN_CLK_NAND_USDHC_BUS + IMX8MN_CLK_USDHC3_ROOT + IMX8MN_CLK_UART4_ROOT>; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts new file mode 100644 index 000000000000..4eb0b1efdba1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + rpmsg_reserved: rpmsg@0xb8200000 { + no-map; + reg = <0 0xb8200000 0 0x200000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mn-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8524-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + status = "okay"; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts new file mode 100644 index 000000000000..846f384dca06 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +&usdhc2 { + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 9ad1d43b8ce7..c2bd4e305b93 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/usb/pd.h> #include "imx8mn.dtsi" / { @@ -15,6 +16,40 @@ stdout-path = &uart2; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -23,8 +58,72 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; enable-active-high; }; + + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + }; + + wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_wlf>; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "mclk"; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + asrc-controller = <&easrc>; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; + }; +}; + +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; }; &A53_0 { @@ -34,6 +133,12 @@ &iomuxc { pinctrl-names = "default"; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -54,6 +159,23 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 @@ -67,12 +189,114 @@ >; }; + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_gpio_wlf: gpiowlfgrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { fsl,pins = < MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -80,6 +304,54 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2_gpio: usdhc2grpgpio { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 @@ -175,6 +447,156 @@ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + ptn5110_1: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; }; &fec1 { @@ -199,6 +621,20 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -230,13 +666,8 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "BUCK3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; }; buck4_reg: BUCK4 { @@ -269,7 +700,7 @@ ldo1_reg: LDO1 { regulator-name = "LDO1"; regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1900000>; regulator-boot-on; regulator-always-on; }; @@ -290,14 +721,6 @@ regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - ldo6_reg: LDO6 { regulator-name = "LDO6"; regulator-min-microvolt = <900000>; @@ -309,16 +732,92 @@ }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + &snvs_pwrkey { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -346,3 +845,98 @@ fsl,ext-reset-output; status = "okay"; }; + +&gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; + status= "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + mipi1_sensor_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&cameradev { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts new file mode 100644 index 000000000000..93e4090dc7c5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 16 GPIO_ACTIVE_LOW>; + linux,code = <KEY_MUTE>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F9>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19 + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; +}; + +&i2c3 { + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; +}; + +&uart3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts new file mode 100644 index 000000000000..d7fcf032c9a2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-evk.dts" + +/ { + sound-wm8524 { + asrc-controller = <0>; + }; + sound-ak5558 { + asrc-controller = <&easrc>; + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&ak5558 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts new file mode 100644 index 000000000000..9fe290032f0f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mn-evk.dts" + +/ { + ext_osc_22m: ext-osc-22m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + clock-output-names = "sclk0"; + }; + + ext_osc_24m: ext-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "sclk1"; + }; + + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-cpu = <&sai5>; + audio-codec = <&pcm512x>; + format = "i2s"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + bitclock-master = <&pcm512x>; + frame-master = <&pcm512x>; + dac,24db_digital_gain; + dac,led_status; + }; +}; + +&i2c3 { + pcm512x: pcm512x@4d { + compatible = "ti,pcm5122"; + reg = <0x4d>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + clocks = <&ext_osc_22m>, <&ext_osc_24m>; + clock-names = "sclk0", "sclk1"; + }; +}; + +&iomuxc { + imx8mn-evk { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts new file mode 100644 index 000000000000..584c1fa19f56 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Freescale i.MX8MN EVK"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts new file mode 100644 index 000000000000..888e49e52699 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mn-evk.dts" + +/ { + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-cpu = <&sai5>; + audio-codec = <&pcm512x>; + format = "i2s"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + }; +}; + +&i2c3 { + pcm512x: pcm512x@4c { + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + }; +}; + +&iomuxc { + imx8mn-evk { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts new file mode 100644 index 000000000000..ba5ec6dbcfd0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mn-evk.dts" + +/ { + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-cpu = <&sai5>; + audio-codec = <&pcm512x>; + format = "i2s"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + }; +}; + +&i2c3 { + pcm512x: pcm512x@4c { + compatible = "ti,pcm5142"; + reg = <0x4c>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + }; +}; + +&iomuxc { + imx8mn-evk { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts new file mode 100644 index 000000000000..5e8d16c93c48 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts new file mode 100644 index 000000000000..76ce08791701 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x93c00000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@0xbbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0xbba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0xbb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@0xbb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@0xb7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@0x93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; + }; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + imx8mn-evk { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + }; +}; + +&clk { + init-on-array = <IMX8MN_CLK_NAND_USDHC_BUS + IMX8MN_CLK_USDHC3_ROOT + IMX8MN_CLK_UART4_ROOT + IMX8MN_CLK_OCOTP_ROOT>; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts new file mode 100644 index 000000000000..a2cdd5479946 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: wm8524{ + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mn-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8524-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + status = "okay"; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts new file mode 100644 index 000000000000..8c736e0fe45c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -0,0 +1,1052 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano EVK board"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + asrc-controller = <&easrc>; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&clk { + assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8mn-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + ptn5110_1: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ov5640: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MN_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&usbotg1 { + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + mipi1_sensor_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&isi_0 { + status = "okay"; + cap_device { + status = "okay"; + }; +}; + +&cameradev { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 546511b373d4..eba30c49c94b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -6,7 +6,9 @@ #include <dt-bindings/clock/imx8mn-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/reset/imx8mn-dispmix.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> #include "imx8mn-pinfunc.h" @@ -37,12 +39,28 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; + isi0 = &isi_0; + csi0 = &mipi_csi_1; }; cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; @@ -54,6 +72,8 @@ operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -65,6 +85,8 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -76,6 +98,8 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -87,6 +111,8 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -128,6 +154,21 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x60000000>; + linux,cma-default; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -170,11 +211,84 @@ clock-output-names = "clk_ext4"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MN_DRAM_PLL_OUT>, <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>, <&clk IMX8MN_CLK_DRAM_APB>, + <&clk IMX8MN_CLK_DRAM_CORE>, <&clk IMX8MN_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>, + <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>, + <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>, + <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIOMIX */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <0>; + #power-domain-cells = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + }; + + usb_otg1_pd: usbotg1-pd{ + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU2D&3D */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <4>; + #power-domain-cells = <0>; + domain-name = "gpumix"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + }; + + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <9>; + #power-domain-cells = <0>; + domain-name = "dispmix"; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <10>; + #power-domain-cells = <0>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, @@ -185,12 +299,49 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -198,6 +349,152 @@ #size-cells = <1>; ranges; + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + + easrc: easrc@300C0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x300C0000 0x10000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; + }; + + sai2: sai@30020000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30020000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI2_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI2_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30030000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30050000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30060000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai7: sai@300b0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x300b0000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI7_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI7_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + micfil: micfil@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_PDM_IPG>, + <&clk IMX8MN_CLK_PDM_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>, + <&clk IMX8MN_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx8mm-spdif"; + reg = <0x30090000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MN_CLK_24M>, /* rxtx0 */ + <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MN_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -263,6 +560,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -288,7 +592,7 @@ }; sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302b0000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, @@ -299,7 +603,7 @@ }; sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, @@ -319,8 +623,8 @@ reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon"; + ocotp: efuse@30350000 { + compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; #address-cells = <1>; @@ -337,6 +641,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -347,6 +667,7 @@ offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; clock-names = "snvs-rtc"; }; @@ -354,6 +675,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; + clock-names = "snvs"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; @@ -428,6 +751,14 @@ #pwm-cells = <2>; status = "disabled"; }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; }; aips3: bus@30800000 { @@ -513,6 +844,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_AHB>, + <&clk IMX8MN_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; #address-cells = <1>; @@ -565,8 +926,17 @@ status = "disabled"; }; + mu: mu@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -582,7 +952,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -596,7 +966,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; reg = <0x30b60000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -611,8 +981,24 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, + <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, @@ -623,7 +1009,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, @@ -645,6 +1031,8 @@ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; @@ -657,18 +1045,80 @@ #size-cells = <1>; ranges; + lcdif: lcd-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, + <500000000>, + <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + resets = <&lcdif_resets>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi_controller@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <266000000>, + <12000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + resets = <&mipi_dsi_resets>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, - <&clk IMX8MN_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, - <&clk IMX8MN_SYS_PLL1_100M>; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&usb_otg1_pd>; status = "disabled"; }; @@ -716,6 +1166,54 @@ interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + + ddr-pmu@3d800000 { + compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; + reg = <0x3d800000 0x400000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpu: gpu@38000000 { + compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <600000000>, <600000000>; + power-domains = <&gpumix_pd>; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; }; usbphynop1: usbphynop1 { @@ -725,4 +1223,178 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; }; + + dispmix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mn-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mn-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mn-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + }; + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; + }; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_DSI_CLKREF_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_DSI_PCLK_RESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MN_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; + }; + }; + + isi_resets: isi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + isi-soft-resetn { + compatible = "isi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_ISI_PROC_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_ISI_APB_CLK_RESET>; + }; + + isi-clk-enable { + compatible = "isi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_ISI_PROC_CLK_EN>, + <&dispmix_clk_en IMX8MN_ISI_APB_CLK_EN>; + }; + + }; + + mipi_csi_resets: mipi-csi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + csi-soft-resetn { + compatible = "csi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_CSI_PCLK_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_CSI_ACLK_RESET>; + }; + + csi-clk-enable { + compatible = "csi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_CSI_PCLK_EN>, + <&dispmix_clk_en IMX8MN_MIPI_CSI_ACLK_EN>; + }; + + csi-mipi-reset { + compatible = "csi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_S_RESET>; + }; + }; + + mipi2csi_gasket: gasket@32e28060 { + compatible = "syscon"; + reg = <0x0 0x32e28060 0x0 0x28>; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + isi_0: isi@0x32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x0 0x32e20000 0x0 0x2000>; + power-domains = <&dispmix_pd>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interface = <2 0 2>; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + resets = <&isi_resets>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_1: csi@32e30000 { + compatible = "fsl,imx8mn-mipi-csi"; + reg = <0x0 0x32e30000 0x0 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + bus-width = <4>; + csi-gpr = <&mipi2csi_gasket>; + power-domains = <&mipi_pd>; + resets = <&mipi_csi_resets>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts new file mode 100755 index 000000000000..c15873c90aa5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -0,0 +1,871 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MP SOM on AB2"; + compatible = "fsl,imx8mp-ab2", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-xcvr"; + model = "imx-audio-xcvr"; + cpu-dai = <&xcvr>; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-ak5552"; + model = "ak5552-audio"; + audio-cpu = <&sai3>; + audio-codec = <&ak5552>; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif3_disp>; + }; +}; + +&{/busfreq} { + status = "disabled"; +}; + +&clk { + init-on-array = <IMX8MP_CLK_HSIO_ROOT>; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak4458_2: ak4458@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak4458_3: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak5552: ak5552@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "okay"; +}; + +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xcvr>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmimix_clk { + status = "okay"; +}; + +&hdmimix_reset { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&aud2htx { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6 + MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6 + MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6 + MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6 + MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6 + MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6 + MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; + + pinctrl_xcvr: xcvrgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0xd6 + MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 + MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts new file mode 100644 index 000000000000..7cb9e49193a6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + model = "NXP i.MX8MPlus DDR4 EVK board"; +}; + +&flexspi { + status = "disabled"; +}; + +&clk { + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, + <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <400000000>, + <600000000>, + <400000000>, + <393216000>, + <361267200>, + <1039500000>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; + nand-on-flash-bbt; +}; + +&gpu_2d { + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>, + <&clk IMX8MP_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <600000000>, + <300000000>, <600000000>; +}; + +&gpu_3d { + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>, + <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>, + <600000000>, <300000000>, + <600000000>; +}; + +&ml_vipsi { + assigned-clocks = <&clk IMX8MP_CLK_ML_SRC>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <300000000>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&vpu_g1 { + + assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, <600000000>, <600000000>; +}; + +&vpu_g2 { + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <500000000>, <600000000>; +}; + +&vpu_vc8000e { + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <400000000>, <600000000>; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x00000096 + MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x00000096 + MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x00000096 + MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x00000096 + MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x00000096 + MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x00000096 + MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x00000096 + MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x00000096 + MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x00000096 + MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x00000096 + MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x00000096 + MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x00000096 + MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x00000096 + MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x00000096 + MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x00000096 + MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x00000056 + MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x00000096 + MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x00000096 + >; + }; +}; + +&lcdif3 { + thres-low = <2 3>; /* (FIFO * 2 / 3) */ + thres-high = <3 3>; /* (FIFO * 3 / 3) */ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts new file mode 100755 index 000000000000..671a40a2a67d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&iomuxc { + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 + >; + }; + + pinctrl_csi1_rst: csi1_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 + >; + }; +}; + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_camera@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&i2c3 { + /delete-node/ov5640_mipi@3c; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_1_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; + +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov2775_mipi_1_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts new file mode 100644 index 000000000000..9460d2c5952b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_camera@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <500000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +&ov5640_1 { + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + csi_id = <1>; + + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "okay"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts new file mode 100644 index 000000000000..133dd1403036 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Basler AG + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <500000000>; + max-data-rate = /bits/ 64 <0>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp-lpa.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp-lpa.dts new file mode 100644 index 000000000000..9f7509cd9b6e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp-lpa.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk-dsp.dts" + +&usdhc2 { + non-removable; +}; + +&i2c3 { + codec: wm8960@1a { + compatible = "wlf,wm8960,lpa"; + reg = <0x1a>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + wlf,shared-lrclk; + SPKVDD1-supply = <®_audio_pwr>; + }; +}; + +/ { + sound-dsp { + compatible = "fsl,imx-dsp-audio-lpa"; + model = "wm8960-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&codec>; + audio-platform = <&dsp>; + }; +}; + +&dsp { + compatible = "fsl,imx8mp-dsp-lpa"; + ocram = <&ocram>; + fsl,dsp-firmware = "imx/dsp/hifi4_imx8mp_lpa.bin"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts new file mode 100644 index 000000000000..b35bdeaf3899 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ +/dts-v1/; + +#include "imx8mp-evk.dts" + +/ { + sound-wm8960 { + status = "disable"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_uart4>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "wm8960-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&codec>; + audio-platform = <&dsp>; + }; +}; + +&sai3 { + status = "disable"; +}; + +&easrc { + status = "disable"; +}; + +&uart4 { + /* console for debug dsp*/ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; +}; + +&dsp { + compatible = "fsl,imx8mp-dsp-v1"; + memory-region = <&dsp_reserved>; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + pinctrl-0 = <&pinctrl_uart4>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI_DIV>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>, + <&clk IMX8MP_CLK_UART4_ROOT>, + <&clk IMX8MP_CLK_UART4_ROOT>; + clock-names = "ocram", "audio_root", "audio_axi", "core", "debug", "mu2", "sdma_root", "sai_ipg", "sai_mclk", + "asrc_ipg", "uart_ipg", "uart_per"; + + power-domains = <&audiomix_pd>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + + audio-interface = "sai"; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, + <&mu2 2 1>, + <&mu2 3 0>, + <&mu2 3 1>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts new file mode 100755 index 000000000000..b86e2eca4950 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_0: basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /delete-node/ov5640_mipi@3c; + + basler_1: basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x01>; + status = "okay"; + + port { + basler_ep_1: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&basler_ep_1>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts new file mode 100644 index 000000000000..5c1f3888ea63 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /delete-node/ov5640_mipi@3c; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_1_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + + port@0 { + endpoint { + remote-endpoint = <&ov2775_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov2775_mipi_1_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts new file mode 100644 index 000000000000..0b778945b334 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +&flexcan2 { + status = "okay";/* can2 pin conflict with pdm */ +}; + +&micfil { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts new file mode 100644 index 000000000000..277ef70f2903 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Freescale i.MX8MP EVK"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + + osc_24m: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 155 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 156 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts new file mode 100644 index 000000000000..69fe4aefd953 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +&lvds_bridge { + split-mode; +}; + +&ldb { + fsl,dual-channel; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts new file mode 100644 index 000000000000..904229c988dd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight>; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; +}; + +/delete-node/ &lvds_bridge; + +&ldb { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + + /delete-node/ port@1; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts new file mode 100644 index 000000000000..46edd382d8b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&iomuxc { + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 + >; + }; + + pinctrl_csi1_rst: csi1_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 + >; + }; +}; + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + /delete-node/ov2775_mipi@36; +}; + +&ov5640_1 { + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; + csi_id = <1>; + + status = "okay"; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "okay"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + endpoint { + remote-endpoint = <&ov2775_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts new file mode 100644 index 000000000000..e241e3646c9a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <500000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov5640_1: ov5640_mipi@3c { + status = "disabled"; + }; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <1>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + endpoint { + remote-endpoint = <&ov2775_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts new file mode 100644 index 000000000000..3ed4f2121e5a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts new file mode 100644 index 000000000000..bf23e8a378f9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts new file mode 100644 index 000000000000..c4fca332f75a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + interrupt-parent = <&gic>; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +&cpu_pd_wait { + /delete-property/ compatible; +}; + +&clk { + init-on-array = <IMX8MP_CLK_USDHC3_ROOT + IMX8MP_CLK_NAND_USDHC_BUS + IMX8MP_CLK_HSIO_ROOT + IMX8MP_CLK_UART4_ROOT + IMX8MP_CLK_OCOTP_ROOT>; +}; + +&{/busfreq} { + status = "disabled"; +}; + +&{/reserved-memory} { + jh_reserved: jh@fdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fda00000 { + no-map; + reg = <0 0xfda00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@fd900000 { + no-map; + reg = <0 0xfd900000 0x0 0x00100000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0 0xfd700000 0x0 0x00200000>; + }; + + inmate_reserved: inmate@c0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3d700000>; + }; +}; + +&iomuxc { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; +}; + +&usdhc3 { + status = "disabled"; +}; + +&uart4 { + /delete-property/ dmas; + /delete-property/ dma-names; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&uart2 { + /* uart4 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts new file mode 100644 index 000000000000..858fc1e2ae8c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +/ { + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c_rpbus_3; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@55008000 { + compatible = "shared-dma-pool"; + reg = <0 0x55008000 0 0x8000>; + no-map; + }; + vdevbuffer: vdevbuffer@55400000 { + compatible = "shared-dma-pool"; + reg = <0 0x55400000 0 0x100000>; + no-map; + }; + + rsc-table { + reg = <0 0x550ff000 0 0x1000>; + no-map; + }; + + audio_reserved: audio@0x81000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x81000000 0 0x10000000>; + }; + }; + + sound-wm8960 { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + power-domains = <&audiomix_pd>; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8960-audio"; + cpu-dai = <&rpmsg_i2s>; + audio-codec = <&codec>; + memory-region = <&audio_reserved>; + rpmsg-out; + audio-routing = + "LINPUT1", "MICB", + "LINPUT3", "MICB"; + }; + + imx8mp-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0x55000000>; + clocks = <&clk IMX8MP_CLK_M7_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + status = "okay"; + }; +}; + +/* + * ATTENTION: M7 may use IPs like below + * ECSPI0/ECSPI2, FLEXCAN, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, + * PWM4, SDMA1/SDMA2 + */ +&ecspi2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +/delete-node/ &i2c3; + +&i2c_rpbus_3 { + compatible = "fsl,i2c-rpbus"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ov5640_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "disabled"; + + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; + + codec: wm8960@1a { + compatible = "wlf,wm8960,lpa"; + reg = <0x1a>; + wlf,shared-lrclk; + SPKVDD1-supply = <®_audio_pwr>; + }; +}; + +&pwm4{ + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0x55000000~0x5500ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0x55000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3{ + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts new file mode 100644 index 000000000000..65c627b407d1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8mp-evk.dts" + +/ { + sound-wm8960 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + simple-audio-card,hp-det-gpio = <&gpio4 0 0>; + simple-audio-card,mic-det-gpio = <&gpio4 0 0>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack", + "Playback", "SAI3.OUT", + "SAI3.IN", "Capture"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 0>; + }; + sndcodec: codec { + sound-dai = <&codec>; + }; + }; + }; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8mp-dsp"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + + power-domains = <&audiomix_pd>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "ocram", "core", "debug", "mu2", "sdma3", + "sai3_bus", "sai3_mclk0", "sai3_mclk1", "sai3_mclk2", "sai3_mclk3"; + + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + + + reg = <0x0 0x3B6E8000 0x0 0x88000>; + tplg-name = "sof-imx8mp-wm8960.tplg"; + + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&codec { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sai3 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts new file mode 100644 index 000000000000..367aa99a1cef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This DTB showcase SPDIF loop back setup on i.MX8MP EVK. + * The signal path used to route SPDIF signal in loopback mode is: + * + * SPDIF_TX -> I2C5_SCL -> I2C5_SCL_3V3 -> J22 pin 3 -> + * J22 pin 5 -> I2C5_SDA_3V3 -> I2C5_SDA -> SPDIF_RX + */ + +#include "imx8mp-evk.dts" + +/ { + /delete-node/ regulator-can1-stby; +}; + +/delete-node/ &flexcan1; + +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xcvr>; + pinctrl-assert-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; +}; + +&iomuxc { + + /delete-node/ flexcan1grp; + /delete-node/ flexcan1reggrp; + + pinctrl_xcvr: xcvrgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 + MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 + >; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts new file mode 100644 index 000000000000..c7e15842933f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -0,0 +1,1344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus EVK board"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0x55800000 { + no-map; + reg = <0 0x55800000 0 0x800000>; + }; + }; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai3>; + audio-codec = <&codec>; + asrc-controller = <&easrc>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <3 0>; + hp-det-gpios = <&gpio4 28 0>; + mic-det-gpios = <&gpio4 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-xcvr"; + model = "imx-audio-xcvr"; + cpu-dai = <&xcvr>; + }; + + lvds_backlight: lvds_backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000>; + status = "okay"; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&clk { + init-on-array = <IMX8MP_CLK_HSIO_ROOT>; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + lvds_bridge: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + + port { + it6263_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio4>; + interrupts = <19 8>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + + ov5640_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ov5640_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "disabled"; + + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + wlf,shared-lrclk; + SPKVDD1-supply = <®_audio_pwr>; + }; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + status = "disabled";/* can2 pin conflict with pdm: gpio low select pdm, gpio high select can2 */ +}; + +&hdmimix_clk { + status = "okay"; +}; + +&hdmimix_reset { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&lcdif1 { + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; + + thres-low = <1 2>; /* (FIFO * 1 / 2) */ + thres-high = <3 4>; /* (FIFO * 3 / 4) */ +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&it6263_in>; + }; + }; + }; +}; + +&ldb_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&pcie{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + l1ss-disabled; + status = "okay"; +}; + +&pcie_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + ext_osc = <1>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + status = "disabled"; +}; + +&pcie_phy{ + ext_osc = <1>; + status = "okay"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usb3_phy0 { + vbus-power-supply = <&ptn5110>; + fsl,phy-tx-vref-tune = <6>; + fsl,phy-tx-rise-tune = <0>; + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-comp-dis-tune = <7>; + fsl,pcs-tx-deemph-3p5db = <0x21>; + fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <2>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_typec_mux: typec1muxgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + >; + }; + + pinctrl_csi_mclk: csi_mclk_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x59 + >; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&dsp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h new file mode 100644 index 000000000000..5f175e09879f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -0,0 +1,799 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2020 NXP + */ + +#ifndef __DTS_IMX8MP_PINFUNC_H +#define __DTS_IMX8MP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__USB1_ID 0x03C 0x29C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__USB2_ID 0x040 0x2A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 +#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x044 0x2A4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x048 0x2A8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x04C 0x2AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OC 0x050 0x2B0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 +#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 +#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 0x058 0x2B8 0x4CC 0x3 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 0x05C 0x2BC 0x4C8 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 0x060 0x2C0 0x4C4 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 0x064 0x2C4 0x4C0 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 +#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK 0x068 0x2C8 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 +#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT 0x06C 0x2CC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK 0x084 0x2E4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN 0x088 0x2E8 0x544 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 +#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 +#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 +#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 +#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 +#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 +#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 +#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 0x0C4 0x324 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 +#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 +#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 +#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 +#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT 0x0D0 0x330 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x0E0 0x340 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 +#define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 +#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 +#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 +#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 +#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 +#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x0F4 0x354 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 +#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 +#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x100 0x360 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 +#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 +#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x104 0x364 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 +#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 +#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x108 0x368 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x110 0x370 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x114 0x374 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 0x118 0x378 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 +#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 +#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x120 0x380 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 +#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x124 0x384 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 +#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 +#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 +#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0x130 0x390 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0x14C 0x3AC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 +#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 +#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK 0x194 0x3F4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 +#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 +#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 +#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 +#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 +#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 +#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 +#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN 0x1B8 0x418 0x544 0x4 0x2 +#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 +#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x1BC 0x41C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 +#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 +#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 +#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 +#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT 0x1D0 0x430 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN 0x1D0 0x430 0x544 0x6 0x3 +#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0x1D4 0x434 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 +#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0x1D8 0x438 0x544 0x0 0x4 +#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 +#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 +#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 +#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 +#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 +#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 +#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 +#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 +#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 +#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 +#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 +#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 +#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 0x1F8 0x458 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 +#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 +#define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 +#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 +#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 +#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 +#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 +#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 +#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 +#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 +#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 +#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 +#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 +#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 +#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 +#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 +#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 +#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 +#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x12 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 +#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 +#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 +#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 +#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 +#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 +#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 +#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 +#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 +#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 +#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 +#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 +#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 +#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 +#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 +#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 +#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 +#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 +#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 +#define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 +#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 +#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 +#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 +#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 +#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 +#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x240 0x4A0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x244 0x4A4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x248 0x4A8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x24C 0x4AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 +#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 + +#endif /* __DTS_IMX8MP_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi new file mode 100644 index 000000000000..29252cf0a655 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -0,0 +1,2467 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2021 NXP + */ + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/reset/imx8mq-reset.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/reset/imx8mp-mediamix.h> +#include <dt-bindings/reset/imx-hdmimix-reset.h> +#include "imx8mp-pinfunc.h" + +/ { + compatible = "fsl,imx8mp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + isi0 = &isi_0; + isi1 = &isi_1; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + isp0 = &isp_0; + isp1 = &isp_1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x8a0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0xa0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x20>, <0x3>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + ddr_pmu0: ddr_pmu@3d800000 { + compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; + reg = <0x0 0x3d800000 0x0 0x400000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + edacmc: memory-controller@3d400000 { + compatible = "fsl,imx8mp-ddrc"; + reg = <0x0 0x3d400000 0x0 0x400000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ocram: ocram@900000 { + no-map; + reg = <0 0x900000 0 0x70000>; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@56000000 { + * reg = <0 0x56000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x40000000 0 0xC0000000>; + linux,cma-default; + }; + + dsp_reserved: dsp@92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + + /* used only by tuning tool, can be removed for normal case */ + isp0_reserved: isp0@94400000 { + no-map; + reg = <0 0x94400000 0 0x10000000>; + }; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>, + <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>, + <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>, + <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>, + <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + active-wakeup; + rpm-always-on; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* MLMIX */ + mlmix_pd: mlmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "mlmix"; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; + + audiomix_pd: audiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "audiomix"; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI_DIV>; + }; + + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "gpumix"; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_CLK_GPU_AXI>; + }; + + gpu2d_pd: gpu2d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "gpu2d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + }; + + gpu3d_pd: gpu3d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "gpu3d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_DIV>; + }; + + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "vpumix"; + clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <11>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <12>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + }; + + mediamix_pd: mediamix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <13>; + domain-name = "mediamix"; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + ispdwp_pd: power-domain@14 { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <14>; + domain-name = "ispdwp"; + parent-domains = <&mediamix_pd>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + }; + + mipi_phy1_pd: mipiphy1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <15>; + domain-name = "mipi_phy1"; + parent-domains = <&mediamix_pd>; + }; + + mipi_phy2_pd: mipiphy2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <16>; + domain-name = "mipi_phy2"; + parent-domains = <&mediamix_pd>; + }; + + hdmimix_pd: hdmimix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <17>; + domain-name = "hdmimix"; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>; + }; + + hdmi_phy_pd: hdmiphy-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <18>; + domain-name = "hdmi_phy"; + parent-domains = <&hdmimix_pd>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <8000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x1>; + trips { + soc_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + + aips1: bus@30000000 { + compatible = "simple-bus"; + reg = <0x30000000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mp-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + #thermal-sensor-cells = <1>; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mp-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: efuse@30350000 { + compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; + /* For nvmem subnodes */ + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + eth_mac1: mac-address@640 { + reg = <0x90 6>; + }; + + eth_mac2: mac-address@650 { + reg = <0x96 6>; + }; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", + "syscon"; + reg = <0x30360000 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "snvs-rtc"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "snvs"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mp-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_NOC_IO>, + <&clk IMX8MP_CLK_GIC>, + <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, + <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, + <800000000>, + <500000000>, + <400000000>, + <800000000>, + <400000000>, + <393216000>, + <361267200>, + <1039500000>; + }; + + src: src@30390000 { + compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + }; + + aips2: bus@30400000 { + compatible = "simple-bus"; + reg = <0x30400000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, + <&clk IMX8MP_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, + <&clk IMX8MP_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, + <&clk IMX8MP_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, + <&clk IMX8MP_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; + }; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 5 0x10 21>; + status = "disabled"; + }; + + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_AHB>, + <&clk IMX8MP_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART4_ROOT>, + <&clk IMX8MP_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + + i2c5: i2c@30ad0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30ad0000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; + status = "disabled"; + }; + + i2c6: i2c@30ae0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30ae0000 0x10000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, + <&clk IMX8MP_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, + <&clk IMX8MP_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, + <&clk IMX8MP_CLK_SIM_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_PHY_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_TIMER>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + intf_mode = <&gpr 0x4>; + status = "disabled"; + }; + }; + + aips5: bus@30c00000 { + compatible = "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c10000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xff 0xff>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c20000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c30000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0x3 0x3>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c50000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c60000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c80000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + easrc: easrc@30c90000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x30c90000 0x10000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + micfil: micfil@30ca0000 { + compatible = "fsl,imx8mp-micfil"; + reg = <0x30ca0000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_ROOT>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + xcvr: xcvr@30cc0000 { + compatible = "fsl,imx8mp-xcvr"; + reg = <0x30cc0000 0x800>, + <0x30cc0800 0x400>, + <0x30cc0c00 0x080>, + <0x30cc0e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR IRQ 1 */ + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR PHY - SPDIF wakeup IRQ */ + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; + dma-names = "rx", "tx"; + resets = <&audiomix_reset 0>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e00000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e10000 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + audiomix: audiomix@30e20000 { + compatible = "fsl,imx8mp-audiomix"; + reg = <0x30e20000 0x10000>; + + audiomix_clk: clock-controller { + compatible = "fsl,imx8mp-audiomix-clk"; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "audio_root"; + power-domains = <&audiomix_pd>; + }; + + audiomix_reset: reset-controller { + compatible = "fsl,imx8mp-audiomix-reset"; + power-domains = <&audiomix_pd>; + #reset-cells = <1>; + }; + + audiomix_dsp: audiomix_dsp { + compatible = "fsl,audiomix-dsp"; + }; + }; + + mu2: mu2@30e60000 { + compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; + reg = <0x30E60000 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + fsl,dsp_ap_mu_id = <2>; + #mbox-cells = <2>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; + status = "okay"; + }; + }; + + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mipi_dsi: mipi_dsi@32e60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <12000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mipi_phy1_pd>; + blk-ctl = <&mediamix_blk_ctl>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + lcdif1: lcd-controller@32e80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif1"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <500000000>, <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + blk-ctl = <&mediamix_blk_ctl>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lcdif1_disp: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + lcdif2: lcd-controller@32e90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif2"; + reg = <0x32e90000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <500000000>, <200000000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lcdif2_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif2_disp_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif2_disp_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch1>; + }; + }; + }; + + mediamix_blk_ctl: blk-ctl@32ec0000 { + compatible = "fsl,imx8mp-mediamix-blk-ctl", + "syscon"; + reg = <0x32ec0000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + ldb: ldb@32ec005c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ldb"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + gpr = <&mediamix_blk_ctl>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch1: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch1>; + }; + }; + }; + }; + + /* TODO for HDMI PHY power on */ + hdmi_blk: hdmi-blk@32fc0000 { + compatible = "syscon"; + reg = <0x32fc0000 0x1000>; + }; + + hdmimix: hdmimix@32fc0000 { + compatible = "fsl,imx8mp-audiomix", "fsl,imx8mp-hdmimix"; + reg = <0x32fc0000 0x1000>; + + hdmimix_clk: clock-controller { + compatible = "fsl,imx8mp-hdmimix-clk"; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_DUMMY>; + clock-names = "dummy"; + status = "disabled"; + }; + + hdmimix_reset: reset-controller { + compatible = "fsl,imx8mp-hdmimix-reset"; + #reset-cells = <1>; + status = "disabled"; + }; + }; + + irqsteer_hdmi: irqsteer@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_IRQS_STEER_CLK>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <200000000>; + resets = <&hdmimix_reset IMX_HDMIMIX_IRQ_STEER_RESET>; + power-domains = <&hdmimix_pd>; + status = "disabled"; + }; + + hdmi_pavi: hdmi-pai-pvi@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pavi"; + reg = <0x32fc4000 0x1000>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_GPA_CLK>; + clock-names = "pvi_clk", "pai_clk"; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PAI_RESET>, + <&hdmimix_reset IMX_HDMIMIX_HDMI_PVI_RESET>; + reset-names = "pai_rst", "pvi_rst"; + status = "disabled"; + }; + + lcdif3: lcd-controller@32fc6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif3"; + reg = <0x32fc6000 0x10000>; + clocks = <&hdmiphy 0>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_B_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_B_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PDI_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_SPU_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_NOC_HDMI_CLK>; + clock-names = "pix", "disp-axi", "disp-apb", + "mix_apb","mix_axi", "xtl_24m", "mix_pix", "lcdif_apb", + "lcdif_axi", "lcdif_pdi", "lcdif_pix", "lcdif_spu", + "noc_hdmi"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + resets = <&hdmimix_reset IMX_HDMIMIX_LCDIF_RESET>; + power-domains = <&hdmimix_pd>; + status = "disabled"; + + lcdif3_disp: port@0 { + reg = <0>; + + lcdif3_to_hdmi: endpoint { + remote-endpoint = <&hdmi_from_lcdif3>; + }; + }; + }; + + hdmi: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PREP_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SKP_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SFR_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_CEC_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_HPI_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL>; + clock-names = "iahb", "isfr", + "phy_int", "prep_clk", "skp_clk", "sfr_clk", "pix_clk", + "cec_clk", "apb_clk", "hpi_clk", "fdcc_ref", "pipe_clk"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <200000000>, <500000000>, <24000000>; + phys = <&hdmiphy>; + phy-names = "hdmi"; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_TX_RESET>; + gpr = <&hdmi_blk>; + power-domains = <&hdmi_phy_pd>; + status = "disabled"; + + port@0 { + hdmi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_hdmi>; + }; + }; + }; + + hdmiphy: hdmiphy@32fdff00 { + compatible = "fsl,samsung-hdmi-phy"; + reg = <0x32fdff00 0x100>; + #clock-cells = <1>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>; + clock-names = "apb", "ref"; + clock-output-names = "hdmi_phy"; + #phy-cells = <0>; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PHY_RESET>; + status = "disabled"; + }; + + mediamix_gasket0: gasket@32ec0060 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0060 0x28>; + }; + + mediamix_gasket1: gasket@32ec0090 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0090 0x28>; + }; + + ldb_phy: phy@32ec0128 { + compatible = "fsl,imx8mp-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; + power-domains = <&mediamix_pd>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + mediamix_gpr: media_gpr@32ec0008 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0008 0x4>; + }; + + isi_chain_buf: isi_chain@32e02000{ + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32e02000 0x4>; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e00000 0x2000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interface = <2 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + no-reset-control; + power-domains = <&mediamix_pd>; + isi_chain = <&isi_chain_buf>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + + m2m_device{ + compatible = "imx-isi-m2m"; + status = "disabled"; + }; + }; + + isi_1: isi@32e02000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e02000 0x2000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interface = <3 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + no-reset-control; + power-domains = <&mediamix_pd>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isp_0: isp@32e10000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e10000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&ispdwp_pd>; + id = <0>; + gpr = <&mediamix_blk_ctl>; + memory-region = <&isp0_reserved>; + status = "disabled"; + }; + + isp_1: isp@32e20000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e20000 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&ispdwp_pd>; + id = <1>; + gpr = <&mediamix_blk_ctl>; + status = "disabled"; + }; + + dewarp: dwe@32e30000 { + compatible = "fsl,imx8mp-dwe"; + reg = <0x32e30000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&ispdwp_pd>; + id = <0>; + status = "disabled"; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e40000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket0>; + gpr = <&mediamix_blk_ctl>; + no-reset-control; + power-domains = <&mipi_phy1_pd>; + status = "disabled"; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e50000 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket1>; + gpr = <&mediamix_blk_ctl>; + no-reset-control; + power-domains = <&mipi_phy2_pd>; + status = "disabled"; + }; + }; + }; + }; + + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_DUMMY>; + clock-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + hsio_mix: hsio-mix@32f10000 { + compatible = "fsl,imx8mp-hsio-mix"; + reg = <0x0 0x32f10000 0x0 0x8>; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0 0x33000000 0 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clk IMX8MP_CLK_NAND_ROOT>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pcie: pcie@33800000 { + compatible = "fsl,imx8mp-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, + <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIEPHY_PERST>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + status = "disabled"; + }; + + pcie_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x0 0x33800000 0x0 0x000400000>, + <0x0 0x18000000 0x0 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIEPHY_PERST>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + + gpu_3d: gpu3d@38000000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_DIV>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>, + <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <1000000000>, + <800000000>, <400000000>; + power-domains = <&gpu3d_pd>; + status = "disabled"; + }; + + gpu_2d: gpu2d@38008000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38008000 0x0 0x8000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&gpu2d_pd>; + status = "disabled"; + }; + + usb3_phy0: usb-phy@381f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0 0x381f0040 0 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_0: usb@32f10100 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10100 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hsiomix_pd>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_0: dwc3@38100000 { + compatible = "snps,dwc3"; + reg = <0 0x38100000 0 0x10000>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_CORE_REF>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u2-freeclk-exists-quirk; + status = "disabled"; + }; + + }; + + usb3_phy1: usb-phy@382f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0 0x382f0040 0 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_1: usb@32f10108 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10108 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hsiomix_pd>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_1: dwc3@38200000 { + compatible = "snps,dwc3"; + reg = <0 0x38200000 0 0x10000>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_CORE_REF>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u2-freeclk-exists-quirk; + status = "disabled"; + }; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <700000000>, <800000000>, <700000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; + + vpu_vc8000e: vpu_vc8000e@38320000 { + compatible = "nxp,imx8mp-hantro-vc8000e"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_vc8000e"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro_vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <800000000>; + power-domains = <&vpu_h1_pd>; + status = "disabled"; + }; + + ml_vipsi: vipsi@38500000 { + compatible = "fsl,imx8-gpu", "fsl,imx8-vipsi"; + reg = <0x0 0x38500000 0x0 0x20000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_ML_SRC>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&mlmix_pd>; + status = "disabled"; + }; + + dsp: dsp@3b6e8000 { + compatible = "fsl,imx8mp-dsp-v1"; + memory-region = <&dsp_reserved>; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; + clock-names = "ocram", "core", "debug", "mu2"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&audiomix_pd>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, + <&mu2 2 1>, + <&mu2 3 0>, + <&mu2 3 1>; + status = "disabled"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif1_disp>, + <&lcdif2_disp>, + <&lcdif3_disp>; + }; + + imx_ion: imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + mix_gpu_ml: mix_gpu_ml { + compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; + reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; + + i2c_rpbus_3: i2c-rpbus-3 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28440000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28540000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28640000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28740000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + + }; + + funnel1: funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x28c03000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c04000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c06000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts new file mode 100644 index 000000000000..d2845266b21f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR3L ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + reg_usdhc2_vmmc: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + >; + }; + + pinctrl_reg_usdhc2: regusdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clock-rates = <0>, <0>, <50000000>, <100000000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts new file mode 100644 index 000000000000..826ba6eb67b5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +#include "imx8mq-ddr4-val.dts" + +&iomuxc { + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts new file mode 100644 index 000000000000..7d23d10796fb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR4 ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + + + reg_usdhc2_vmmc: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + >; + }; + + pinctrl_reg_usdhc2: regusdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts new file mode 100644 index 000000000000..61b4bb0b8af8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts @@ -0,0 +1,93 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd512: sai1grp_dsd512 { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd", "dsd512"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + pinctrl-2 = <&pinctrl_sai1_dsd512>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>; + assigned-clock-rates = <45158400>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0x11>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts new file mode 100644 index 000000000000..3eba0b6bb06e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts new file mode 100644 index 000000000000..d98d6dc34f55 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +/delete-node/ &hdmi; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&adv_bridge { + status = "okay"; + + port@0 { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts new file mode 100644 index 000000000000..bf678498c863 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/delete-node/&hdmi; + +&irqsteer { + status = "okay"; +}; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts new file mode 100644 index 000000000000..c6f73734a8cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8mq-evk-dcss-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c3 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <720>; + touchscreen-size-y = <1440>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts new file mode 100644 index 000000000000..912db5380489 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; + disp-dev = "hdmi_disp"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-dp"; + lane-mapping = <0xc6>; + + status = "okay"; + + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts new file mode 100644 index 000000000000..49aadba32d93 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8mq-evk-lcdif-adv7535.dts" + +/ { + sound-hdmi { + status = "okay"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts new file mode 100644 index 000000000000..2c61c7fd768c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial1 = &uart2; + mmc2 = &usdhc1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_25m: clock-osc-25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc_25m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "400m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bfb00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 54 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbfb00000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart2: serial@30890000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mq-usdhc", + "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart2 { + clocks = <&osc_25m>, + <&osc_25m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc1 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts new file mode 100644 index 000000000000..be0c75892e48 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +&dcss { + status = "disabled"; +}; + +&lcdif { + status = "okay"; + max-memory-bandwidth = <221184000>; /* 1280x720-32@60 */ + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; + + port@0 { + lcdif_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&adv_bridge { + status = "okay"; + + port@0 { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts new file mode 100644 index 000000000000..7c1d7c60b539 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts @@ -0,0 +1,92 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +&lcdif { + status = "okay"; + max-memory-bandwidth = <497829888>; /* 1920x1080-32@60.02 */ + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; + + port@0 { + lcdif_mipi_dsi: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts new file mode 100644 index 000000000000..ef18836e1581 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8mq-evk-lcdif-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts new file mode 100644 index 000000000000..7534041490c7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; +}; + +&pcie1_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts new file mode 100644 index 000000000000..652b32644021 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017-2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie0{ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts new file mode 100644 index 000000000000..0f5d7b73df5e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-pdm { + compatible = "fsl,imx-pdm-mic"; + model = "imx-pdm-audio"; + audio-cpu = <&sai3>; + decimation = <64>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts new file mode 100644 index 000000000000..1b36694ae341 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mq-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +&CPU_SLEEP { + /* We are not using GPC for now, need set 0 to avoid hang */ + arm,psci-suspend-param = <0x0>; +}; + +&clk { + init-on-array = <IMX8MQ_CLK_UART2_ROOT + IMX8MQ_CLK_UART2 + IMX8MQ_CLK_USDHC1_ROOT + IMX8MQ_CLK_NAND_USDHC_BUS + IMX8MQ_CLK_OCOTP_ROOT>; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&resmem { + jh_reserved: jh@fdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + inmate_reserved: inmate@c0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3dc00000>; + }; + + loader_reserved: loader@bff00000 { + no-map; + reg = <0 0xbff00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@bfe00000 { + no-map; + reg = <0 0xbfe00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bfd00000 { + no-map; + reg = <0 0xbfd00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bfc00000 { + no-map; + reg = <0 0xbfb00000 0x0 0x00200000>; + }; +}; + +&uart1 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>, + <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_25M>; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc1 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts new file mode 100644 index 000000000000..68e480b4b3c2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8200000 0 0x200000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + imx8mq-cm4 { + compatible = "fsl,imx8mq-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MQ_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +/* + * Regarding to the HW conflications, the following module should be disabled + * when M4 is running on evk board. + * gpt1, i2c2, pwm4, tmu, uart2 + */ + +&i2c2 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&tmu { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts new file mode 100644 index 000000000000..1bdffc2b9de7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts new file mode 100644 index 000000000000..33d7dc1a047f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + mmc-pwrseq = <&usdhc2_pwrseq>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 05958124f173..3d48c558b43b 100644..100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include <dt-bindings/usb/pd.h> #include "imx8mq.dtsi" / { @@ -21,12 +22,73 @@ reg = <0x00000000 0x40000000 0 0xc0000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; + pcie1_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + ptn36043 { + compatible = "nxp,ptn36043"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ss_sel>; + switch-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -35,6 +97,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -50,12 +113,36 @@ 900000 0x1>; }; + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -71,6 +158,8 @@ cpudai: simple-audio-card,cpu { sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; }; link_codec: simple-audio-card,codec { @@ -78,6 +167,60 @@ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; }; }; + + sound-hdmi { + compatible = "fsl,imx8mq-evk-cdnhdmi", + "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + protocol = <1>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif2>; + spdif-in; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458-mq"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558-mq"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-ak4497-mq"; + model = "ak4497-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4497>; + status = "disabled"; + }; }; &A53_0 { @@ -96,6 +239,30 @@ cpu-supply = <&buck2_reg>; }; +&csi1_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&csi2_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi2_ep: endpoint { + remote-endpoint = <&csi2_mipi_ep>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -111,6 +278,41 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + at803x,eee-disabled; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi1_mipi_ep: endpoint@1 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_csi_2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi2_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi2_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi2_mipi_ep: endpoint@1 { + remote-endpoint = <&csi2_ep>; }; }; }; @@ -118,12 +320,93 @@ &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <0>, <24576000>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "pcm_b2m", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_pcm_b2m>; + pinctrl-2 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_SPDIF1>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_AUDIO_PLL1_OUT>, <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", + "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&spdif2 { + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; status = "okay"; }; + &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_reset>; @@ -141,8 +424,31 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + ov5640_mipi2: ov5640_mipi2@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; + pmic@8 { compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; reg = <0x8>; regulators { @@ -224,6 +530,127 @@ }; }; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <3 8>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "disabled"; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + }; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; }; &pcie0 { @@ -235,46 +662,137 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; + hard-wired = <1>; + vph-supply = <&vgen5_reg>; + l1ss-disabled; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; + vph-supply = <&vgen5_reg>; + l1ss-disabled; status = "okay"; }; +&pcie1_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; + status = "disabled"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + &snvs_pwrkey { status = "okay"; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; status = "okay"; }; -&usb3_phy1 { +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; status = "okay"; }; -&usb_dwc3_1 { - dr_mode = "host"; +&usb3_phy0 { + vbus-power-supply = <&ptn5110>; status = "okay"; }; -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; status = "okay"; - n25q256a: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; }; }; +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -306,6 +824,19 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x16 + >; + }; + pinctrl_buck2: vddarmgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 @@ -313,6 +844,30 @@ }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f + >; + }; + + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + >; + }; + pinctrl_csi2_pwn: csi2_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -340,6 +895,26 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_dsi_ts_int: dsi_ts_int { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 @@ -347,6 +922,14 @@ >; }; + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */ + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + pinctrl_qspi: qspigrp { fsl,pins = < MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 @@ -371,7 +954,97 @@ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_ss_sel: usb3ssgrp{ + fsl,pins = < + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 >; }; @@ -382,6 +1055,16 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 @@ -481,3 +1164,36 @@ >; }; }; + +&vpu { + status = "okay"; +}; + +&gpu3d { + status = "okay"; +}; + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-hdmi"; + lane-mapping = <0xe4>; + status = "okay"; + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h index 68e8fa172974..760321ac5f94 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h @@ -555,12 +555,12 @@ #define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 #define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x12 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 #define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 #define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 3dae8d7c7619..49c544d72173 100644..100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -20,6 +20,9 @@ #size-cells = <2>; aliases { + csi0 = &mipi_csi_1; + csi1 = &mipi_csi_2; + ethernet0 = &fec1; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -29,6 +32,8 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -103,6 +108,7 @@ #cooling-cells = <2>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + cpu-idle-states = <&CPU_SLEEP>; }; A53_1: cpu@1 { @@ -115,6 +121,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_2: cpu@2 { @@ -127,6 +134,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_3: cpu@3 { @@ -139,11 +147,27 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_L2: l2-cache0 { compatible = "cache"; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; a53_opp_table: opp-table { @@ -228,34 +252,6 @@ }; }; }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; }; timer { @@ -268,6 +264,25 @@ arm,no-tick-in-suspend; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, + <&clk IMX8MQ_CLK_DRAM_APB>, <&clk IMX8MQ_CLK_DRAM_APB>, + <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>, + <&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_MAIN_AXI>, + <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m", + "sys1_pll_100m", "sys1_pll_800m", "noc_div", "main_axi_src", + "ahb_div", "osc_25m", "sys2_pll_333m", "sys1_pll_133m"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -275,12 +290,82 @@ ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + bus@30000000 { /* AIPS1 */ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; + sai1: sai@30010000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30010000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 1 0>, <&sdma2 9 1 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0xff 0xff>; + status = "disabled"; + }; + + sai6: sai@30030000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30030000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI6_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + sai5: sai@30040000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30040000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + status = "disabled"; + }; + + sai4: sai@30050000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x30050000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0x0 0xf>; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -396,7 +481,7 @@ 0x00030005 0x00000053 0x00030006 0x0000005f 0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; + #thermal-sensor-cells = <0>; }; wdog1: watchdog@30280000 { @@ -423,7 +508,7 @@ status = "disabled"; }; - sdma2: sdma@302c0000 { + sdma2: dma-controller@302c0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; @@ -434,6 +519,21 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; }; + lcdif: lcdif@30320000 { + compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; + reg = <0x30320000 0x10000>; + clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + clock-names = "pix"; + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x30330000 0x10000>; @@ -451,7 +551,7 @@ }; }; - ocotp: ocotp-ctrl@30350000 { + ocotp: efuse@30350000 { compatible = "fsl,imx8mq-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; @@ -461,6 +561,10 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@640 { + reg = <0x90 6>; + }; }; anatop: syscon@30360000 { @@ -469,6 +573,22 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -487,6 +607,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; + clock-names = "snvs"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; @@ -505,6 +627,19 @@ clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MQ_CLK_NOC>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, + <&clk IMX8MQ_CLK_AUDIO_AHB>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_AUDIO_PLL2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_500M>; + assigned-clock-rates = <800000000>, + <0>, + <0>, + <786432000>, + <722534400>; }; src: reset-controller@30390000 { @@ -519,6 +654,7 @@ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; interrupt-controller; + broken-wake-request-signals; #interrupt-cells = <3>; pgc { @@ -669,6 +805,30 @@ ranges = <0x30800000 0x30800000 0x400000>, <0x08000000 0x08000000 0x10000000>; + spdif1: spdif@30810000 { + compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; + reg = <0x30810000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; @@ -724,6 +884,8 @@ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, <&clk IMX8MQ_CLK_UART3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -735,6 +897,32 @@ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, <&clk IMX8MQ_CLK_UART2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdif2: spdif@308a0000 { + compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; + reg = <0x308a0000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -744,14 +932,30 @@ reg = <0x308b0000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; + sai3: sai@308c0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + crypto: crypto@30900000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; @@ -795,6 +999,47 @@ status = "disabled"; }; + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30a00000 0x300>; + clocks = <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + clock-names = "core", + "rx_esc", + "tx_esc", + "phy_ref", + "video_pll", + "lcdif"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <27000000>, + <266000000>, + <80000000>, + <20000000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pgc_mipi>; + resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, + <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; + reset-names = "byte", "dpi", "esc", "pclk"; + mux-controls = <&mux 0>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a20000 0x10000>; @@ -843,9 +1088,49 @@ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, <&clk IMX8MQ_CLK_UART4_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mipi_csi_1: mipi_csi1@30a70000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x30a70000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, + <&clk IMX8MQ_CLK_CSI1_ESC>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF>, + <&clk IMX8MQ_CLK_CSI1_ESC>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; + power-domains = <&pgc_mipi_csi1>; + csis-phy-reset = <&src 0x4c 7>; + phy-gpr = <&iomuxc_gpr 0x88>; status = "disabled"; }; + csi1_bridge: csi1_bridge@30a90000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x30a90000 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; @@ -878,6 +1163,35 @@ status = "disabled"; }; + mipi_csi_2: mipi_csi2@30b60000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x30b60000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_ESC>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>, + <&clk IMX8MQ_CLK_CSI2_ESC>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; + power-domains = <&pgc_mipi_csi2>; + csis-phy-reset = <&src 0x50 7>; + phy-gpr = <&iomuxc_gpr 0xa4>; + status = "disabled"; + }; + + csi2_bridge: csi2_bridge@30b80000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x30b80000 0x10000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI2_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + qspi0: spi@30bb0000 { #address-cells = <1>; #size-cells = <0>; @@ -892,7 +1206,7 @@ status = "disabled"; }; - sdma1: sdma@30bd0000 { + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -918,6 +1232,11 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&iomuxc_gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; }; @@ -928,6 +1247,14 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + hdmi: hdmi@32c00000 { + reg = <0x32c00000 0x100000>, + <0x32e40000 0x40000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "plug_in", "plug_out"; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; @@ -939,6 +1266,35 @@ interrupt-controller; #interrupt-cells = <1>; }; + + dcss: display-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>, <16>, <17>; + interrupt-names = "ctx_ld", "ctxld_kick", "vblank", + "dtrc_ch1", "dtrc_ch2"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", + "pll_phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + }; }; gpu: gpu@38000000 { @@ -963,6 +1319,7 @@ assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>, <0>; power-domains = <&pgc_gpu>; + status = "disabled"; }; usb_dwc3_0: usb@38100000 { @@ -982,6 +1339,7 @@ phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg1>; usb3-resume-missing-cas; + snps,power-down-scale = <2>; status = "disabled"; }; @@ -1014,6 +1372,7 @@ phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg2>; usb3-resume-missing-cas; + snps,power-down-scale = <2>; status = "disabled"; }; @@ -1029,6 +1388,35 @@ status = "disabled"; }; + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + pcie0: pcie@33800000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33800000 0x400000>, @@ -1042,8 +1430,9 @@ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, @@ -1054,8 +1443,9 @@ power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, <&clk IMX8MQ_CLK_PCIE1_PHY>, <&clk IMX8MQ_CLK_PCIE1_AUX>; @@ -1079,8 +1469,9 @@ 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, @@ -1091,7 +1482,25 @@ power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + status = "disabled"; + }; + + pcie1_ep: pcie_ep@33c00000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, <&clk IMX8MQ_CLK_PCIE2_PHY>, @@ -1101,6 +1510,8 @@ <&clk IMX8MQ_SYS1_PLL_80M>; assigned-clock-rates = <250000000>, <100000000>, <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; status = "disabled"; }; @@ -1123,5 +1534,58 @@ interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; + + vpu: vpu@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x38300000 0x200000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <600000000>, <800000000>; + power-domains = <&pgc_vpu>; + status = "disabled"; + }; + }; + + gpu3d: gpu3d@38000000 { + compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, + <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, + <&clk IMX8MQ_CLK_GPU_AXI>, + <&clk IMX8MQ_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, + <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, + <&clk IMX8MQ_CLK_GPU_AXI>, + <&clk IMX8MQ_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; + power-domains = <&pgc_gpu>; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8q-val.dtsi b/arch/arm64/boot/dts/freescale/imx8q-val.dtsi new file mode 100644 index 000000000000..4e15f7ff1d36 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8q-val.dtsi @@ -0,0 +1,993 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&lsio_gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <3000>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&iomuxc { + imx8qm-val { + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QM_MLB_SIG_CONN_MLB_SIG 0x21 + IMX8QM_MLB_CLK_CONN_MLB_CLK 0x21 + IMX8QM_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; + status = "okay"; +}; + +&gpio0_mipi_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts new file mode 100644 index 000000000000..d11def2e6e91 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts @@ -0,0 +1,886 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM DDR4 VALIDATION"; + compatible = "fsl,imx8qm-val", "fsl,imx8qm"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&lsio_gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_b 3 0>; + enable-active-high; + }; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&iomuxc { + imx8qm-val { + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QM_MLB_SIG_CONN_MLB_SIG 0x21 + IMX8QM_MLB_CLK_CONN_MLB_CLK 0x21 + IMX8QM_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; + +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "disabled"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90100000 0x0 0x10000>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&vpu_decoder { + core_type = <2>; + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi new file mode 100644 index 000000000000..13692cf40709 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* fec1 cannot attach to ethphy0 since the PHY address + * conflict with ethphy2. So eth0 should not work. + * There still enable fec1 to share the MDIO bus for fec2 due + * to board limitation. + */ +&fec1 { + /* PHY address should rework to 3 */ + phy-handle = <ðphy3>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + tja110x,refclk_in; + /delete-property/ at803x,eee-disabled; + /delete-property/ at803x,vddio-1p8v; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + /delete-property/ phy-supply; +}; + +&iomuxc { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT 0x06000020 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER 0x06000020 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts new file mode 100644 index 000000000000..53f8bad38368 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal1; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts new file mode 100644 index 000000000000..e59fd9cddd7d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts new file mode 100644 index 000000000000..c8ab941ed396 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +/* + * DP only dts, disable ldb display. + */ +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai5>; + hdmi-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-dp"; + firmware-name = "dpfw.bin"; + lane-mapping = <0x1b>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts new file mode 100644 index 000000000000..302cc251e3df --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018~2019 NXP + */ + +#include "imx8qm-lpddr4-val-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x600004c + IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x600004c + IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x600004c + IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x600004c + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts new file mode 100644 index 000000000000..da0682d0eaab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qm-lpddr4-val.dts" + +&iomuxc { + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x600004c + IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x600004c + IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x21 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x600004c + IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x600004c + IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x600004c + IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x600004c + >; + }; +}; + +&lpspi0 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts new file mode 100644 index 000000000000..6103a5c0478a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts @@ -0,0 +1,79 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 + IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + status = "disabled"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts new file mode 100644 index 000000000000..ec874258dbb6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + status = "disabled"; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 + IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "disabled"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts new file mode 100755 index 000000000000..2e7db1cf5689 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM LPDDR4 Validation Board"; + compatible = "fsl,imx8qm-lpddr4-val", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart0; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + }; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; + status = "okay"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts new file mode 100644 index 000000000000..b37842fd49b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +&thermal_zones { + /delete-node/ cpu-thermal1; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts new file mode 100644 index 000000000000..357a4ebc4799 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts new file mode 100644 index 000000000000..999424d135cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts @@ -0,0 +1,790 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-xen.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + + stdout-path = &lpuart0; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_MU_2A + IMX_SC_R_GPU_0_PID0 + IMX_SC_R_GPU_0_PID1 + IMX_SC_R_GPU_0_PID2 + IMX_SC_R_GPU_0_PID3 + IMX_SC_R_LVDS_0 + IMX_SC_R_LVDS_0_I2C_0 + IMX_SC_R_LVDS_0_PWM_0 + IMX_SC_R_DC_0 + IMX_SC_R_DC_0_BLIT0 + IMX_SC_R_DC_0_BLIT1 + IMX_SC_R_DC_0_BLIT2 + IMX_SC_R_DC_0_BLIT_OUT + IMX_SC_R_DC_0_WARP + IMX_SC_R_DC_0_VIDEO0 + IMX_SC_R_DC_0_VIDEO1 + IMX_SC_R_DC_0_FRAC0 + IMX_SC_R_DC_0_PLL_0 + IMX_SC_R_DC_0_PLL_1 + IMX_SC_R_SDHC_0 + /*vpu*/ + IMX_SC_R_VPU_PID0 + IMX_SC_R_VPU_PID1 + IMX_SC_R_VPU_PID2 + IMX_SC_R_VPU_PID3 + IMX_SC_R_VPU_PID4 + IMX_SC_R_VPU_PID5 + IMX_SC_R_VPU_PID6 + IMX_SC_R_VPU_PID7 + IMX_SC_R_VPU + IMX_SC_R_VPU_DEC_0 + IMX_SC_R_VPU_ENC_0 + IMX_SC_R_VPU_ENC_1 + IMX_SC_R_VPU_TS_0 + IMX_SC_R_VPU_MU_0 + IMX_SC_R_VPU_MU_1 + IMX_SC_R_VPU_MU_2 + IMX_SC_R_VPU_MU_3 + IMX_SC_R_MU_13A + IMX_SC_R_MU_13B + IMX_SC_R_DSP + IMX_SC_R_DSP_RAM + /* usbotg1 */ + IMX_SC_R_USB_0 + IMX_SC_R_USB_0_PHY + /* usbotg3 */ + IMX_SC_R_USB_2 + IMX_SC_R_USB_2_PHY + + /* ASRC0 */ + IMX_SC_R_DMA_2_CH0 + IMX_SC_R_DMA_2_CH1 + IMX_SC_R_DMA_2_CH2 + IMX_SC_R_DMA_2_CH3 + IMX_SC_R_DMA_2_CH4 + IMX_SC_R_DMA_2_CH5 + IMX_SC_R_DMA_2_CH6 + IMX_SC_R_DMA_2_CH7 + IMX_SC_R_DMA_2_CH8 + IMX_SC_R_DMA_2_CH9 + IMX_SC_R_DMA_2_CH10 + IMX_SC_R_DMA_2_CH11 + IMX_SC_R_DMA_2_CH12 + IMX_SC_R_DMA_2_CH13 + IMX_SC_R_DMA_2_CH14 + IMX_SC_R_DMA_2_CH15 + IMX_SC_R_DMA_2_CH16 + IMX_SC_R_DMA_2_CH17 + IMX_SC_R_DMA_2_CH18 + IMX_SC_R_DMA_2_CH19 + IMX_SC_R_DMA_2_CH20 + IMX_SC_R_AUDIO_CLK_0 + IMX_SC_R_AUDIO_CLK_1 + IMX_SC_R_MCLK_OUT_0 + IMX_SC_R_MCLK_OUT_1 + IMX_SC_R_AUDIO_PLL_0 + IMX_SC_R_AUDIO_PLL_1 + IMX_SC_R_ASRC_0 + IMX_SC_R_ASRC_1 + IMX_SC_R_ESAI_0 + IMX_SC_R_ESAI_1 + IMX_SC_R_SAI_0 + IMX_SC_R_SAI_1 + IMX_SC_R_SAI_2 + IMX_SC_R_SAI_3 + IMX_SC_R_SAI_4 + IMX_SC_R_SAI_5 + IMX_SC_R_SAI_6 + IMX_SC_R_SAI_7 + IMX_SC_R_SPDIF_0 + IMX_SC_R_SPDIF_1 + IMX_SC_R_MQS_0 + IMX_SC_R_DMA_3_CH0 + IMX_SC_R_DMA_3_CH1 + IMX_SC_R_DMA_3_CH2 + IMX_SC_R_DMA_3_CH3 + IMX_SC_R_DMA_3_CH4 + IMX_SC_R_DMA_3_CH5 + IMX_SC_R_DMA_3_CH6 + IMX_SC_R_DMA_3_CH7 + IMX_SC_R_DMA_3_CH8 + IMX_SC_R_DMA_3_CH9 + IMX_SC_R_DMA_3_CH10 + + IMX_SC_R_SATA_0 + IMX_SC_R_PCIE_A + IMX_SC_R_PCIE_B + IMX_SC_R_SERDES_0 + IMX_SC_R_SERDES_1 + IMX_SC_R_HSIO_GPIO + + IMX_SC_R_DMA_0_CH14 + IMX_SC_R_DMA_0_CH15 + IMX_SC_R_UART_1 + + IMX_SC_R_MIPI_0 + IMX_SC_R_MIPI_0_I2C_0 + IMX_SC_R_MIPI_0_I2C_1 + IMX_SC_R_MIPI_1 + IMX_SC_R_MIPI_1_I2C_0 + IMX_SC_R_MIPI_1_I2C_1 + + IMX_SC_R_HDMI_PLL_0 + IMX_SC_R_HDMI_PLL_1 + IMX_SC_R_HDMI + IMX_SC_R_HDMI_I2C_0 + IMX_SC_R_HDMI_I2S + + IMX_SC_R_CSI_0 + IMX_SC_R_CSI_0_I2C_0 + IMX_SC_R_CSI_1 + IMX_SC_R_CSI_1_I2C_0 + IMX_SC_R_ISI_CH0 + IMX_SC_R_ISI_CH1 + IMX_SC_R_ISI_CH2 + IMX_SC_R_ISI_CH3 + IMX_SC_R_ISI_CH4 + IMX_SC_R_ISI_CH5 + IMX_SC_R_ISI_CH6 + IMX_SC_R_ISI_CH7 + IMX_SC_R_MJPEG_DEC_MP + IMX_SC_R_MJPEG_DEC_S0 + IMX_SC_R_MJPEG_DEC_S1 + IMX_SC_R_MJPEG_DEC_S2 + IMX_SC_R_MJPEG_DEC_S3 + IMX_SC_R_MJPEG_ENC_MP + IMX_SC_R_MJPEG_ENC_S0 + IMX_SC_R_MJPEG_ENC_S1 + IMX_SC_R_MJPEG_ENC_S2 + IMX_SC_R_MJPEG_ENC_S3 + >; + pads = < + /* i2c1_lvds1 */ + IMX8QM_LVDS0_I2C1_SCL + IMX8QM_LVDS0_I2C1_SDA + /* emmc */ + IMX8QM_EMMC0_CLK + IMX8QM_EMMC0_CMD + IMX8QM_EMMC0_DATA0 + IMX8QM_EMMC0_DATA1 + IMX8QM_EMMC0_DATA2 + IMX8QM_EMMC0_DATA3 + IMX8QM_EMMC0_DATA4 + IMX8QM_EMMC0_DATA5 + IMX8QM_EMMC0_DATA6 + IMX8QM_EMMC0_DATA7 + IMX8QM_EMMC0_STROBE + IMX8QM_EMMC0_RESET_B + + /* lvds pwm */ + IMX8QM_LVDS0_GPIO00 + + /* usbotg1/3 */ + IMX8QM_USB_SS3_TC0 + IMX8QM_QSPI1A_SS0_B + IMX8QM_USB_SS3_TC3 + IMX8QM_QSPI1A_DATA0 + + /* ESAI0 */ + IMX8QM_ESAI0_FSR + IMX8QM_ESAI0_FST + IMX8QM_ESAI0_SCKR + IMX8QM_ESAI0_SCKT + IMX8QM_ESAI0_TX0 + IMX8QM_ESAI0_TX1 + IMX8QM_ESAI0_TX2_RX3 + IMX8QM_ESAI0_TX3_RX2 + IMX8QM_ESAI0_TX4_RX1 + IMX8QM_ESAI0_TX5_RX0 + /* SAI1 */ + IMX8QM_SAI1_RXD + IMX8QM_SAI1_RXC + IMX8QM_SAI1_RXFS + IMX8QM_SAI1_TXD + IMX8QM_SAI1_TXC + + IMX8QM_PCIE_CTRL0_CLKREQ_B + IMX8QM_PCIE_CTRL0_WAKE_B + IMX8QM_PCIE_CTRL0_PERST_B + IMX8QM_LVDS1_I2C0_SDA + IMX8QM_USDHC2_RESET_B + + IMX8QM_QSPI1A_DQS + IMX8QM_UART1_RX + IMX8QM_UART1_TX + IMX8QM_UART1_CTS_B + IMX8QM_UART1_RTS_B + + IMX8QM_MIPI_CSI0_I2C0_SCL + IMX8QM_MIPI_CSI0_I2C0_SDA + IMX8QM_MIPI_CSI1_I2C0_SCL + IMX8QM_MIPI_CSI1_I2C0_SDA + IMX8QM_MIPI_CSI1_GPIO0_00 + + IMX8QM_MIPI_CSI0_GPIO0_00 + IMX8QM_MIPI_CSI0_GPIO0_01 + IMX8QM_MIPI_CSI0_MCLK_OUT + + IMX8QM_USDHC2_WP + + IMX8QM_MIPI_DSI0_I2C0_SCL + IMX8QM_MIPI_DSI0_I2C0_SDA + IMX8QM_MIPI_DSI0_GPIO0_01 + + IMX8QM_MIPI_DSI1_I2C0_SCL + IMX8QM_MIPI_DSI1_I2C0_SDA + IMX8QM_MIPI_DSI1_GPIO0_01 + + IMX8QM_SCU_GPIO0_07 + + IMX8QM_SPI0_CS1 + IMX8QM_SPI2_CS1 + IMX8QM_SAI1_RXFS + IMX8QM_SAI1_RXC + >; + + gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 19 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 27 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 28 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 30 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 1 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 3 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 6 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 9 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 22 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 25 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 26 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 27 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + }; + }; + + /* Interrupt 33 is not used, use it virtual PL031 */ + rtc0: rtc@23000000 { + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + xen,passthrough; + }; + + gpio4_dummy: gpio4_dummy@0{ + /* Passthrough gpio4 interrupt to DomU */ + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + xen,passthrough; + }; + + gpio1_dummy: gpio1_dummy@0{ + /* Passthrough gpio1 interrupt to DomU */ + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + xen,passthrough; + }; + + reserved-device-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + xen,passthrough; + }; + encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + xen,passthrough; + }; + m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + xen,passthrough; + }; + rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + xen,passthrough; + }; + decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + xen,passthrough; + }; + encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + xen,passthrough; + }; + dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + xen,passthrough; + }; + encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + xen,passthrough; + }; + ts_boot@0x95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + xen,passthrough; + }; + }; +}; + +&{/reserved-memory} { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xa8000000 0 0x58000000>; + linux,cma-default; + }; +}; + +&smmu { + mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, <&usdhc1 0x12>, <&edma0 0x14>, + <&vpu_decoder 0x7>, <&usbotg1 0x11>, <&usbotg3 0x4>, + <&pciea 0x8>, <&edma214 0x10>, <&isi_0 0x5>; +}; + +&edma0 { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; +}; + +&gpu_3d0{ + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d1>; + reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; + status = "okay"; +}; + +&lsio_mu1 { + /* not map for dom0, dom0 will mmio trap to xen */ + xen,no-map; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; + +&dc0_irqsteer { + reg = <0x56000000 0x20000>; + xen,passthrough; +}; + +&dc0_pc { + xen,passthrough; +}; + +&dc0_prg1 { + xen,passthrough; +}; + +&dc0_prg2 { + xen,passthrough; +}; + +&dc0_prg3 { + xen,passthrough; +}; + +&dc0_prg4 { + xen,passthrough; +}; + +&dc0_prg5 { + xen,passthrough; +}; + +&dc0_prg6 { + xen,passthrough; +}; + +&dc0_prg7 { + xen,passthrough; +}; + +&dc0_prg8 { + xen,passthrough; +}; + +&dc0_prg9 { + xen,passthrough; +}; + +&dc0_dpr1_channel1 { + xen,passthrough; +}; + +&dc0_dpr1_channel2 { + xen,passthrough; +}; + +&dc0_dpr1_channel3 { + xen,passthrough; +}; + +&dc0_dpr2_channel1 { + xen,passthrough; +}; + +&dc0_dpr2_channel2 { + xen,passthrough; +}; + +&dc0_dpr2_channel3 { + xen,passthrough; +}; + +&dpu1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&irqsteer_lvds0 { + reg = <0x56240000 0x10000>; + xen,passthrough; +}; + +&lvds0_region { + xen,passthrough; +}; + +&i2c1_lvds0 { + xen,passthrough; +}; + +&ldb1_phy { + xen,passthrough; +}; + +&ldb1 { + xen,passthrough; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&sdhc0_lpcg { + xen,passthrough; +}; + +&lsio_mu2 { + xen,passthrough; +}; + +&lsio_gpio1 { + /* + * Use GPT1 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + xen,domu-irq; + xen,shared; +}; + +/* +&gpt0 { + /delete-property/ interrupts; + status = "disabled"; +}; +*/ + +&lsio_gpio4 { + /* + * Use GPT0 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + xen,domu-irq; + xen,shared; +}; + +&gpio0_mipi_csi0 { + xen,passthrough; +}; + +&gpio0_mipi_csi1 { + xen,passthrough; +}; + +/* vpu_subsys */ +&vpu_lpcg { + xen,passthrough; +}; + +&vpu_decoder { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = <IMX_SC_R_VPU_DEC_0>, + <IMX_SC_R_VPU_TS_0>, + <IMX_SC_R_VPU_PID0>, + <IMX_SC_R_VPU_PID1>, + <IMX_SC_R_VPU_PID2>, + <IMX_SC_R_VPU_PID3>, + <IMX_SC_R_VPU_PID4>, + <IMX_SC_R_VPU_PID5>, + <IMX_SC_R_VPU_PID6>, + <IMX_SC_R_VPU_PID7>; +}; + +&vpu_encoder { + xen,passthrough; +}; + +&vpu_ts { + xen,passthrough; +}; + +&dsp { + xen,passthrough; +}; + +&lsio_mu13 { + xen,passthrough; +}; + +&mu_m0 { + xen,passthrough; +}; + +&mu1_m0 { + xen,passthrough; +}; + +&mu2_m0 { + xen,passthrough; +}; + +&mu3_m0 { + xen,passthrough; +}; + +&vpu_enc_core0 { + xen,passthrough; +}; + +&vpu_enc_core1 { + xen,passthrough; +}; + +&usbotg1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + xen,passthrough; +}; + +&usbphy1 { + xen,passthrough; +}; + +&usb2_lpcg { + xen,passthrough; +}; + +&usbotg3 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usb3phynop1 { + status = "disabled"; +}; + +&usb3_lpcg { + xen,passthrough; +}; + +&ptn5110 { + status = "disabled"; +}; + +&{/cbtl04gp} { + status = "disabled"; +}; + +&audio_subsys { + reg = <0 0x59000000 0 0x1000000>; + xen,passthrough; +}; + +/* Passthrough baseboard audio to DomU */ +&cs42888 { + xen,passthrough; +}; + +®_audio { + xen,passthrough; +}; + +&{/sound-cs42888} { + xen,passthrough; +}; + +&esai0 { + xen,passthrough; +}; + +&wm8960 { + xen,passthrough; +}; + +&hsio_subsys { + xen,passthrough; +}; + +&pciea { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + fsl,sc_rsrc_id = <IMX_SC_R_PCIE_A>; +}; + +&pcieb { + xen,passthrough; +}; + +&epdev_on { + status = "disabled"; +}; + +&lpuart1 { + xen,passthrough; +}; + +&modem_reset { + status = "disabled"; +}; + +&edma214 { + xen,passthrough; + #stream-id-cells = <1>; +}; + +&hdmi_subsys { + xen,passthrough; + reg = <0 0x56260000 0 0x10000>; +}; + +&img_subsys { + xen,passthrough; + reg = <0 0x58000000 0 0x1000000>; +}; + +&mipi0_subsys { + xen,passthrough; + reg = <0 0x56220000 0 0x10000>; +}; + +&mipi1_subsys { + xen,passthrough; + reg = <0 0x57220000 0 0x10000>; +}; + +&isi_0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = <IMX_SC_R_ISI_CH0>, + <IMX_SC_R_ISI_CH1>, + <IMX_SC_R_ISI_CH2>, + <IMX_SC_R_ISI_CH3>, + <IMX_SC_R_ISI_CH4>, + <IMX_SC_R_ISI_CH5>, + <IMX_SC_R_ISI_CH6>, + <IMX_SC_R_ISI_CH7>, + <IMX_SC_R_ISI_CH0>, + <IMX_SC_R_MJPEG_DEC_S0>, + <IMX_SC_R_MJPEG_DEC_S1>, + <IMX_SC_R_MJPEG_DEC_S2>, + <IMX_SC_R_MJPEG_DEC_S3>, + <IMX_SC_R_MJPEG_ENC_S0>, + <IMX_SC_R_MJPEG_ENC_S1>, + <IMX_SC_R_MJPEG_ENC_S2>, + <IMX_SC_R_MJPEG_ENC_S3>; +}; + +&sc_pwrkey { + status = "disabled"; +}; + +&pwm_lvds0 { + status = "disabled"; +}; + +&uart0_lpcg { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts new file mode 100644 index 000000000000..14dbed99bb02 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts @@ -0,0 +1,1452 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/usb/pd.h> + +/* + * At current stage, M41 is not ready to communicate with XEN, so we + * we need a way to tell XEN uboot is running or linux is running. + * XEN will check the contents of this area. + * So reserve a page at the beginning of GUEST_RAM0_BASE to avoid Linux + * touch this area. + */ +/memreserve/ 0x80000000 0x1000; + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + dpu0 = &dpu1; + ldb0 = &ldb1; + serial1 = &lpuart1; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + mu1 = &lsio_mu1; + mu2 = &lsio_mu2; + dphy0 = &mipi0_dphy; + dphy1 = &mipi1_dphy; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + /* + * The reserved memory will be used when using U-Boot loading android + * image. For booting kernel using xl tool, pass args: + * cma=960M@2400M-3584M + * For the rpmsg_reserved area, need xl tool to create for non-android. + */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + passthrough; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + ts_boot: ts_boot@0x95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + linux,phandle = <0xfde8>; + phandle = <0xfde8>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.11", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + clk0: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + rtc0: rtc@23000000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x23000000 0x0 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk0>; + clock-names = "apb_pclk"; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + xen,passthrough; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + }; + + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + }; + + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-audio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-dma.dtsi" + #include "imx8-ss-img.dtsi" + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + xen,passthrough; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + xen,passthrough; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio1 13 0>; + enable-active-high; + xen,passthrough; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + xen,passthrough; + }; + + xen_i2c0: xen_i2c@0 { + compatible = "xen,i2c"; + be-adapter = "5a800000.i2c"; + status = "okay"; + xen,passthrough; + }; + + xen_i2c1: xen_i2c@1 { + compatible = "xen,i2c"; + be-adapter = "3b230000.i2c"; + xen,passthrough; + status = "okay"; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + xen,passthrough; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + vpu_subsys_dsp: bus@55000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x55000000 0x0 0x55000000 0x1000000>; + xen,passthrough; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qm-dsp"; + reg = <0x556e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + memory-region = <&dsp_reserved>; + fixup-offset = <0x4000000>; + status = "disabled"; + }; + }; + +}; + +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-gpu.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-img.dtsi" + +/ { + display-subsystem { + xen,passthrough; + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; +}; + +&lsio_mu13 { + xen,passthrough; +}; + +&dc0_subsys { + xen,passthrough; +}; + +&dma_subsys { + xen,passthrough; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + + edma214: dma-controller@5a2e0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan14", "edma0-chan15"; + status = "okay"; + }; +}; + +&audio_subsys { + xen,passthrough; +}; + +&hsio_subsys { + xen,passthrough; +}; + +&lvds1_subsys { + xen,passthrough; +}; + +&hdmi_subsys { + xen,passthrough; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status="okay"; +}; + +&ldb1 { + status="okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&dc0_pc { + status="okay"; +}; + +&dc0_prg1 { + status="okay"; +}; + +&dc0_prg2 { + status="okay"; +}; + +&dc0_prg3 { + status="okay"; +}; + +&dc0_prg4 { + status="okay"; +}; + +&dc0_prg5 { + status="okay"; +}; + +&dc0_prg6 { + status="okay"; +}; + +&dc0_prg7 { + status="okay"; +}; + +&dc0_prg8 { + status="okay"; +}; + +&dc0_prg9 { + status="okay"; +}; + +&dc0_dpr1_channel1 { + status="okay"; +}; + +&dc0_dpr1_channel2 { + status="okay"; +}; + +&dc0_dpr1_channel3 { + status="okay"; +}; + +&dc0_dpr2_channel1 { + status="okay"; +}; + +&dc0_dpr2_channel2 { + status="okay"; +}; + +&dc0_dpr2_channel3 { + status="okay"; +}; + +&dpu1 { + status="okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&imx8_gpu_ss { + /* xen guests have 2GB of low RAM @ 2GB */ + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + cores = <&gpu_3d0>; + status = "okay"; +}; + +&iomuxc { + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + /delete-property/ iommus; + status = "disabled"; +}; + +&usdhc3 { + /delete-property/ iommus; + status = "disabled"; +}; + +&fec1 { + /delete-property/ iommus; + status = "disabled"; +}; + +&fec2 { + /delete-property/ iommus; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; + /delete-property/ iommus; +}; + +&xen_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&mu_m0{ + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu1_m0{ + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu2_m0{ + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&mu3_m0{ + interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&vpu_decoder { + compatible = "nxp,imx8qm-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d080000>; + core_type = <2>; + status = "okay"; +}; + +&vpu_ts { + compatible = "nxp,imx8qm-b0-vpu-ts"; + boot-region = <&ts_boot>; + reg-csr = <0x2d0b0000>; + status = "okay"; +}; + +&vpu_encoder { + compatible = "nxp,imx8qm-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpuenc1", "vpuenc2", "vpu"; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", + "enc2_tx0", "enc2_tx1", "enc2_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0 + &mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + status = "okay"; + + vpu_enc_core0: core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + + vpu_enc_core1: core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10A0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; + +&lsio_gpio4 { + /delete-property/ power-domains; +}; + +&lsio_gpio1 { + /delete-property/ power-domains; +}; + +/* Audio */ +&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + /*pinctrl-0 = <&pinctrl_sai1>;*/ + status = "disabled"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&xen_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sata { + /delete-property/ iommus; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&pcieb{ + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; + dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; +}; + +&img_subsys { + xen,passthrough; +}; + +&hdmi_subsys { + xen,passthrough; +}; + +&mipi0_subsys { + xen,passthrough; +}; + +&mipi1_subsys { + xen,passthrough; +}; + +&dsi_ipg_clk { + xen,passthrough; +}; + +&mipi_pll_div2_clk { + xen,passthrough; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dp.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dp.dts new file mode 100644 index 000000000000..09a433429243 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dp.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Oliver Brown <oliver.brown@nxp.com> + */ + /* Three displays enabled: DP, LVDS, and MIPI DSI */ + +/dts-v1/; + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai5>; + protocol = <1>; + hdmi-out; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "disabled"; +}; + +&mipi0_dsi_host { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-dp"; + firmware-name = "dpfw.bin"; + lane-mapping = <0x1b>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..32ac9ca1b6a0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dsp.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsp.dts new file mode 100644 index 000000000000..2dd8d4f031da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsp.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan21", + "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + reserved-region = <&dsp_reserved>; + reg = <0x556e8000 0x88000>; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&asrc0_lpcg 0>, + <&asrc0_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + audio-interface = "esai"; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>; + status = "okay"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..61e7c4b644ce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts new file mode 100644 index 000000000000..bd3558911665 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + esai_client0: esai_client@0 { + compatible = "fsl,esai-client"; + fsl,client-id = <0>; + }; + + esai_client1: esai_client@1 { + compatible = "fsl,esai-client"; + fsl,client-id = <1>; + }; +}; + +&esai0 { + client-dais = <&esai_client0>, <&esai_client1>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts new file mode 100644 index 000000000000..fe434e68fdf1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Sandor Yu <Sandor.yu@nxp.com> + */ + /* Three display enabled: HDMI, LVDS, and MIPI DSI */ + +/dts-v1/; + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai5>; + protocol = <1>; + hdmi-out; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "disabled"; +}; + +&mipi0_dsi_host { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-hdmi"; + firmware-name = "hdmitxfw.bin"; + lane-mapping = <0x93>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts new file mode 100644 index 000000000000..47c622dce667 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QM MEK inmate"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&fec1 { + /delete-property/ iommus; +}; + +&fec2 { + /delete-property/ iommus; +}; + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&usbotg3 { + /delete-property/ iommus; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts new file mode 100644 index 000000000000..b57423235fc7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qm-mek-rpmsg.dts" +#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..821f37d50e05 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi new file mode 100644 index 000000000000..68e96d8118aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +/delete-node/ &it6263_1_in; + +&ldb2 { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts new file mode 100644 index 000000000000..e58913258af8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek.dts" + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_6 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_7 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&mipi_csi_1 { + /delete-property/virtual-channel; + + /* Camera 1 MIPI CSI-2 (CSIS0) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; + +&i2c_mipi_csi1 { + ov5640_mipi_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts new file mode 100644 index 000000000000..f1324bbe72fe --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek-rpmsg.dts" + +&pciea{ + status = "disabled"; +}; + +&pcieb{ + status = "disabled"; +}; + +&lsio_mu8{ + doorbell-reg = <0x5d2c0000 0x10000>; + status = "okay"; +}; + +&pciea_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + ext_osc = <1>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts new file mode 100644 index 000000000000..55cb2af806e8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm-mek.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_UART_2 + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8QM_EMMC0_CLK + IMX8QM_EMMC0_CMD + IMX8QM_EMMC0_DATA0 + IMX8QM_EMMC0_DATA1 + IMX8QM_EMMC0_DATA2 + IMX8QM_EMMC0_DATA3 + IMX8QM_EMMC0_DATA4 + IMX8QM_EMMC0_DATA5 + IMX8QM_EMMC0_DATA6 + IMX8QM_EMMC0_DATA7 + IMX8QM_EMMC0_STROBE + IMX8QM_EMMC0_RESET_B + /* lpuart2 */ + IMX8QM_UART0_RTS_B + IMX8QM_UART0_CTS_B + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@0xfdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@0xfdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xfd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@0xfd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@0xdf7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&smmu { + /* Jailhouse hypervisor will initialize SMMU and use it. */ + status = "disabled"; +}; + +&usdhc1 { + /* Let U-Boot program SID */ + iommus = <&smmu 0x10 0x7f80>; + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts new file mode 100644 index 000000000000..5639b0a84770 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek.dts" + +/delete-node/ &cm41_i2c; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&cm41_i2c_lpcg { + status = "disabled"; +}; + +®_can01_en { + status = "disabled"; +}; + +®_can2_en { + status = "disabled"; +}; + +®_can01_stby { + status = "disabled"; +}; + +®_can2_stby { + status = "disabled"; +}; + +&cm41_intmux { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +&can1_lpcg { + status = "disabled"; +}; + +&can2_lpcg { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&lpuart2 { + status = "disabled"; +}; + +&uart2_lpcg { + status = "disabled"; +}; + +&imx8qm_cm40 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; + +&imx8qm_cm41 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts new file mode 100644 index 000000000000..06dec161f50d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-audio-cs42888 { + compatible = "simple-audio-card"; + label = "imx-cs42888"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack", + "Playback", "ESAI0.OUT"; + status = "okay"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 0>; + }; + codec { + sound-dai = <&cs42888>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + + power-domains = <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, + <&clk_dummy>; + clock-names = "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + tplg-name = "sof-imx8qxp-cs42888.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts new file mode 100644 index 000000000000..9fa20ad9cc96 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio1 0 0>; + mic-det-gpio = <&lsio_gpio1 0 0>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack", + "Playback", "SAI1.OUT", + "SAI1.IN", "Capture"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + + clock-names = "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; + clocks = <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + + tplg-name = "sof-imx8qxp-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&cs42888 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts new file mode 100644 index 000000000000..4d688997d97a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ +#include "imx8qm-mek-rpmsg.dts" + +&pinctrl_usdhc2 { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000021 + >; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&lsio_gpio4 8 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + /delete-property/ wp-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts new file mode 100644 index 000000000000..a44dd8a2501e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ +#include "imx8qm-mek-rpmsg.dts" + +/ { + reg_usdhc3_vmmc: usdhc3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + power-domains = <&pd IMX_SC_R_BOARD_R3>; + }; +}; + +&epdev_on { + regulator-always-on; +}; + +&iomuxc { + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + >; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + pinctrl-assert-gpios = <&lsio_gpio4 10 GPIO_ACTIVE_HIGH>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + vmmc-supply = <®_usdhc3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-vop.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-vop.dts new file mode 100644 index 000000000000..f33a27a81332 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-vop.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +&resmem { + fsl,imx_mic { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2000000>; + alloc-ranges = <0 0xf8000000 0 0x2000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts new file mode 100755 index 000000000000..a82c860a0e6c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -0,0 +1,1888 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpu_reserved: gpu_reserved@0x8800000000 { + no-map; + reg = <0x8 0x80000000 0 0x10000000>; + }; + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + ts_boot: ts_boot@0x95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio1 13 0>; + enable-active-high; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; + enable-active-high; + }; + + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + imx8qm_cm40: imx8qm_cm4@0 { + compatible = "fsl,imx8qm-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + core-index = <0>; + core-id = <IMX_SC_R_M4_0_PID0>; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + imx8qm_cm41: imx8x_cm4@1 { + compatible = "fsl,imx8qm-cm4"; + rsc-da = <0x90100000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu6 0 1 + &lsio_mu6 1 1 + &lsio_mu6 3 1>; + mub-partition = <4>; + memory-region = <&vdev2vring0>, <&vdev2vring1>, <&vdevbuffer>, + <&vdev3vring0>, <&vdev3vring1>; + core-index = <1>; + core-id = <IMX_SC_R_M4_1_PID0>; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_1_PID0>, + <&pd IMX_SC_R_M4_1_MU_1A>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc-table@0 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + vdev2vring0: vdev0vring0@90100000 { + compatible = "shared-dma-pool"; + reg = <0 0x90100000 0 0x8000>; + no-map; + }; + + vdev2vring1: vdev0vring1@90108000 { + compatible = "shared-dma-pool"; + reg = <0 0x90108000 0 0x8000>; + no-map; + }; + + vdev3vring0: vdev1vring0@90110000 { + compatible = "shared-dma-pool"; + reg = <0 0x90110000 0 0x8000>; + no-map; + }; + + vdev3vring1: vdev1vring1@90118000 { + compatible = "shared-dma-pool"; + reg = <0 0x90118000 0 0x8000>; + no-map; + }; + + rsc-table@1 { + reg = <0 0x901ff000 0 0x1000>; + no-map; + }; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm41_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&cm41_intmux { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds1>; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&emvsim0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim0>; + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart2 { /* Dbg console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "disabled"; +}; + +&lpuart3 { /* MKbus */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "okay"; +}; + +&rpmsg0{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sata>; + clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + >; + }; + + pinctrl_cm41_i2c: cm41i2cgrp { + fsl,pins = < + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c + IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + >; + }; + + pinctrl_lpspi2_cs: lpspi2cs { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + + pinctrl_sim0: sim0grp { + fsl,pins = < + IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 + IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 + IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 + IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 + IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_lvds1: pwmlvds1grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_sata: satagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c + IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c + IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c + IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; + +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + memory-region=<&gpu_reserved>; + status = "okay"; +}; + +&mu_m0{ + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu1_m0{ + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu2_m0{ + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&mu3_m0{ + interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&vpu_decoder { + compatible = "nxp,imx8qm-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d080000>; + core_type = <2>; + status = "okay"; +}; + +&vpu_ts { + compatible = "nxp,imx8qm-b0-vpu-ts"; + boot-region = <&ts_boot>; + reg-csr = <0x2d0b0000>; + status = "okay"; +}; + +&vpu_encoder { + compatible = "nxp,imx8qm-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, + <&pd IMX_SC_R_VPU>; + power-domain-names = "vpuenc1", "vpuenc2", "vpu"; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", + "enc2_tx0", "enc2_tx1", "enc2_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0 + &mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + status = "okay"; + + vpu_enc_core0: core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + + vpu_enc_core1: core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10A0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts new file mode 100644 index 000000000000..22738c54673a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = <PCIEAX2PCIEBX1> + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = <PCIEAX1PCIEBX1SATA> would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + num-lanes = <2>; + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per","pcie_per", "misc_per"; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx2_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_per", "pcie_phy", + "pcie_serdes", "hsio_gpio"; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi new file mode 100644 index 000000000000..708f21910053 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +/delete-node/ &acm; +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + reg = <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59260000 0x10000>, /* esai0 rx */ + <0x59270000 0x10000>, /* esai0 tx */ + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592A0000 0x10000>, /* spdif1 rx */ + <0x592B0000 0x10000>, /* spdif1 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59320000 0x10000>, /* sai4 rx */ + <0x59330000 0x10000>; /* sai5 tx */ + dma-channels = <20>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */ + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */ + "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan16-rx", "edma2-chan17-tx", /* sai2, dai3 */ + "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH16>, + <&pd IMX_SC_R_DMA_2_CH17>, + <&pd IMX_SC_R_DMA_2_CH18>, + <&pd IMX_SC_R_DMA_2_CH19>; + power-domain-names = "edma2-chan0", "edma2-chan1", + "edma2-chan2", "edma2-chan3", + "edma2-chan4", "edma2-chan5", + "edma2-chan6", "edma2-chan7", + "edma2-chan8", "edma2-chan9", + "edma2-chan10", "edma2-chan11", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan16", "edma2-chan17", + "edma2-chan18", "edma2-chan19"; +}; + +/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ +&edma1{ + reg = <0x59A00000 0x10000>, /* asrc1 */ + <0x59A10000 0x10000>, + <0x59A20000 0x10000>, + <0x59A30000 0x10000>, + <0x59A40000 0x10000>, + <0x59A50000 0x10000>, + <0x59A80000 0x10000>, /* sai6 rx */ + <0x59A90000 0x10000>, /* sai6 tx */ + <0x59AA0000 0x10000>; /* sai7 tx */ + dma-channels = <9>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */ + interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */ + "edma3-chan2-rx", "edma3-chan3-tx", + "edma3-chan4-tx", "edma3-chan5-tx", + "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */ + "edma3-chan10-tx"; /* sai7 */ + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH8>, + <&pd IMX_SC_R_DMA_3_CH9>, + <&pd IMX_SC_R_DMA_3_CH10>; + power-domain-names = "edma3-chan0", "edma3-chan1", + "edma3-chan2", "edma3-chan3", + "edma3-chan4", "edma3-chan5", + "edma3-chan8", "edma3-chan9", + "edma3-chan10"; +}; + +&asrc0 { + clocks = <&asrc0_lpcg 0>, + <&asrc0_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_0>; +}; + +&esai0 { + power-domains = <&pd IMX_SC_R_ESAI_0>; +}; + +&spdif0 { + power-domains = <&pd IMX_SC_R_SPDIF_0>; +}; + +&spdif1 { + power-domains = <&pd IMX_SC_R_SPDIF_1>; +}; + +&sai0 { + power-domains = <&pd IMX_SC_R_SAI_0>; +}; + +&sai1 { + power-domains = <&pd IMX_SC_R_SAI_1>; +}; + +&sai2 { + power-domains = <&pd IMX_SC_R_SAI_2>; +}; + +&sai3 { + power-domains = <&pd IMX_SC_R_SAI_3>; +}; + +&asrc1 { + clocks = <&asrc1_lpcg 0>, + <&asrc1_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_1>; +}; + +&amix { + dais = <&sai6>, <&sai7>; +}; + +&asrc0_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <0 8>; + clock-output-names = "asrc0_lpcg_ipg_clk", + "asrc0_lpcg_mem_clk"; +}; + +&esai0_lpcg { + bit-offset = <16 0>; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; +}; + +&spdif0_lpcg { + bit-offset = <20 16>; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; +}; + +&spdif1_lpcg { + bit-offset = <20 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; +}; + +&sai0_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; +}; + +&sai1_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; +}; + +&sai2_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; +}; + +&sai3_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; +}; + +&asrc1_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <0 8>; + clock-output-names = "asrc1_lpcg_ipg_clk", + "asrc1_lpcg_mem_clk"; +}; + +&mqs0_lpcg { + bit-offset = <16 0>; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; +}; + +&dsp_lpcg { + status = "disabled"; +}; + +&dsp_ram_lpcg { + status = "disabled"; +}; + +&audio_subsys { + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x59e00000 0x1D0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_ESAI_1>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SAI_6>, + <&pd IMX_SC_R_SAI_7>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_MQS_0>; + }; + + sai4: sai@59080000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59080000 0x10000>; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai4_lpcg 1>, + <&clk_dummy>, + <&sai4_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 18 0 1>; + fsl,dataline = <0 0xf 0x0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59090000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59090000 0x10000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai5_lpcg 1>, + <&clk_dummy>, + <&sai5_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma0 19 0 0>; + fsl,dataline = <0 0x0 0xf>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1: esai@59810000 { + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; + reg = <0x59810000 0x10000>; + interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&esai1_lpcg 1>, + <&esai1_lpcg 0>, + <&esai1_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + status = "disabled"; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai6_lpcg 1>, + <&clk_dummy>, + <&sai6_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_6>; + status = "disabled"; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai7_lpcg 1>, + <&clk_dummy>, + <&sai7_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_7>; + status = "disabled"; + }; + + sai4_lpcg: clock-controller@59480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59480000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5_lpcg: clock-controller@59490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59490000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1_lpcg: clock-controller@59c10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c10000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "esai1_lpcg_extal_clk", + "esai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + }; + + sai6_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai6_lpcg_mclk", + "sai6_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_6>; + }; + + sai7_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai7_lpcg_mclk", + "sai7_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_7>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi new file mode 100644 index 000000000000..1f875642ec2a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&conn_subsys { + usbh1: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x5b0e0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "hsic"; + dr_mode = "host"; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd IMX_SC_R_USB_1>; + status = "disabled"; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0e0200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&usb2_lpcg 1>; + clock-names = "main_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "disabled"; + }; +}; + +&fec1 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; +}; + +&fec2 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; +}; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; + iommus = <&smmu 0x11 0x7f80>; +}; + +&usdhc2 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; + iommus = <&smmu 0x11 0x7f80>; +}; + +&usdhc3 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; + iommus = <&smmu 0x11 0x7f80>; +}; + +&usbotg3 { + iommus = <&smmu 0x4 0x7f80>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi new file mode 100644 index 000000000000..e0c93f2aeddc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +&dpu1 { + compatible = "fsl,imx8qm-dpu"; + + dpu1_disp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dpu1_disp0_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_disp>; + }; + + dpu1_disp0_mipi0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi0_dsi_in>; + }; + }; + + dpu1_disp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dpu1_disp1_ldb1_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu1_disp1_ldb1_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + }; +}; + +&dpu2 { + compatible = "fsl,imx8qm-dpu"; + + dpu2_disp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dpu2_disp0_mipi1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_dsi_in>; + }; + + }; + + dpu2_disp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dpu2_disp1_ldb2_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu2_disp1_ldb2_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + }; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>, + <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi new file mode 100644 index 000000000000..e47b12a76556 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&ddr_subsys { + ddr_pmu1: ddr-pmu@5c120000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&ddr_pmu0 { + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi new file mode 100644 index 000000000000..c4edc739cbe5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&dma_subsys { + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + reg = <0x5a0a0000 0x1000>; + interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_4>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 21 0 0>, + <&edma2 20 0 1>; + status = "disabled"; + }; + + uart4_lpcg: clock-controller@5a4a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a4a0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart4_lpcg_baud_clk", + "uart4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_4>; + }; + + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a840000 0x4000>; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&i2c4_lpcg 0>, + <&i2c4_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_4>; + status = "disabled"; + }; + + i2c4_lpcg: clock-controller@5ac40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac40000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c4_lpcg_clk", + "i2c4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_4>; + }; + + can1_lpcg: clock-controller@5ace0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ace0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can1_lpcg_pe_clk", + "can1_lpcg_ipg_clk", + "can1_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_1>; + }; + + can2_lpcg: clock-controller@5acf0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acf0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can2_lpcg_pe_clk", + "can2_lpcg_ipg_clk", + "can2_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_2>; + }; +}; + +&flexcan1 { + fsl,clk-source = <1>; +}; + +&flexcan2 { + clocks = <&can1_lpcg 1>, + <&can1_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; + fsl,clk-source = <1>; +}; + +&flexcan3 { + clocks = <&can2_lpcg 1>, + <&can2_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; + fsl,clk-source = <1>; +}; + +&lpspi2 { + compatible = "fsl,imx8qm-lpspi", "fsl,imx7ulp-spi"; +}; + +/* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ +&edma2 { + reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ + <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ + <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ + <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ + <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>, /* channel15 UART1 tx */ + <0x5a300000 0x10000>, /* channel16 UART2 rx */ + <0x5a310000 0x10000>, /* channel17 UART2 tx */ + <0x5a320000 0x10000>, /* channel18 UART3 rx */ + <0x5a330000 0x10000>, /* channel19 UART3 tx */ + <0x5a340000 0x10000>, /* channel20 UART4 rx */ + <0x5a350000 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <18>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-rx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan6", "edma0-chan7", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan18", "edma0-chan19", + "edma0-chan20", "edma0-chan21"; + status = "okay"; +}; + +&lpuart0 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart1 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; +}; + +&lpuart2 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 17 0 0>, + <&edma2 16 0 1>; +}; + +&lpuart3 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 19 0 0>, + <&edma2 18 0 1>; +}; + +&i2c0 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c2 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c3 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi new file mode 100644 index 000000000000..90b670b15276 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&gpu_3d0 { + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = <IMX_SC_R_GPU_0_PID0>; +}; + +&gpu1_subsys { + imx8_gpu_ss: imx8_gpu1_ss { + compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>, <&gpu_3d1>; + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + depth-compression = <0>; + /*<freq-kHz vol-uV>*/ + operating-points = < + /*overdrive*/ 800000 0 /*The first tuple is for core clock frequency*/ + 1000000 0 /*The second tuple is for shader clock frequency*/ + /*nominal*/ 650000 0 + 700000 0 + /*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi new file mode 100644 index 000000000000..049416cb629a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Sandor Yu <Sandor.yu@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +/ { + hdmi_subsys: bus@56260000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56260000 0x0 0x56260000 0x10000>; + + irqsteer_hdmi: irqsteer@56260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56260000 0x1000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&hdmi_lpcg_lis_ipg 0>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + assigned-clock-rates = <800000000>, <84375000>; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_i2c0: clock-controller@56263000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0 16>; + clock-output-names = "hdmi_lpcg_i2c0_clk", + "hdmi_lpcg_i2c0_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; + status = "disabled"; + }; + + hdmi_lpcg_lis_ipg: clock-controller@56263004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263004 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_lis_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_pwm_ipg: clock-controller@56263008 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263008 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_pwm_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_i2s: clock-controller@5626300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5626300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_i2s_clk"; + power-domains = <&pd IMX_SC_R_HDMI_I2S>; + status = "disabled"; + }; + + hdmi_lpcg_gpio_ipg: clock-controller@56263010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_gpio_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_msi_hclk: clock-controller@56263014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_msi_hclk_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_pxl: clock-controller@56263018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_phy: clock-controller@5626301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5626301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0 16>; + clock-output-names = "hdmi_lpcg_phy_vif_clk", + "hdmi_lpcg_phy_pclk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb_mux_csr: clock-controller@56263020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263020 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_lpcg_apb 0>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_mux_csr_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb_mux_ctrl: clock-controller@56263024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263024 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_lpcg_apb 0>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_mux_ctrl_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb: clock-controller@56263028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263028 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + i2c0_hdmi: i2c@56266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x56266000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&hdmi_lpcg_i2c0 0>, + <&hdmi_lpcg_i2c0 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; + status = "disabled"; + }; + + hdmi:hdmi@56268000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56268000 0x1000>, + <0x56261000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <10>, <13>; + interrupt-names = "plug_in", "plug_out"; + status = "disabled"; + + clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>, + <&hdmi_lpcg_phy 1>, + <&hdmi_lpcg_msi_hclk 0>, + <&hdmi_lpcg_pxl 0>, + <&hdmi_lpcg_phy 0>, + <&hdmi_lpcg_lis_ipg 0>, + <&hdmi_lpcg_apb 0>, + <&hdmi_lpcg_apb_mux_csr 0>, + <&hdmi_lpcg_apb_mux_ctrl 0>, + <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_BYPASS>, + <&hdmi_lpcg_i2s 0>; + clock-names = "dig_pll", "av_pll", "clk_ipg", + "clk_core", "clk_pxl", "clk_pxl_mux", + "clk_pxl_link", "lpcg_hdp", "lpcg_msi", + "lpcg_pxl", "lpcg_vif", "lpcg_lis", + "lpcg_apb", "lpcg_apb_csr", "lpcg_apb_ctrl", + "clk_i2s_bypass", "lpcg_i2s"; + assigned-clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>; + assigned-clock-parents = <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>; + power-domains = <&pd IMX_SC_R_HDMI>, + <&pd IMX_SC_R_HDMI_PLL_0>, + <&pd IMX_SC_R_HDMI_PLL_1>; + power-domain-names = "hdmi", "pll0", "pll1"; + + port@0 { + reg = <0>; + hdmi_disp: endpoint { + remote-endpoint = <&dpu1_disp0_hdmi>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi new file mode 100644 index 000000000000..09fde1445c45 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Richard Zhu <hongxing.zhu@nxp.com> + */ + +&hsio_subsys { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + pciea_lpcg: clock-controller@5f050000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f050000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + bit-offset = <16 20 24>; + clock-output-names = "hsio_pciea_mstr_axi_clk", + "hsio_pciea_slv_axi_clk", + "hsio_pciea_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_lpcg: clock-controller@5f070000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f070000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>; + bit-offset = <16>; + clock-output-names = "hsio_sata_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + phyx2_lpcg: clock-controller@5f080000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f080000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_refa_clk>, <&hsio_per_clk>; + bit-offset = <0 4 16 20>; + clock-output-names = "hsio_phyx2_pclk_0", + "hsio_phyx2_pclk_1", + "hsio_phyx2_apbclk_0", + "hsio_phyx2_apbclk_1"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + phyx2_crr0_lpcg: clock-controller@5f0a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0a0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_phyx2_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + pciea_crr2_lpcg: clock-controller@5f0c0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0c0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_pciea_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_crr4_lpcg: clock-controller@5f0e0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0e0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_sata_per_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + pciea: pcie@0x5f000000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f000000 0x10000>, /* Controller reg */ + <0x6ff00000 0x80000>, /* PCI cfg space */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "dbi", "config", "hsio"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x6ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60000000 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 73 4>, + <0 0 0 2 &gic 0 74 4>, + <0 0 0 3 &gic 0 75 4>, + <0 0 0 4 &gic 0 76 4>; + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + local-addr = <0x40000000>; + status = "disabled"; + }; + + pciea_ep: pcie_ep@0x5f000000 { + compatible = "fsl,imx8qm-pcie-ep"; + reg = <0x5f000000 0x00010000>, + <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */ + <0x60000000 0x10000000>; + reg-names = "regs", "hsio", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + local-addr = <0x40000000>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f010000 0x10000>, /* Controller reg */ + <0x7ff00000 0x80000>, /* PCI cfg space */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "dbi", "config", "hsio"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx2_lpcg 1>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_per", "pcie_phy", + "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + local-addr = <0x80000000>; + status = "disabled"; + }; + + sata: sata@5f020000 { + compatible = "fsl,imx8qm-ahci"; + reg = <0x5f020000 0x10000>, /* Controller reg */ + <0x5f1a0000 0x10000>, /* PHY reg */ + <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ + reg-names = "ctl", "phy", "hsio"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sata_lpcg 0>, + <&phyx1_lpcg 0>, + <&phyx1_lpcg 1>, + <&phyx1_lpcg 2>, + <&phyx2_crr0_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&sata_crr4_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&phyx2_lpcg 0>, + <&phyx2_lpcg 1>, + <&phyx1_lpcg 3>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "per_clk0", "per_clk1", "per_clk2", + "per_clk3", "per_clk4", "per_clk5", + "phy_pclk0", "phy_pclk1", "phy_apbclk"; + power-domains = <&pd IMX_SC_R_SATA_0>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + fsl,sc_rsrc_id = <IMX_SC_R_SATA_0>; + iommus = <&smmu 0x13 0x7f80>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi new file mode 100644 index 000000000000..a1baeeac02fe --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&pi0_pxl_lpcg { + status = "disabled"; +}; + +&pi0_ipg_lpcg { + status = "disabled"; +}; + +&pi0_misc_lpcg { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi new file mode 100644 index 000000000000..d5875e7aa65b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ +&lsio_subsys { + lsio_mu6: mailbox@5d210000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d210000 0x10000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_6A>; + }; +}; + +&lsio_gpio0 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_mu0 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu1 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu2 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu3 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu4 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi new file mode 100644 index 000000000000..03786f8e0f5d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds1_subsys: bus@56240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56240000 0x0 0x56240000 0x10000>; + + lvds0_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds0_ipg_clk"; + }; + + lvds0_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds0_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_pwm_lpcg_clk", + "lvds0_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + }; + + lvds0_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c0_lpcg_clk", + "lvds0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + lvds0_i2c1_lpcg: clock-controller@56243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c1_lpcg_clk", + "lvds0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + irqsteer_lvds0: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_region: lvds_region@56241000 { + compatible = "syscon"; + reg = <0x56241000 0xf0>; + }; + + ldb1_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-phy"; + reg = <0x56241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + gpr = <&lvds0_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch1>; + }; + }; + }; + }; + + pwm_lvds0: pwm@56244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + clocks = <&lvds0_pwm_lpcg 0>, + <&lvds0_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + status = "disabled"; + }; + + i2c0_lvds0: i2c@56246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>, + <&lvds0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56247000 0x1000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>, + <&lvds0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + }; + + lvds2_subsys: bus@57240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57240000 0x0 0x57240000 0x10000>; + + lvds1_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds1_ipg_clk"; + }; + + lvds1_lis_lpcg: clock-controller@57243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds1_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_pwm_lpcg: clock-controller@5724300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5724300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_pwm_lpcg_clk", + "lvds1_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + }; + + lvds1_i2c0_lpcg: clock-controller@57243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c0_lpcg_clk", + "lvds1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + lvds1_i2c1_lpcg: clock-controller@57243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c1_lpcg_clk", + "lvds1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + irqsteer_lvds1: irqsteer@57240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57240000 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_region: lvds_region@57241000 { + compatible = "syscon"; + reg = <0x57241000 0xf0>; + }; + + ldb2_phy: ldb_phy@57241000 { + compatible = "mixel,lvds-phy"; + reg = <0x57241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + + ldb2_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb2_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + gpr = <&lvds1_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch1>; + }; + }; + }; + }; + + pwm_lvds1: pwm@57244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x57244000 0x1000>; + clocks = <&lvds1_pwm_lpcg 0>, + <&lvds1_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + status = "disabled"; + }; + + i2c0_lvds1: i2c@57246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>, + <&lvds1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57247000 0x1000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>, + <&lvds1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi new file mode 100644 index 000000000000..ba166abbab3c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + dsi_ipg_clk: clock-dsi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dsi_ipg_clk"; + }; + + mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; + }; + + mipi0_subsys: bus@56220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56220000 0x0 0x56220000 0x10000>; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_i2c0_lpcg_clk: clock-controller@5622301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223018 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223014 0x4>; + #clock-cells = <1>; + clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c1_lpcg_clk: clock-controller@5622302c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622302c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223028 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223024 0x4>; + #clock-cells = <1>; + clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + irqsteer_mipi0: irqsteer@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + i2c0_mipi0: i2c@56226000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi0>; + clocks = <&mipi0_i2c0_lpcg_clk 0>, + <&mipi0_i2c0_lpcg_ipg_clk 0>; + clock-names = "per", "ipg"; + assigned-clocks = <&mipi0_i2c0_lpcg_clk 0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi0_csr: csr@56221000 { + compatible = "syscon"; + reg = <0x56221000 0x240>; + }; + + mipi0_dphy: dphy@56228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi0_dsi_host: dsi_host@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-nwl-dsi"; + reg = <0x56228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + phys = <&mipi0_dphy>; + phy-names = "dphy"; + csr = <&mipi0_csr>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi0_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu1_disp0_mipi0>; + }; + }; + }; + }; + }; + + mipi1_subsys: bus@57220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57220000 0x0 0x57220000 0x10000>; + + mipi1_lis_lpcg: clock-controller@57223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223000 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_i2c0_lpcg_clk: clock-controller@5722301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5722301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223018 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223014 0x4>; + #clock-cells = <1>; + clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c1_lpcg_clk: clock-controller@5722302c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5722302c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223028 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223024 0x4>; + #clock-cells = <1>; + clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + irqsteer_mipi1: irqsteer@57220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57220000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + i2c0_mipi1: i2c@57226000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi1>; + clocks = <&mipi1_i2c0_lpcg_clk 0>, + <&mipi1_i2c0_lpcg_ipg_clk 0>; + clock-names = "per", "ipg"; + assigned-clocks = <&mipi1_i2c0_lpcg_clk 0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi1_csr: csr@57221000 { + compatible = "syscon"; + reg = <0x57221000 0x240>; + }; + + mipi1_dphy: dphy@57228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x57228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; + + mipi1_dsi_host: dsi_host@57228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-nwl-dsi"; + reg = <0x57228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + phys = <&mipi1_dphy>; + phy-names = "dphy"; + csr = <&mipi1_csr>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi1_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu2_disp0_mipi1>; + }; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi new file mode 100644 index 000000000000..39fcd8b5c8bc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&fec1 { + /delete-property/ iommus; +}; + +&fec2 { + /delete-property/ iommus; +}; + +&sata { + /delete-property/ iommus; +}; + +&usbotg3 { + /delete-property/ iommus; +}; + +&smmu { + /* xen only supports legacy bindings for now */ + #iommu-cells = <0>; +}; + +&dpu1 { + fsl,sc_rsrc_id = <IMX_SC_R_DC_0_BLIT0>, + <IMX_SC_R_DC_0_BLIT1>, + <IMX_SC_R_DC_0_BLIT2>, + <IMX_SC_R_DC_0_BLIT_OUT>, + <IMX_SC_R_DC_0_WARP>, + <IMX_SC_R_DC_0_VIDEO0>, + <IMX_SC_R_DC_0_VIDEO1>, + <IMX_SC_R_DC_0_FRAC0>, + <IMX_SC_R_DC_0>; +}; + +&dpu2 { + fsl,sc_rsrc_id = <IMX_SC_R_DC_1_BLIT0>, + <IMX_SC_R_DC_1_BLIT1>, + <IMX_SC_R_DC_1_BLIT2>, + <IMX_SC_R_DC_1_BLIT_OUT>, + <IMX_SC_R_DC_1_WARP>, + <IMX_SC_R_DC_1_VIDEO0>, + <IMX_SC_R_DC_1_VIDEO1>, + <IMX_SC_R_DC_1_FRAC0>, + <IMX_SC_R_DC_1>; +}; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + fsl,sc_rsrc_id = <IMX_SC_R_DMA_2_CH0>, + <IMX_SC_R_DMA_2_CH1>, + <IMX_SC_R_DMA_2_CH2>, + <IMX_SC_R_DMA_2_CH3>, + <IMX_SC_R_DMA_2_CH4>, + <IMX_SC_R_DMA_2_CH5>, + <IMX_SC_R_DMA_2_CH6>, + <IMX_SC_R_DMA_2_CH7>, + <IMX_SC_R_DMA_2_CH8>, + <IMX_SC_R_DMA_2_CH9>, + <IMX_SC_R_DMA_2_CH10>, + <IMX_SC_R_DMA_2_CH11>, + <IMX_SC_R_DMA_2_CH12>, + <IMX_SC_R_DMA_2_CH13>, + <IMX_SC_R_DMA_2_CH14>, + <IMX_SC_R_DMA_2_CH15>, + <IMX_SC_R_DMA_2_CH16>, + <IMX_SC_R_DMA_2_CH17>, + <IMX_SC_R_DMA_2_CH18>, + <IMX_SC_R_DMA_2_CH19>; +}; + +&edma1 { + xen,passthrough; +}; + +&acm { + xen,passthrough; +}; + +&asrc0 { + xen,passthrough; +}; + +&esai0 { + xen,passthrough; +}; + +&spdif0 { + xen,passthrough; +}; + +&spdif1 { + xen,passthrough; +}; + +&sai0 { + xen,passthrough; +}; + +&sai1 { + xen,passthrough; +}; + +&sai2 { + xen,passthrough; +}; + +&sai3 { + xen,passthrough; +}; + +&asrc1 { + xen,passthrough; +}; + +&amix { + xen,passthrough; +}; + +&asrc0_lpcg { + xen,passthrough; +}; + +&esai0_lpcg { + xen,passthrough; +}; + +&spdif0_lpcg { + xen,passthrough; +}; + +&spdif1_lpcg { + xen,passthrough; +}; + +&sai0_lpcg { + xen,passthrough; +}; + +&sai1_lpcg { + xen,passthrough; +}; + +&sai2_lpcg { + xen,passthrough; +}; + +&sai3_lpcg { + xen,passthrough; +}; + +&asrc1_lpcg { + xen,passthrough; +}; + +&mqs0_lpcg { + xen,passthrough; +}; + +&dsp_lpcg { + xen,passthrough; +}; + +&dsp_ram_lpcg { + xen,passthrough; +}; + +&sai4 { + xen,passthrough; +}; + +&sai5 { + xen,passthrough; +}; + +&esai1 { + xen,passthrough; +}; + +&sai6 { + xen,passthrough; +}; + +&sai7 { + xen,passthrough; +}; + +&sai4_lpcg { + xen,passthrough; +}; + +&sai5_lpcg { + xen,passthrough; +}; + +&esai1_lpcg { + xen,passthrough; +}; + +&sai6_lpcg { + xen,passthrough; +}; + +&sai7_lpcg { + xen,passthrough; +}; + +&amix_lpcg { + xen,passthrough; +}; + +&aud_rec0_lpcg { + xen,passthrough; +}; + +&aud_rec1_lpcg { + xen,passthrough; +}; + +&aud_pll_div0_lpcg { + xen,passthrough; +}; + +&aud_pll_div1_lpcg { + xen,passthrough; +}; + +&mclkout0_lpcg { + xen,passthrough; +}; + +&mclkout1_lpcg { + xen,passthrough; +}; + +/ { + +dma_subsys: bus@5a000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + /* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ + edma214: dma-controller@5a2e0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan14", "edma0-chan15"; + status = "okay"; + fsl,sc_rsrc_id = <IMX_SC_R_DMA_0_CH14>, + <IMX_SC_R_DMA_0_CH15>; + }; +}; +}; + +&edma2 { + reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ + <0x5a300000 0x10000>, /* channel16 UART2 rx */ + <0x5a310000 0x10000>, /* channel17 UART2 tx */ + <0x5a320000 0x10000>, /* channel18 UART3 rx */ + <0x5a330000 0x10000>, /* channel19 UART3 tx */ + <0x5a340000 0x10000>, /* channel20 UART4 rx */ + <0x5a350000 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <12>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan6", "edma0-chan7", + "edma0-chan12", "edma0-chan13", + "edma0-chan16", "edma0-chan17", + "edma0-chan18", "edma0-chan19", + "edma0-chan20", "edma0-chan21"; + status = "okay"; +}; + +&lpspi0 { +}; + +&lpuart1 { + dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; +}; + +&lpuart2 { +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi new file mode 100755 index 000000000000..2005e40f6763 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + mu1 = &lsio_mu1; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + dpu0 = &dpu1; + dpu1 = &dpu2; + ldb0 = &ldb1; + ldb1 = &ldb2; + i2c0 = &i2c_rpbus_0; + i2c1 = &i2c_rpbus_1; + dphy0 = &mipi0_dphy; + dphy1 = &mipi1_dphy; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&A72_0>; + }; + core1 { + cpu = <&A72_1>; + }; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + a53_opp_table: a53-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-896000000 { + opp-hz = /bits/ 64 <896000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + a72_opp_table: a72-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1596000000 { + opp-hz = /bits/ 64 <1596000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3 + &lsio_mu1 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + ocotp: imx8qm-ocotp { + compatible = "fsl,imx8qm-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + read-only; + + fec_mac0: mac@1c4 { + reg = <0x1c4 6>; + }; + + fec_mac1: mac@1c6 { + reg = <0x1c6 6>; + }; + }; + + rtc: rtc { + compatible = "fsl,imx8qm-sc-rtc"; + }; + + watchdog { + compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qm-sc-thermal"; + tsens-num = <6>; + #thermal-sensor-cells = <1>; + }; + + secvio: secvio { + compatible = "fsl,imx-sc-secvio"; + nvmem = <&ocotp>; + }; + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A53>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A72>; + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + rpmsg0: rpmsg0{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + status = "disabled"; + }; + + rpmsg1: rpmsg1{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu6 0 1 + &lsio_mu6 1 1 + &lsio_mu6 3 1>; + mub-partition = <4>; + status = "disabled"; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + + vpu_subsys_dsp: bus@55000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x55000000 0x0 0x55000000 0x1000000>; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qm-dsp"; + reg = <0x556e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + memory-region = <&dsp_reserved>; + fixup-offset = <0x4000000>; + status = "disabled"; + }; + }; + + /* sorted in register address */ + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm41.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-img.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" +}; + +#include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-ddr.dtsi" +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-img.dtsi" +#include "imx8qm-ss-gpu.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts new file mode 100644 index 000000000000..882b52adc03d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qp.dtsi" +#include "imx8q-val.dtsi" + +/ { + model = "Freescale i.MX8QP Validation Board"; + compatible = "fsl,imx8qp-val", "fsl,imx8qp", "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp.dtsi b/arch/arm64/boot/dts/freescale/imx8qp.dtsi new file mode 100644 index 000000000000..ab657da22882 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QP"; + compatible = "fsl,imx8qp", "fsl,imx8qm"; +}; + +&cpus { + cpu-map { + cluster1 { + /delete-node/ core1; + }; + }; + /delete-node/ cpu@101; +}; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&gpu_3d1 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&imx8_gpu_ss {/*<freq-kHz vol-uV>*/ + operating-points = < + /*nominal*/ 625000 0 + 625000 0 +/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; +}; + +&thermal_zones { + cpu-thermal1 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts new file mode 100644 index 000000000000..4587edd5ddf8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" +#include "imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8QXP 17x17 Validation Board"; + compatible = "fsl,imx8qxp-17x17-val", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts index 91eef9754101..ee1610b5db66 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts @@ -13,13 +13,13 @@ compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp"; aliases { - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; }; chosen { - stdout-path = &adma_lpuart2; + stdout-path = &lpuart2; }; memory@80000000 { @@ -82,7 +82,7 @@ }; /* BT */ -&adma_lpuart0 { +&lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; uart-has-rtscts; @@ -90,21 +90,21 @@ }; /* LS-UART0 */ -&adma_lpuart1 { +&lpuart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart1>; status = "okay"; }; /* Debug */ -&adma_lpuart2 { +&lpuart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart2>; status = "okay"; }; /* PCI-E UART */ -&adma_lpuart3 { +&lpuart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart3>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts new file mode 100644 index 000000000000..05411ec714a6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-lpddr4-val.dts" + +/ { + model = "Freescale i.MX8QXP DDR3L VALIDATION"; + compatible = "fsl,imx8qxp-ddr3l-val", "fsl,imx8qxp"; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi new file mode 100644 index 000000000000..d8d5b37196df --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_DISABLE_50>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + /delete-property/ phy-supply; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + tja110x,refclk_in; + }; + }; +}; + +&iomuxc { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT 0x06000020 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x06000020 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts new file mode 100644 index 000000000000..74695fd4a8e0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-lpddr4-val.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts new file mode 100644 index 000000000000..369c942694e6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts new file mode 100644 index 000000000000..ef997e2f9361 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi2 { + fsl,pins = < + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x600004c + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x600004c + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x600004c + IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x600004c + >; +}; + +&lpspi2 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi2>; + /delete-property/ cs-gpios; + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts new file mode 100644 index 000000000000..bc4535647fc4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&iomuxc { + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x600004c + IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x600004c + IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x21 + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x600004c + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x600004c + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x600004c + IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x600004c + >; + }; +}; + +&lpspi0 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi2 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts new file mode 100644 index 000000000000..f4a180867eae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&esai0 { + status = "disabled"; +}; + +&mlb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts new file mode 100644 index 000000000000..dacf725d2487 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qxp-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_MQS_L 0xc6000061 + IMX8QXP_SPDIF0_RX_ADMA_MQS_R 0xc6000061 + >; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts new file mode 100644 index 000000000000..81ec0d0e9b98 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts @@ -0,0 +1,56 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 + IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&spdif0 { + compatible = "fsl,imx8qm-spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&spdif0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts new file mode 100755 index 000000000000..e53b7e670202 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP LPDDR4 Validation Board"; + compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp"; + + chosen { + stdout-path = &lpuart0; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; +}; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG 0x21 + IMX8QXP_ESAI0_FST_CONN_MLB_CLK 0x21 + IMX8QXP_ESAI0_TX0_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts new file mode 100644 index 000000000000..16b0261ded57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts new file mode 100644 index 000000000000..9cd0ea20937f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + + stdout-path = &lpuart0; + + module@0 { + bootargs = "earlycon=xen console=hvc0 root=/dev/mmcblk1p2 rootwait rw"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + /* The size will be override by uboot command */ + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x30000000>; + alloc-ranges = <0 0xb0000000 0 0x40000000>; + linux,cma-default; + }; + }; + + rtc0: rtc@23000000 { + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + xen,passthrough; + }; +}; + +&imx8_gpu_ss { + reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; + status = "okay"; +}; + +&lsio_mu1 { + /* not map for dom0, dom0 will mmio trap to xen */ + xen,no-map; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts new file mode 100644 index 000000000000..24a370642674 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-dpu-lcdif.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts new file mode 100644 index 000000000000..2d3bd4eb2c89 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-dpu-lcdif.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts new file mode 100644 index 000000000000..614705c26b39 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-dsi-rm67191.dts" +#include "imx8x-mek-rpmsg.dtsi" + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..d17639e0afd6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&lvds_bridge0 { + status = "disabled"; +}; + +&lvds_bridge1 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts new file mode 100644 index 000000000000..03fbdd76c1b8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0 &pinctrl_lpuart2>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp-v1"; + reserved-region = <&dsp_reserved>; + reg = <0x596e8000 0x88000>; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&asrc0_lpcg 0>, + <&clk_dummy>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&uart2_lpcg 1>, <&uart2_lpcg 0>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", "uart_ipg", + "uart_per"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>, + <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; + audio-interface = "esai"; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>, <80000000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_UART_2>; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; +}; + +&lpuart2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..7651dc6fa682 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-mek-enet2.dts" +#include "imx8qxp-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts new file mode 100644 index 000000000000..2a77456c74da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-mek.dts" + +&esai0 { + status = "disabled"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts new file mode 100644 index 000000000000..89669251f81c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8qxp.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QXP MEK Inmate"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-adma.dtsi" +#include "imx8qxp-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +/delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts new file mode 100644 index 000000000000..8debd826171b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts new file mode 100644 index 000000000000..07bb468e227d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts new file mode 100644 index 000000000000..26cead50be3c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts new file mode 100644 index 000000000000..406047eb5cd0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts new file mode 100644 index 000000000000..8903d2d99a66 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts new file mode 100644 index 000000000000..5027beb1cef0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts new file mode 100644 index 000000000000..01560ad50724 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..1982c4afa84f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts new file mode 100644 index 000000000000..20adc45ec8ca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-lcdif.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts new file mode 100644 index 000000000000..cc65560a7e8f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-lcdif.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts new file mode 100644 index 000000000000..b3e608689701 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 +#include "imx8qxp-mek-ov5640.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts new file mode 100644 index 000000000000..2ceac305f7ac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek.dts" + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts new file mode 100644 index 000000000000..e259b929475c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" + +&pcieb{ + status = "disabled"; +}; + +&lsio_mu8{ + doorbell-reg = <0x5d2c0000 0x10000>; + status = "okay"; +}; + +&pcieb_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + ext_osc = <1>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts new file mode 100644 index 000000000000..5f4ee5adbec8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_UART_2 + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8QXP_EMMC0_CLK + IMX8QXP_EMMC0_CMD + IMX8QXP_EMMC0_DATA0 + IMX8QXP_EMMC0_DATA1 + IMX8QXP_EMMC0_DATA2 + IMX8QXP_EMMC0_DATA3 + IMX8QXP_EMMC0_DATA4 + IMX8QXP_EMMC0_DATA5 + IMX8QXP_EMMC0_DATA6 + IMX8QXP_EMMC0_DATA7 + IMX8QXP_EMMC0_STROBE + /* lpuart2 */ + IMX8QXP_UART2_TX + IMX8QXP_UART2_RX + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@fdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@df7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&usdhc1 { + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts new file mode 100644 index 000000000000..412f32a4b8b8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts new file mode 100644 index 000000000000..87ec14d02b6e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-audio-cs42888 { + compatible = "simple-audio-card"; + label = "imx-cs42888"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack", + "Playback", "ESAI0.OUT"; + status = "okay"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 0>; + }; + + codec { + sound-dai = <&cs42888>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8qxp-dsp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + + power-domains = <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>; + clock-names = "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + reg = <0x596e8000 0x88000>; + tplg-name = "sof-imx8qxp-cs42888.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts new file mode 100644 index 000000000000..6eeda70d1a91 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio1 0 0>; + mic-det-gpio = <&lsio_gpio1 0 0>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack", + "Playback", "SAI1.OUT", + "SAI1.IN", "Capture"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8qxp-dsp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + + + clock-names = "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; + clocks = <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + reg = <0x596e8000 0x88000>; + tplg-name = "sof-imx8qxp-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&cs42888 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-vop.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-vop.dts new file mode 100644 index 000000000000..1e7255a679bd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-vop.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" + +&resmem { + fsl,imx_mic { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2000000>; + alloc-ranges = <0 0xf8000000 0 0x2000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 8148196902dd..715a52a5abbe 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -1,231 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017~2018 NXP + * Copyright 2017-2020 NXP */ /dts-v1/; #include "imx8qxp.dtsi" +#include "imx8x-mek.dtsi" / { model = "Freescale i.MX8QXP MEK"; compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; - - chosen { - stdout-path = &adma_lpuart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - }; - - reg_usdhc2_vmmc: usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&adma_i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9646", "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - pca9557_a: gpio@1a { - compatible = "nxp,pca9557"; - reg = <0x1a>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@1d { - compatible = "nxp,pca9557"; - reg = <0x1d>; - gpio-controller; - #gpio-cells = <2>; - }; - - light-sensor@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "isil,isl29023"; - reg = <0x44>; - interrupt-parent = <&lsio_gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; - }; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_ioexp_rst: ioexp_rst_grp { - fsl,pins = < - IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 - >; - }; - - pinctrl_isl29023: isl29023grp { - fsl,pins = < - IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 - IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; -}; - -&adma_dsp { - status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi new file mode 100644 index 000000000000..f1b9b0da5e6d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&dma_ipg_clk { + clock-frequency = <160000000>; +}; + +&audio_ipg_clk { + clock-frequency = <160000000>; +}; + +&lpuart0 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&lpuart1 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&lpuart2 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&lpuart3 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&i2c0 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c1 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c2 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c3 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&audio_subsys { + + dsp: dsp@596e8000 { + compatible = "fsl,imx8qxp-dsp"; + reg = <0x596e8000 0x88000>; + clocks = <&dsp_lpcg 1>, + <&dsp_ram_lpcg 0>, + <&dsp_lpcg 2>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + mbox-names = "txdb0", "txdb1", + "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + status = "disabled"; + }; +}; + +&dma_subsys { + lcdif_mux_regs: mux-regs@5a170000 { + compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon"; + reg = <0x5a170000 0x4>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi new file mode 100644 index 000000000000..f8ad22a7d1e2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&usdhc1 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; + +&fec1 { + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; +}; + +&fec2 { + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi new file mode 100644 index 000000000000..a929c3a2341a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +&dpu1 { + compatible = "fsl,imx8qxp-dpu"; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_ldb1_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_ldb1_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi0_dsi_in>; + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_ldb2_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_ldb2_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi1_dsi_in>; + }; + + dpu_disp1_lcdif: endpoint@3 { + }; + }; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi new file mode 100644 index 000000000000..424a25582434 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&gpu0_subsys { + imx8_gpu_ss: imx8_gpu0_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi new file mode 100644 index 000000000000..4fae19e5edb4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Richard Zhu <hongxing.zhu@nxp.com> + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi new file mode 100644 index 000000000000..b455ed6fc483 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&csi1_pxl_lpcg { + status = "disabled"; +}; + +&csi1_core_lpcg { + status = "disabled"; +}; + +&csi1_esc_lpcg { + status = "disabled"; +}; + +&irqsteer_csi1 { + status = "disabled"; +}; + +&i2c_mipi_csi1 { + status = "disabled"; +}; + +&gpio0_mipi_csi1 { + status = "disabled"; +}; + +&mipi_csi_1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi new file mode 100644 index 000000000000..48ffdb001a33 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&lsio_gpio0 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_mu0 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu1 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu2 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu3 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu4 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi new file mode 100644 index 000000000000..c8b5468f2d86 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds_subsys: bus@56220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56220000 0x0 0x56220000 0x30000>; + + mipi_ipg_clk: clock-mipi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_ipg_clk"; + }; + + mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; + }; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_pwm_lpcg: clock-controller@5622300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi0_pwm_lpcg_clk", + "mipi0_pwm_lpcg_ipg_clk", + "mipi0_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + }; + + mipi0_i2c0_lpcg: clock-controller@56223010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi0_i2c0_lpcg_clk", + "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi1_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi1_pwm_lpcg_clk", + "mipi1_pwm_lpcg_ipg_clk", + "mipi1_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + }; + + mipi1_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi1_i2c0_lpcg_clk", + "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + lvds_region1: lvds_region@56221000 { + compatible = "syscon"; + reg = <0x56221000 0xf0>; + }; + + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56221000 0x100>, <0x56228000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + }; + + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass", + "aux_pixel", "aux_bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>, + <&pd IMX_SC_R_LVDS_1>; + power-domain-names = "main", "aux"; + gpr = <&lvds_region1>; + fsl,auxldb = <&ldb2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds0: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56224000 0x1000>; + clocks = <&mipi0_pwm_lpcg 0>, + <&mipi0_pwm_lpcg 1>, + <&mipi0_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&mipi0_i2c0_lpcg 0>, + <&mipi0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi0_dphy: dphy@56228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi0_dsi_host: dsi_host@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + phys = <&mipi0_dphy>; + phy-names = "dphy"; + csr = <&lvds_region1>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi0_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp0_mipi_dsi>; + }; + }; + }; + }; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + lvds_region2: lvds_region@56241000 { + compatible = "syscon"; + reg = <0x56241000 0xf0>; + }; + + ldb2_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56241000 0x100>, <0x56248000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + }; + + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass", + "aux_pixel", "aux_bypass"; + power-domains = <&pd IMX_SC_R_LVDS_1>, + <&pd IMX_SC_R_LVDS_0>; + power-domain-names = "main", "aux"; + gpr = <&lvds_region2>; + fsl,auxldb = <&ldb1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds1: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + clocks = <&mipi1_pwm_lpcg 0>, + <&mipi1_pwm_lpcg 1>, + <&mipi1_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&mipi1_i2c0_lpcg 0>, + <&mipi1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi1_dphy: dphy@56248300 { + compatible = "fsl,imx8qx-mipi-dphy"; + reg = <0x56248300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; + + mipi1_dsi_host: dsi_host@56248000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56248000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + phys = <&mipi1_dphy>; + phy-names = "dphy"; + csr = <&lvds_region2>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi1_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp1_mipi_dsi>; + }; + }; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 1133b412182a..89f6f168cd4b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * Dong Aisheng <aisheng.dong@nxp.com> */ @@ -9,7 +9,9 @@ #include <dt-bindings/firmware/imx/rsrc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/pads-imx8qxp.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -17,6 +19,8 @@ #size-cells = <2>; aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; gpio0 = &lsio_gpio0; gpio1 = &lsio_gpio1; gpio2 = &lsio_gpio2; @@ -25,17 +29,40 @@ gpio5 = &lsio_gpio5; gpio6 = &lsio_gpio6; gpio7 = &lsio_gpio7; + dpu0 = &dpu1; + ldb0 = &ldb1; + ldb1 = &ldb2; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; mu1 = &lsio_mu1; - serial0 = &adma_lpuart0; - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + i2c1 = &i2c_rpbus_1; + i2c5 = &i2c_rpbus_5; + i2c12 = &i2c_rpbus_12; + i2c13 = &i2c_rpbus_13; + i2c14 = &i2c_rpbus_14; + i2c15 = &i2c_rpbus_15; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; }; - cpus { + cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -46,7 +73,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -57,7 +84,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -68,7 +95,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -79,7 +106,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -152,9 +179,16 @@ &lsio_mu1 1 3 &lsio_mu1 3 3>; + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; + }; + clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; clocks = <&xtal32k &xtal24m>; clock-names = "xtal_32KHz", "xtal_24Mhz"; }; @@ -167,21 +201,40 @@ compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; - }; + read-only; - pd: imx8qx-pd { - compatible = "fsl,imx8qxp-scu-pd"; - #power-domain-cells = <1>; + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; }; rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; + secvio: secvio { + compatible = "fsl,imx-sc-secvio"; + nvmem = <&ocotp>; + }; + watchdog { compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; timeout-sec = <60>; }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal"; + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; }; timer { @@ -192,6 +245,43 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 355>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -206,395 +296,72 @@ clock-output-names = "xtal_24MHz"; }; - adma_subsys: bus@59000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x59000000 0x0 0x59000000 0x2000000>; - - adma_lpcg: clock-controller@59000000 { - compatible = "fsl,imx8qxp-lpcg-adma"; - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - - adma_dsp: dsp@596e8000 { - compatible = "fsl,imx8qxp-dsp"; - reg = <0x596e8000 0x88000>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; - clock-names = "ipg", "ocram", "core"; - power-domains = <&pd IMX_SC_R_MU_13A>, - <&pd IMX_SC_R_MU_13B>, - <&pd IMX_SC_R_DSP>, - <&pd IMX_SC_R_DSP_RAM>; - mbox-names = "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes = <&lsio_mu13 2 0>, - <&lsio_mu13 2 1>, - <&lsio_mu13 3 0>, - <&lsio_mu13 3 1>; - memory-region = <&dsp_reserved>; - status = "disabled"; - }; - - adma_lpuart0: serial@5a060000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a060000 0x1000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_0>; - status = "disabled"; - }; - - adma_lpuart1: serial@5a070000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a070000 0x1000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_1>; - status = "disabled"; - }; - - adma_lpuart2: serial@5a080000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a080000 0x1000>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_2>; - status = "disabled"; - }; - - adma_lpuart3: serial@5a090000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a090000 0x1000>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_3>; - status = "disabled"; - }; - - adma_i2c0: i2c@5a800000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a800000 0x4000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_0>; - status = "disabled"; - }; - - adma_i2c1: i2c@5a810000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a810000 0x4000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_1>; - status = "disabled"; - }; - - adma_i2c2: i2c@5a820000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a820000 0x4000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_2>; - status = "disabled"; - }; - - adma_i2c3: i2c@5a830000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a830000 0x4000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_3>; - status = "disabled"; - }; + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; }; - conn_subsys: bus@5b000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - - conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - - usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_0>; - status = "disabled"; - }; - - usdhc2: mmc@5b020000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_1>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc3: mmc@5b030000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_2>; - status = "disabled"; - }; - - fec1: ethernet@5b040000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b040000 0x10000>; - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_0>; - status = "disabled"; - }; - - fec2: ethernet@5b050000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b050000 0x10000>; - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_1>; - status = "disabled"; - }; + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + status = "disabled"; }; - ddr_subsyss: bus@5c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; - - ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; - reg = <0x5c020000 0x10000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - }; + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; }; - lsio_subsys: bus@5d000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; - - lsio_gpio0: gpio@5d080000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d080000 0x10000>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_0>; - }; - - lsio_gpio1: gpio@5d090000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d090000 0x10000>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_1>; - }; - - lsio_gpio2: gpio@5d0a0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0a0000 0x10000>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_2>; - }; - - lsio_gpio3: gpio@5d0b0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0b0000 0x10000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_3>; - }; - - lsio_gpio4: gpio@5d0c0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0c0000 0x10000>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_4>; - }; - - lsio_gpio5: gpio@5d0d0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0d0000 0x10000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_5>; - }; - - lsio_gpio6: gpio@5d0e0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0e0000 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_6>; - }; - - lsio_gpio7: gpio@5d0f0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0f0000 0x10000>; - interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_7>; - }; - - lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1b0000 0x10000>; - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1c0000 0x10000>; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - }; - - lsio_mu2: mailbox@5d1d0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1d0000 0x10000>; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1e0000 0x10000>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; - }; + /* sorted in register address */ + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm40.dtsi" + #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-img.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-lcdif.dtsi" +}; - lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1f0000 0x10000>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; - }; +#include "imx8qxp-ss-adma.dtsi" +#include "imx8qxp-ss-conn.dtsi" +#include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-hsio.dtsi" +#include "imx8qxp-ss-img.dtsi" +#include "imx8qxp-ss-dc.dtsi" +#include "imx8qxp-ss-lvds.dtsi" +#include "imx8qxp-ss-gpu.dtsi" + +&edma2 { + status = "okay"; +}; - lsio_mu13: mailbox@5d280000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d280000 0x10000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - power-domains = <&pd IMX_SC_R_MU_13A>; - }; +&A35_0 { + operating-points = < + /* kHz uV*/ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 900000 0 + >; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; - lsio_lpcg: clock-controller@5d400000 { - compatible = "fsl,imx8qxp-lpcg-lsio"; - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - }; +&dsp { + memory-region = <&dsp_reserved>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi new file mode 100644 index 000000000000..7a609d29836a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8x-val.dtsi" + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; + + regulators { + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + imx8qxp-lpddr4-arm2 { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + >; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + /delete-node/ gpio@68; + /delete-node/ typec@3d; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + /delete-node/ gpio@18; + /delete-node/ gpio@19; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_mipi_csi0 { + status = "disabled"; +}; + +&mipi_csi_0 { + status = "disabled"; +}; + +&gpio0_mipi_csi0 { + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + disable-gpio = <&pca9557_a 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + /delete-node/ mt35xu512aba@0; + + flash0: mt25qu512abb@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu512abb"; + spi-max-frequency = <29000000>; + }; +}; + +&adc0 { + status = "disabled"; +}; + +&usbotg1 { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi new file mode 100644 index 000000000000..d4fe033cb939 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + panel { + compatible = "sii,43wvf1g"; + backlight = <&lcdif_backlight>; + status = "okay"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcdif_backlight: lcdif-backlight { + compatible = "pwm-backlight"; + pwms = <&adma_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&dpu_disp1_lcdif { + remote-endpoint = <&lcd_display_in>; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000 + >; + }; +}; + +&sai1 { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdifpwm>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi new file mode 100644 index 000000000000..fc09e0f65ca7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +&i2c0_mipi_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + fsl,dual-channel; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi new file mode 100644 index 000000000000..77e32fd2826e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +&i2c0_mipi_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2 { + fsl,dual-channel; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi new file mode 100644 index 000000000000..51a744ed8ba1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +/delete-node/ &it6263_0_in; + +&ldb1 { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds0_in>; + }; + }; + }; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi new file mode 100644 index 000000000000..58255c03b854 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight0>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +/delete-node/ &it6263_1_in; + +&ldb2 { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&ldb1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi new file mode 100644 index 000000000000..73d5cd433191 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +/ { + display-subsystem { + status = "disabled"; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&lcdif_backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&adapter_out>; + }; + }; + }; + + seiko_adapter: seiko-adapter { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,seiko-43wvfig"; + bus_mode = <18>; + + port@0 { + reg = <0>; + adapter_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + port@1 { + reg = <1>; + adapter_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + lcdif_backlight: lcdif-backlight { + compatible = "pwm-backlight"; + pwms = <&adma_pwm 0 100000 0>; + status = "okay"; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&iomuxc { + /delete-node/ pinctrl_hog; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdifpwm>; + status = "okay"; +}; + +&adma_pwm_lpcg { + status = "okay"; +}; + + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port@0 { + lcdif_out: endpoint { + remote-endpoint = <&adapter_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi new file mode 100644 index 000000000000..47243b55d06b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/delete-node/ &cm40_i2c; +/delete-node/ &i2c1; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&pi0_misc_lpcg 0>; + assigned-clocks = <&pi0_misc_lpcg 0>; + assigned-clock-rates = <24000000>; + clock-names = "xclk"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&i2c_rpbus_12 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_rpbus_14 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; +}; + +&i2c_rpbus_15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <2 2>; + }; +}; + +&cm40_i2c_lpcg { + status = "disabled"; +}; + +&i2c1_lpcg { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +®_can_en { + status = "disabled"; +}; + +®_can_stby { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&cm40_intmux { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&lpuart3 { + status = "disabled"; +}; + +&uart3_lpcg { + status = "disabled"; +}; + +&imx8x_cm4 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi new file mode 100644 index 000000000000..3413a1fc3b27 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi @@ -0,0 +1,1544 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2020 NXP + */ + +#include <dt-bindings/usb/pd.h> +/ { + chosen { + stdout-path = &lpuart0; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <3480>; + enable-active-high; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&lsio_gpio1 0 0>; + mic-det-gpios = <&lsio_gpio1 0 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + imx8x_cm4: imx8x_cm4@0 { + compatible = "fsl,imx8qxp-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + core-index = <0>; + core-id = <IMX_SC_R_M4_0_PID0>; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + +}; + +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; + scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&pi0_misc_lpcg 0>; + assigned-clocks = <&pi0_misc_lpcg 0>; + assigned-clock-rates = <24000000>; + clock-names = "xclk"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + status = "okay"; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds_bridge0: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + status = "okay"; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds_bridge1: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp-v1"; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9646", "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + }; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + disable-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&vpu_decoder { + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d040000>; + core_type = <1>; + status = "okay"; +}; + +&vpu_encoder { + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + status = "okay"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1050000 0x10000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + interface = <6 0 2>; + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_cm40_i2c_gpio: cm40i2cgrp-gpio { + fsl,pins = < + IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c + IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_ioexp_rst: ioexp_rst_grp { + fsl,pins = < + IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 + IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 + IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 + IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + IMX8QXP_CSI_D00_CI_PI_D02 0xC0000041 + IMX8QXP_CSI_D01_CI_PI_D03 0xC0000041 + IMX8QXP_CSI_D02_CI_PI_D04 0xC0000041 + IMX8QXP_CSI_D03_CI_PI_D05 0xC0000041 + IMX8QXP_CSI_D04_CI_PI_D06 0xC0000041 + IMX8QXP_CSI_D05_CI_PI_D07 0xC0000041 + IMX8QXP_CSI_D06_CI_PI_D08 0xC0000041 + IMX8QXP_CSI_D07_CI_PI_D09 0xC0000041 + + IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 + IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xC0000041 + IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 + IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 + IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 + >; + }; + + pinctrl_lcdifpwm: lcdifpwmgrp { + fsl,pins = < + IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-val.dtsi b/arch/arm64/boot/dts/freescale/imx8x-val.dtsi new file mode 100644 index 000000000000..d6d0274b5bf1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-val.dtsi @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <2720>; + enable-active-high; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_audio: fixedregulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_baseboard: fixedregulator@1 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "baseboard_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_adc_vref_1v8: adc_vref_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + status = "okay"; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_adc_vref_1v8>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + imx8qxp-lpddr4-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0xc600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 + IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 + >; + }; + + pinctrl_csi0_lpi2c0: csi0lpi2c0grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_ptn5150: ptn5150 { + fsl,pins = < + IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x0600002c + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x0600002c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x0600002c + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x0600002c + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600002c + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600002c + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x0600002c + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x0600002c + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG 0x21 + IMX8QXP_ESAI0_FST_CONN_MLB_CLK 0x21 + IMX8QXP_ESAI0_TX0_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + status = "okay"; + }; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + reg = <0x3d>; + connect-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cm40_intmux { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi new file mode 100644 index 000000000000..0a68ec4c0026 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi @@ -0,0 +1,55 @@ +/* + * QorIQ BMan SDK Portals device tree nodes + * + * Copyright 2011-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +&bportals { + bman-portal@0 { + cell-index = <0>; + }; + + bman-portal@10000 { + cell-index = <1>; + }; + + bman-portal@20000 { + cell-index = <2>; + }; + + bman-portal@30000 { + cell-index = <3>; + }; + + bman-portal@40000 { + cell-index = <4>; + }; + + bman-portal@50000 { + cell-index = <5>; + }; + + bman-portal@60000 { + cell-index = <6>; + }; + + bman-portal@70000 { + cell-index = <7>; + }; + + bman-portal@80000 { + cell-index = <8>; + }; + + bman-portal@90000 { + cell-index = <9>; + }; + + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi new file mode 100644 index 000000000000..d3ae39944bf4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi @@ -0,0 +1,72 @@ +/* + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ] + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +fsldpaa: fsl,dpaa { + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + dma-coherent; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + dma-coherent; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + dma-coherent; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + dma-coherent; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + dma-coherent; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + dma-coherent; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + dma-coherent; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi index dbd2fc3ba790..801b6d095a29 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi @@ -9,16 +9,17 @@ fman@1a00000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; + fsl,qman-channel-id = <0x800>; }; ethernet@f0000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi index 6fc5d2560057..dad547c44450 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi @@ -9,16 +9,17 @@ fman@1a00000 { fman0_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; + fsl,qman-channel-id = <0x801>; }; ethernet@f2000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi index 4e02276fcf99..60ed4473ef84 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; + fsl,qman-channel-id = <0x802>; }; ethernet@e0000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi index 0312fa43fa77..69de2c1ff0c0 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; + fsl,qman-channel-id = <0x803>; }; ethernet@e2000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi index af2df07971dd..981bbfcaaa29 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; + fsl,qman-channel-id = <0x804>; }; ethernet@e4000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi index 4ac98dc8b227..956b1b9df696 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; + fsl,qman-channel-id = <0x805>; }; ethernet@e6000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi index bd932d8b0160..52899ce69580 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; + fsl,qman-channel-id = <0x806>; }; ethernet@e8000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi index 7de1c5203f3e..fe8c4c29bb5c 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman0_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; + fsl,qman-channel-id = <0x807>; }; ethernet@ea000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi new file mode 100644 index 000000000000..2d0df20db55e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi @@ -0,0 +1,47 @@ +/* + * QorIQ FMan v3 OH ports device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +fman@1a00000 { + + fman0_oh1: port@82000 { + cell-index = <0>; + compatible = "fsl,fman-port-oh"; + reg = <0x82000 0x1000>; + }; + + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; + + fman0_oh3: port@84000 { + cell-index = <2>; + compatible = "fsl,fman-port-oh"; + reg = <0x84000 0x1000>; + }; + + fman0_oh4: port@85000 { + cell-index = <3>; + compatible = "fsl,fman-port-oh"; + reg = <0x85000 0x1000>; + }; + + fman0_oh5: port@86000 { + cell-index = <4>; + compatible = "fsl,fman-port-oh"; + reg = <0x86000 0x1000>; + }; + + fman0_oh6: port@87000 { + cell-index = <5>; + compatible = "fsl,fman-port-oh"; + reg = <0x87000 0x1000>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi index 263b972a6d1e..a10a00543d08 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi @@ -20,45 +20,95 @@ fman0: fman@1a00000 { fsl,qman-channel-range = <0x800 0x10>; ptimer-handle = <&ptp_timer0>; + cc { + compatible = "fsl,fman-cc"; + }; + muram@0 { compatible = "fsl,fman-muram"; reg = <0x0 0x60000>; }; + bmi@80000 { + compatible = "fsl,fman-bmi"; + reg = <0x80000 0x400>; + }; + + qmi@80400 { + compatible = "fsl,fman-qmi"; + reg = <0x80400 0x400>; + }; + fman0_oh_0x2: port@82000 { cell-index = <0x2>; compatible = "fsl,fman-v3-port-oh"; reg = <0x82000 0x1000>; + fsl,qman-channel-id = <0x809>; }; fman0_oh_0x3: port@83000 { cell-index = <0x3>; compatible = "fsl,fman-v3-port-oh"; reg = <0x83000 0x1000>; + fsl,qman-channel-id = <0x80a>; }; fman0_oh_0x4: port@84000 { cell-index = <0x4>; compatible = "fsl,fman-v3-port-oh"; reg = <0x84000 0x1000>; + fsl,qman-channel-id = <0x80b>; }; fman0_oh_0x5: port@85000 { cell-index = <0x5>; compatible = "fsl,fman-v3-port-oh"; reg = <0x85000 0x1000>; + fsl,qman-channel-id = <0x80c>; }; fman0_oh_0x6: port@86000 { cell-index = <0x6>; compatible = "fsl,fman-v3-port-oh"; reg = <0x86000 0x1000>; + fsl,qman-channel-id = <0x80d>; }; fman0_oh_0x7: port@87000 { cell-index = <0x7>; compatible = "fsl,fman-v3-port-oh"; reg = <0x87000 0x1000>; + fsl,qman-channel-id = <0x80e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; }; mdio0: mdio@fc000 { @@ -77,7 +127,7 @@ fman0: fman@1a00000 { }; ptp_timer0: ptp-timer@1afe000 { - compatible = "fsl,fman-ptp-timer"; + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc"; reg = <0x0 0x1afe000 0x0 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 3 0>; diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi new file mode 100644 index 000000000000..d3abfaf6efde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi @@ -0,0 +1,38 @@ +/* + * QorIQ QMan SDK Portals device tree nodes + * + * Copyright 2011-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 256>; + }; + + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x401 0xf>; + }; + + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; + + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234-evb.dts b/arch/arm64/boot/dts/freescale/s32v234-evb.dts new file mode 100644 index 000000000000..d26845a39de8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234-evb.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017,2019 NXP + */ + +/dts-v1/; +#include "s32v234.dtsi" + +/ { + model = "NXP S32V234-EVB2 Board"; + compatible = "fsl,s32v234-evb", "fsl,s32v234"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&siul2 { + status = "okay"; + s32v234-evb { + + /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the + * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference + * Manual states. + */ + + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + S32V234_PAD_PA12__UART0_TXD + S32V234_PAD_PA11__UART0_RXD_OUT + S32V234_PAD_PA11__UART0_RXD_IN + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + S32V234_PAD_PA14__UART1_TXD + S32V234_PAD_PA13__UART1_RXD_OUT + S32V234_PAD_PA13__UART1_RXD_IN + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + S32V234_PAD_PK6__USDHC_CLK_OUT + S32V234_PAD_PK6__USDHC_CLK_IN + S32V234_PAD_PK7__USDHC_CMD_OUT + S32V234_PAD_PK7__USDHC_CMD_IN + S32V234_PAD_PK8__USDHC_DAT0_OUT + S32V234_PAD_PK8__USDHC_DAT0_IN + S32V234_PAD_PK9__USDHC_DAT1_OUT + S32V234_PAD_PK9__USDHC_DAT1_IN + S32V234_PAD_PK10__USDHC_DAT2_OUT + S32V234_PAD_PK10__USDHC_DAT2_IN + S32V234_PAD_PK11__USDHC_DAT3_OUT + S32V234_PAD_PK11__USDHC_DAT3_IN + S32V234_PAD_PK15__USDHC_DAT4_OUT + S32V234_PAD_PK15__USDHC_DAT4_IN + S32V234_PAD_PL0__USDHC_DAT5_OUT + S32V234_PAD_PL0__USDHC_DAT5_IN + S32V234_PAD_PL1__USDHC_DAT6_OUT + S32V234_PAD_PL1__USDHC_DAT6_IN + S32V234_PAD_PL2__USDHC_DAT7_OUT + S32V234_PAD_PL2__USDHC_DAT7_IN + >; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc0 { + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts new file mode 100644 index 000000000000..a481a1969928 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts @@ -0,0 +1,183 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 MicroSys Electronics GmbH + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; + +#include "s32v234.dtsi" + +/ { + model = "Freescale S32V234"; + compatible = "fsl,s32v234-sbc", "fsl,s32v234"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&siul2 { + status = "okay"; + + s32v234-sbc { + /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the + * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference + * Manual states. + */ + + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + /* + * Configure pin C12 as GPIO[6] in MSCR#6. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.75V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA6 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + /* + * Configure pin C11 as GPIO[7] in MSCR#7. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.39V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA7 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + S32V234_PAD_PC13__MDC + S32V234_PAD_PC14__MDIO_OUT + S32v234_PAD_PC14__MDIO_IN + S32V234_PAD_PC15__TXCLK_OUT + S32V234_PAD_PC15__TXCLK_IN + S32V234_PAD_PD0__RXCLK_OUT + S32V234_PAD_PD0__RXCLK_IN + S32V234_PAD_PD1__RX_D0_OUT + S32V234_PAD_PD1__RX_D0_IN + S32V234_PAD_PD2__RX_D1_OUT + S32V234_PAD_PD2__RX_D1_IN + S32V234_PAD_PD3__RX_D2_OUT + S32V234_PAD_PD3__RX_D2_IN + S32V234_PAD_PD4__RX_D3_OUT + S32V234_PAD_PD4__RX_D3_IN + S32V234_PAD_PD4__RX_DV_OUT + S32V234_PAD_PD4__RX_DV_IN + S32V234_PAD_PD7__TX_D0_OUT + S32V234_PAD_PD8__TX_D1_OUT + S32V234_PAD_PD9__TX_D2_OUT + S32V234_PAD_PD10__TX_D3_OUT + S32V234_PAD_PD11__TX_EN_OUT + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + S32V234_PAD_PA12__UART0_TXD + S32V234_PAD_PA11__UART0_RXD_OUT + S32V234_PAD_PA11__UART0_RXD_IN + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + S32V234_PAD_PA14__UART1_TXD + S32V234_PAD_PA13__UART1_RXD_OUT + S32V234_PAD_PA13__UART1_RXD_IN + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + S32V234_PAD_PK6__USDHC_CLK_OUT + S32V234_PAD_PK6__USDHC_CLK_IN + S32V234_PAD_PK7__USDHC_CMD_OUT + S32V234_PAD_PK7__USDHC_CMD_IN + S32V234_PAD_PK8__USDHC_DAT0_OUT + S32V234_PAD_PK8__USDHC_DAT0_IN + S32V234_PAD_PK9__USDHC_DAT1_OUT + S32V234_PAD_PK9__USDHC_DAT1_IN + S32V234_PAD_PK10__USDHC_DAT2_OUT + S32V234_PAD_PK10__USDHC_DAT2_IN + S32V234_PAD_PK11__USDHC_DAT3_OUT + S32V234_PAD_PK11__USDHC_DAT3_IN + S32V234_PAD_PK15__USDHC_DAT4_OUT + S32V234_PAD_PK15__USDHC_DAT4_IN + S32V234_PAD_PL0__USDHC_DAT5_OUT + S32V234_PAD_PL0__USDHC_DAT5_IN + S32V234_PAD_PL1__USDHC_DAT6_OUT + S32V234_PAD_PL1__USDHC_DAT6_IN + S32V234_PAD_PL2__USDHC_DAT7_OUT + S32V234_PAD_PL2__USDHC_DAT7_IN + >; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc0 { + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi new file mode 100644 index 000000000000..47db198b36ad --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/s32v234-clock.h> +#include <dt-bindings/pinctrl/s32v234-pinctrl.h> + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,s32v234"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + can0 = &can0; + can1 = &can1; + serial0 = &uart0; + serial1 = &uart1; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + fxosc { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster0_l2_cache>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster0_l2_cache>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster1_l2_cache>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&cluster1_l2_cache>; + }; + + cluster0_l2_cache: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2_cache: l2-cache1 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; + /* clock-frequency might be modified by u-boot, depending on the + * chip version. + */ + clock-frequency = <10000000>; + }; + + gic: interrupt-controller@7d001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x7d001000 0 0x1000>, + <0 0x7d002000 0 0x2000>, + <0 0x7d004000 0 0x2000>, + <0 0x7d006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + aips0: aips-bus@40000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + reg = <0x0 0x40000000 0x0 0x7d000>; + ranges; + + fec: ethernet@40032000 { + compatible = "fsl,s32v234-fec"; + reg = <0x0 0x40032000 0x0 0x1000>; + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks S32V234_CLK_SYS6>, + <&clks S32V234_CLK_SYS3>, + <&clks S32V234_CLK_ENET_TIME>, + <&clks S32V234_CLK_ENET>, + <&clks S32V234_CLK_ENET_TIME>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", + "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + + clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; + }; + + mc_cgm1: mc_cgm1@4003F000 { + compatible = "fsl,s32v234-mc_cgm1"; + reg = <0x0 0x4003F000 0x0 0x1000>; + }; + + mc_cgm2: mc_cgm2@40042000 { + compatible = "fsl,s32v234-mc_cgm2"; + reg = <0x0 0x40042000 0x0 0x1000>; + }; + + mc_cgm3: mc_cgm3@40045000 { + compatible = "fsl,s32v234-mc_cgm3"; + reg = <0x0 0x40045000 0x0 0x1000>; + }; + + mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; + }; + + uart0: serial@40053000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x0 0x40053000 0x0 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; + clocks = <&clks S32V234_CLK_LIN>; + clock-names = "lin"; + status = "disabled"; + }; + + can0: flexcan@40055000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x40055000 0x0 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usdhc0: usdhc@4005d000 { + compatible = "fsl,s32v234-usdhc"; + reg = <0x0 0x4005D000 0x0 0x1000>; + interrupts = <0 28 4>; + clocks = <&clks S32V234_CLK_SDHC>, + <&clks S32V234_CLK_SDHC>, + <&clks S32V234_CLK_SDHC>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + status = "disabled"; + }; + + siul2: siul@4006c000 { + compatible = "fsl,s32v234-siul2"; + reg = <0x0 0x4006C000 0x0 0x1794>; + status = "disabled"; + }; + + src: src@4007c000 { + compatible = "fsl,s32v234-src"; + reg = <0x0 0x4007C000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + reg = <0x0 0x40080000 0x0 0x70000>; + ranges; + + uart1: serial@400bc000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x0 0x400bc000 0x0 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>; + clocks = <&clks S32V234_CLK_LIN>; + clock-names = "lin"; + status = "disabled"; + }; + + can1: flexcan@400be000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x400be000 0x0 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; |