diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts | 284 |
1 files changed, 284 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts new file mode 100644 index 000000000000..e1b9e53b354c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QM MEK inmate"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&fec1 { + /delete-property/ iommus; +}; + +&fec2 { + /delete-property/ iommus; +}; + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&usbotg3 { + /delete-property/ iommus; +}; + +&usbotg3_cdns3 { + /delete-property/ iommus; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; |