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-rw-r--r--arch/arm/common/Kconfig1
-rw-r--r--arch/arm/common/gic.c4
2 files changed, 1 insertions, 4 deletions
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index a3beda1213da..a11cee523cd4 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,5 +1,6 @@
config ARM_GIC
select IRQ_DOMAIN
+ select MULTI_IRQ_HANDLER
bool
config GIC_NON_BANKED
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 3c78b7c60691..a1feb6b4f9f5 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -71,9 +71,6 @@ struct gic_chip_data {
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
-/* Address of GIC 0 CPU interface */
-void __iomem *gic_cpu_base_addr __read_mostly;
-
/*
* Supported arch specific GIC irq extension.
* Default make them NULL.
@@ -700,7 +697,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
* For secondary GICs, skip over PPIs, too.
*/
if (gic_nr == 0) {
- gic_cpu_base_addr = cpu_base;
domain->hwirq_base = 16;
if (irq_start > 0)
irq_start = (irq_start & ~31) + 16;