diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6qp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qp.dtsi | 73 |
1 files changed, 52 insertions, 21 deletions
diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index d91f92f944c5..cd074d1b9b1f 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -5,6 +5,15 @@ #include "imx6q.dtsi" / { + aliases { + pre0 = &pre1; + pre1 = &pre2; + pre2 = &pre3; + pre3 = &pre4; + prg0 = &prg1; + prg1 = &prg2; + }; + soc { ocram2: sram@940000 { compatible = "mmio-sram"; @@ -20,57 +29,63 @@ aips-bus@2100000 { pre1: pre@21c8000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c8000 0x1000>; interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; clocks = <&clks IMX6QDL_CLK_PRE0>; clock-names = "axi"; - fsl,iram = <&ocram2>; + ocram = <&ocram2>; + status = "disabled"; }; pre2: pre@21c9000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c9000 0x1000>; interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>; clocks = <&clks IMX6QDL_CLK_PRE1>; clock-names = "axi"; - fsl,iram = <&ocram2>; + ocram = <&ocram2>; + status = "disabled"; }; pre3: pre@21ca000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021ca000 0x1000>; interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>; clocks = <&clks IMX6QDL_CLK_PRE2>; clock-names = "axi"; - fsl,iram = <&ocram3>; + ocram = <&ocram3>; + status = "disabled"; }; pre4: pre@21cb000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021cb000 0x1000>; interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>; clocks = <&clks IMX6QDL_CLK_PRE3>; clock-names = "axi"; - fsl,iram = <&ocram3>; + ocram = <&ocram3>; + status = "disabled"; }; prg1: prg@21cc000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cc000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; + clock-names = "apb", "axi"; + gpr = <&gpr>; + status = "disabled"; }; prg2: prg@21cd000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cd000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG1_APB>, <&clks IMX6QDL_CLK_PRG1_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre4>, <&pre2>, <&pre3>; + clock-names = "apb", "axi"; + gpr = <&gpr>; + status = "disabled"; }; }; }; @@ -87,22 +102,34 @@ &ipu1 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU1>, + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg1>; }; &ipu2 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg2>; }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb"; }; &mmdc0 { @@ -112,3 +139,7 @@ &pcie { compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; }; + +&pcie_ep { + compatible = "fsl,imx6qp-pcie-ep"; +}; |