diff options
-rw-r--r-- | arch/arm/mach-tegra/board-aruba-pinmux.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-aruba.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-tegra/devices.c | 28 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 4 | ||||
-rw-r--r-- | sound/arm/Makefile | 1 | ||||
-rw-r--r-- | sound/arm/tegra/Makefile | 29 | ||||
-rw-r--r-- | sound/arm/tegra/hda_tegra.c | 972 | ||||
-rw-r--r-- | sound/arm/tegra/patch_nvhdmi_tegra.c | 590 | ||||
-rw-r--r-- | sound/core/memalloc.c | 2 | ||||
-rw-r--r-- | sound/pci/Kconfig | 2 | ||||
-rw-r--r-- | sound/pci/hda/Kconfig | 4 | ||||
-rw-r--r-- | sound/pci/hda/Makefile | 2 | ||||
-rw-r--r-- | sound/pci/hda/hda_beep.c | 4 | ||||
-rw-r--r-- | sound/pci/hda/hda_codec.c | 2 | ||||
-rw-r--r-- | sound/pci/hda/hda_codec.h | 11 | ||||
-rw-r--r-- | sound/pci/hda/hda_intel.c | 1414 | ||||
-rw-r--r-- | sound/pci/hda/lib_hda_intel.c | 1411 | ||||
-rw-r--r-- | sound/pci/hda/lib_hda_intel.h | 621 | ||||
-rw-r--r-- | sound/pci/hda/patch_realtek.c | 14 | ||||
-rw-r--r-- | sound/soc/tegra/Kconfig | 16 |
20 files changed, 3711 insertions, 1427 deletions
diff --git a/arch/arm/mach-tegra/board-aruba-pinmux.c b/arch/arm/mach-tegra/board-aruba-pinmux.c index 069468b3ae00..3db2ede1eb1c 100644 --- a/arch/arm/mach-tegra/board-aruba-pinmux.c +++ b/arch/arm/mach-tegra/board-aruba-pinmux.c @@ -246,11 +246,19 @@ static __initdata struct tegra_pingroup_config aruba_pinmux[] = { DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), +#ifdef CONFIG_SND_HDA_TEGRA + DEFAULT_PINMUX(DAP1_FS, HDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, HDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, HDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, HDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ, DAP1, NORMAL, NORMAL, INPUT), +#else DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), +#endif DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), diff --git a/arch/arm/mach-tegra/board-aruba.c b/arch/arm/mach-tegra/board-aruba.c index b9559b652377..cfe990f41033 100644 --- a/arch/arm/mach-tegra/board-aruba.c +++ b/arch/arm/mach-tegra/board-aruba.c @@ -359,6 +359,9 @@ static struct platform_device *aruba_devices[] __initdata = { #endif &aruba_keys_device, &tegra_wdt_device, +#if defined(CONFIG_SND_HDA_TEGRA) + &tegra_hda_device, +#endif &tegra_avp_device, }; diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index 4f86a47f613f..c29755dc0530 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -583,25 +583,33 @@ struct platform_device tegra_audio_device = { .resource = audio_resource, .num_resources = ARRAY_SIZE(audio_resource), }; +#endif + +#if defined(CONFIG_SND_HDA_TEGRA) +static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32); -static struct resource hda_resource[] = { +static struct resource tegra_hda_resources[] = { [0] = { + .start = TEGRA_HDA_BASE, + .end = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1 , + .flags = IORESOURCE_MEM + }, + [1] = { .start = INT_HDA, .end = INT_HDA, .flags = IORESOURCE_IRQ }, - [1] = { - .start = TEGRA_HDA_BASE, - .end = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1, - .flags = IORESOURCE_MEM - } }; struct platform_device tegra_hda_device = { - .name = "hda", - .id = -1, - .resource = hda_resource, - .num_resources = ARRAY_SIZE(hda_resource), + .name = "tegra-hda", + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .dma_mask = &tegra_hda_dma_mask, + }, + .resource = tegra_hda_resources, + .num_resources = ARRAY_SIZE(tegra_hda_resources), }; #endif diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 7ee8b0193282..673b490356ce 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -2532,8 +2532,8 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("dam0", "dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam1", "dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam2", "dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), - PERIPH_CLK("hda2codec", "hda2codec", NULL, 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("hda", "hda", NULL, 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("hda", "hda", NULL, 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("hda2codec_2x", "hda2codec_2x", NULL, 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_2), PERIPH_CLK("hda2hdmi", "hda2hdmi", NULL, 128, 0, 48000000, mux_clk_m, 0), PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), diff --git a/sound/arm/Makefile b/sound/arm/Makefile index 8c0c851d4641..55c7646f4b09 100644 --- a/sound/arm/Makefile +++ b/sound/arm/Makefile @@ -2,6 +2,7 @@ # Makefile for ALSA # +obj-$(CONFIG_SND_HDA_TEGRA) += tegra/ obj-$(CONFIG_SND_ARMAACI) += snd-aaci.o snd-aaci-objs := aaci.o diff --git a/sound/arm/tegra/Makefile b/sound/arm/tegra/Makefile new file mode 100644 index 000000000000..7c44d09c4e63 --- /dev/null +++ b/sound/arm/tegra/Makefile @@ -0,0 +1,29 @@ +#EXTRA_CFLAGS += -DSND_HDA_TEGRA + +snd-hda-tegra-objs := ../../pci/hda/lib_hda_intel.o hda_tegra.o + +snd-hda-codec-y := ../../pci/hda/hda_codec.o +snd-hda-codec-$(CONFIG_SND_HDA_GENERIC) += ../../pci/hda/hda_generic.o +snd-hda-codec-$(CONFIG_SND_HDA_HWDEP) += ../../pci/hda/hda_hwdep.o +snd-hda-codec-$(CONFIG_SND_HDA_INPUT_BEEP) += ../../pci/hda/hda_beep.o +snd-hda-codec-$(CONFIG_PROC_FS) += ../../pci/hda/hda_proc.o + +snd-hda-codec-nvhdmi-objs := patch_nvhdmi_tegra.o +snd-hda-codec-realtek-objs := ../../pci/hda/patch_realtek.o + + +# common driver +obj-$(CONFIG_SND_HDA_TEGRA) := snd-hda-codec.o + +# codec drivers (note: CONFIG_SND_HDA_CODEC_XXX are booleans) +ifdef CONFIG_SND_HDA_CODEC_NVHDMI +#obj-$(CONFIG_SND_HDA_TEGRA) += snd-hda-codec-nvhdmi.o +endif +ifdef CONFIG_SND_HDA_CODEC_REALTEK +obj-$(CONFIG_SND_HDA_TEGRA) += snd-hda-codec-realtek.o +endif + +# this must be the last entry after codec drivers; +# otherwise the codec patches won't be hooked before the PCI probe +# when built in kernel +obj-$(CONFIG_SND_HDA_TEGRA) += snd-hda-tegra.o diff --git a/sound/arm/tegra/hda_tegra.c b/sound/arm/tegra/hda_tegra.c new file mode 100644 index 000000000000..9bbda282a634 --- /dev/null +++ b/sound/arm/tegra/hda_tegra.c @@ -0,0 +1,972 @@ +/* + * + * hda_tegra.c - Implementation of primary alsa driver code base + * for T30 HD Audio. + * + * Copyright(c) 2004 Intel Corporation. All rights reserved. + * + * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> + * PeiSen Hou <pshou@realtek.com.tw> + * Copyright (C) 2010 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * CONTACTS: + * + * Matt Jared matt.jared@intel.com + * Andy Kopp andy.kopp@intel.com + * Dan Kogan dan.d.kogan@intel.com + * + * CHANGES: + * + * 2004.12.01 Major rewrite by tiwai, merged the work of pshou + * + */ + +#include "../../pci/hda/hda_codec.h" +#include "../../pci/hda/lib_hda_intel.h" +#include <linux/clk.h> +#include <mach/clk.h> + +static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; +static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; +static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; +static char *model[SNDRV_CARDS]; +static int position_fix[SNDRV_CARDS]; +static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; +static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; +static int probe_only[SNDRV_CARDS]; +static int single_cmd; +static int enable_msi; + +/* Module clock info */ +static struct clk *clk_hda; +static struct clk *clk_hda2codec; + +#ifdef CONFIG_SND_HDA_PATCH_LOADER +static char *patch[SNDRV_CARDS]; +#endif +#ifdef CONFIG_SND_HDA_INPUT_BEEP +static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = + CONFIG_SND_HDA_INPUT_BEEP_MODE}; +#endif + +module_param_array(index, int, NULL, 0444); +MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); +module_param_array(id, charp, NULL, 0444); +MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); +module_param_array(enable, bool, NULL, 0444); +MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); +module_param_array(model, charp, NULL, 0444); +MODULE_PARM_DESC(model, "Use the given board model."); +module_param_array(position_fix, int, NULL, 0444); +MODULE_PARM_DESC(position_fix, "Fix DMA pointer " + "(0 = auto, 1 = none, 2 = POSBUF)."); +module_param_array(bdl_pos_adj, int, NULL, 0644); +MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); +module_param_array(probe_mask, int, NULL, 0444); +MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); +module_param_array(probe_only, int, NULL, 0444); +MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); +module_param(single_cmd, bool, 0444); +MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " + "(for debugging only)."); +module_param(enable_msi, int, 0444); +MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); +#ifdef CONFIG_SND_HDA_PATCH_LOADER +module_param_array(patch, charp, NULL, 0444); +MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); +#endif +#ifdef CONFIG_SND_HDA_INPUT_BEEP +module_param_array(beep_mode, int, NULL, 0444); +MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " + "(0=off, 1=on, 2=mute switch on/off) (default=1)."); +#endif + +#ifdef CONFIG_SND_HDA_POWER_SAVE +static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; +module_param(power_save, int, 0644); +MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " + "(in second, 0 = disable)."); + +/* reset the HD-audio controller in power save mode. + * this may give more power-saving, but will take longer time to + * wake up. + */ +static int power_save_controller = 1; +module_param(power_save_controller, bool, 0644); +MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); +#endif + +#define T30SFX "hda-tegra: " + +#define TEGRA_HDA_BAR0_OFFSET 0x8000 +#define TEGRA_HDA_BAR0_SIZE 0x4000 +#define TEGRA_HDA_CONFIG_OFFSET 0x1000 +#define TEGRA_HDA_CONFIG_SIZE 0x1000 + +#define NV_TEGRA_HDA_CFG_CMD_OFFSET 0x04 +#define NV_TEGRA_HDA_CFG_BAR0_OFFSET 0x10 + +#define NV_TEGRA_HDA_ENABLE_IO_SPACE (1 << 0) +#define NV_TEGRA_HDA_ENABLE_MEM_SPACE (1 << 1) +#define NV_TEGRA_HDA_ENABLE_BUS_MASTER (1 << 2) +#define NV_TEGRA_HDA_ENABLE_SERR (1 << 8) +#define NV_TEGRA_HDA_DISABLE_INTR (1 << 10) +#define NV_TEGRA_HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF +#define NV_TEGRA_HDA_BAR0_FINAL_PROGRAM (1 << 14) + +#define CLK_RST_HDA2CODEC (1<<15) +#define CLK_RST_HDA (1<<29) + +/* Define core/link clocks */ +#define NV_TEGRA_HDA_CORE_CLOCK_FREQ_KHZ (108*1000) +#define NV_TEGRA_HDA_LINK_CLOCK_FREQ_KHZ (48*1000) + +/* IPFS */ +#define IPFS_EN_FPCI 0x1 +#define IPFS_HDA_CONFIGURATION_0 0x180 +#define IPFS_HDA_FPCI_BAR0 0x80 +#define IPFS_HDA_INTR_MASK 0x188 +#define FPCI_BAR0_START 0x40 + +#define TEGRA_HDA_CONFIG_OFFSET 0x1000 + +#define TIMEOUT_CODEC 50 + +static u32 alc269_verb_table[] = { + /* HDA Codec Subsystem ID Verb-table */ + /* HDA Codec Subsystem ID : 0x00000000 */ + 0x10172000, 0x10172100, 0x10172200, 0x10172300, + /* Pin Widget Verb-table */ + /* Pin Complex (NID 0x12 )*/ + 0x11271CF0, 0x11271D01, 0x11271ED3, 0x11271F01, + /* Pin Complex (NID 0x14 ) */ + 0x11471CF0, 0x11471D01, 0x11471E11, 0x11471F90, + /* Pin Complex (NID 0x21 ) */ + 0x12171CF0, 0x12171D01, 0x12171E11, 0x12171F40, + /* Pin Complex (NID 0x17 ) */ + 0x11771CF0, 0x11771D01, 0x11771E11, 0x11771F40, + /* Pin Complex (NID 0x18 ) */ + 0x11871CF0, 0x11871D91, 0x11871EA1, 0x11871F01, + /* Pin Complex (NID 0x19 ) */ + 0x11971CF0, 0x11971D01, 0x11971E13, 0x11971F90, + /* Pin Complex (NID 0x1A ) */ + 0x11A71CF0, 0x11A71D41, 0x11A71E01, 0x11A71F01, + /* Pin Complex (NID 0x1B ) */ + 0x11B71CF0, 0x11B71D31, 0x11B71E81, 0x11B71F01, + /* Pin Complex (NID 0x1D ) */ + 0x11D71CF0, 0x11D71D01, 0x11D71E83, 0x11D71F40, + /* Pin Complex (NID 0x1E ) */ + 0x11E71CF0, 0x11E71D11, 0x11E71E45, 0x11E71F01, + /* Pin Complex (NID 0x20 ) */ + 0x12050011, 0x12040010, 0x12050012, 0x12041901, + /* Pin Complex (NID 0x20 ) - 1 */ + 0x12050002, 0x1204AAB8, 0x12050002, 0x1204AAB8, + /* Pin Complex (NID 0x20 ) - 2 */ + 0x1205000F, 0x1204B60B, 0x1205000F, 0x1204B60B, + /* Pin Complex (NID 0x20 ) - 3 */ + 0x12050007, 0x120400C0, 0x12050007, 0x120400C0, + /* Pin Complex (NID 0x20 ) - 4 */ + 0x12050008, 0x12040300, 0x12050008, 0x12040300, +}; + + +/* + * Interface for HD codec + */ + +/* + * CORB / RIRB interface + */ +static int azx_alloc_cmd_io(struct azx *chip) +{ + int err; + /* single page (at least 4096 bytes) must suffice for both ringbuffes */ + err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, + &chip->pdev->dev, + PAGE_SIZE , &chip->rb); + if (err < 0) { + snd_printk(KERN_ERR T30SFX "cannot allocate CORB/RIRB\n"); + return err; + } + return 0; +} + +static struct snd_pcm_ops azx_pcm_ops = { + .open = azx_pcm_open, + .close = azx_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = azx_pcm_hw_params, + .hw_free = azx_pcm_hw_free, + .prepare = azx_pcm_prepare, + .trigger = azx_pcm_trigger, + .pointer = azx_pcm_pointer, + .page = snd_pcm_sgbuf_ops_page, +}; + + +/* + * set up BDL entries + */ +int azx_setup_periods(struct azx *chip, + struct snd_pcm_substream *substream, + struct azx_dev *azx_dev) +{ + u32 *bdl; + int i, ofs, periods, period_bytes; + int pos_adj; + + /* reset BDL address */ + azx_sd_writel(azx_dev, SD_BDLPL, 0); + azx_sd_writel(azx_dev, SD_BDLPU, 0); + + period_bytes = azx_dev->period_bytes; + periods = azx_dev->bufsize / period_bytes; + + /* program the initial BDL entries */ + bdl = (u32 *)azx_dev->bdl.area; + ofs = 0; + azx_dev->frags = 0; + pos_adj = bdl_pos_adj[chip->dev_index]; + if (pos_adj > 0) { + struct snd_pcm_runtime *runtime = substream->runtime; + int pos_align = pos_adj; + pos_adj = (pos_adj * runtime->rate + 47999) / 48000; + if (!pos_adj) + pos_adj = pos_align; + else + pos_adj = ((pos_adj + pos_align - 1) / pos_align) * + pos_align; + pos_adj = frames_to_bytes(runtime, pos_adj); + if (pos_adj >= period_bytes) { + snd_printk(KERN_WARNING SFX "Too big adjustment %d\n", + bdl_pos_adj[chip->dev_index]); + pos_adj = 0; + } else { + ofs = setup_bdle(substream, azx_dev, + &bdl, ofs, pos_adj, 1); + if (ofs < 0) + goto error; + } + } else + pos_adj = 0; + for (i = 0; i < periods; i++) { + if (i == periods - 1 && pos_adj) + ofs = setup_bdle(substream, azx_dev, &bdl, ofs, + period_bytes - pos_adj, 0); + else + ofs = setup_bdle(substream, azx_dev, &bdl, ofs, + period_bytes, 1); + if (ofs < 0) + goto error; + } + return 0; + + error: + snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n", + azx_dev->bufsize, period_bytes); + return -EINVAL; +} + + +static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, + struct hda_pcm *cpcm); + /* + * Codec initialization + */ + +static int __devinit azx_codec_create(struct azx *chip, const char *model) +{ + struct hda_bus_template bus_temp; + int c, codecs, err; + int max_slots; + + memset(&bus_temp, 0, sizeof(bus_temp)); + bus_temp.private_data = chip; + bus_temp.modelname = model; + bus_temp.pdev = chip->pdev; + bus_temp.ops.command = azx_send_cmd; + bus_temp.ops.get_response = azx_get_response; + bus_temp.ops.attach_pcm = azx_attach_pcm_stream; + bus_temp.ops.bus_reset = azx_bus_reset; +#ifdef CONFIG_SND_HDA_POWER_SAVE + bus_temp.power_save = &power_save; + bus_temp.ops.pm_notify = azx_power_notify; +#endif + + err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); + if (err < 0) + return err; + + if (chip->driver_type == AZX_DRIVER_NVIDIA) + chip->bus->needs_damn_long_delay = 1; + + codecs = 0; + max_slots = AZX_DEFAULT_CODECS; + + /* First try to probe all given codec slots */ + for (c = 0; c < max_slots; c++) { + if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { + if (probe_codec(chip, c) < 0) { + /* Some BIOSen give you wrong codec addresses + * that don't exist + */ + snd_printk(KERN_WARNING T30SFX + "Codec #%d probe error; " + "disabling it...\n", c); + chip->codec_mask &= ~(1 << c); + /* More badly, accessing to a non-existing + * codec often screws up the controller chip, + * and disturbs the further communications. + * Thus if an error occurs during probing, + * better to reset the controller chip to + * get back to the sanity state. + */ + azx_stop_chip(chip); + azx_init_chip(chip, 1); + } + } + } + + /* Then create codec instances */ + for (c = 0; c < max_slots; c++) { + if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { + struct hda_codec *codec; + err = snd_hda_codec_new(chip->bus, c, &codec); + if (err < 0) + continue; + codec->beep_mode = chip->beep_mode; + codecs++; + } + } + if (!codecs) { + snd_printk(KERN_ERR T30SFX "no codecs initialized\n"); + return -ENXIO; + } + return 0; +} +/* + * Check whether the current DMA position is acceptable for updating + * periods. Returns non-zero if it's OK. + * + * Many HD-audio controllers appear pretty inaccurate about + * the update-IRQ timing. The IRQ is issued before actually the + * data is processed. So, we need to process it afterwords in a + * workqueue. + */ +int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) +{ + u32 wallclk; + unsigned int pos; + int stream; + + wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; + if (wallclk < (azx_dev->period_wallclk * 2) / 3) + return -1; /* bogus (too early) interrupt */ + + stream = azx_dev->substream->stream; + pos = azx_get_position(chip, azx_dev); + if (chip->position_fix[stream] == POS_FIX_AUTO) { + if (!pos) { + printk(KERN_WARNING + "hda-intel: Invalid position buffer, " + "using LPIB read method instead.\n"); + chip->position_fix[stream] = POS_FIX_LPIB; + pos = azx_get_position(chip, azx_dev); + } else + chip->position_fix[stream] = POS_FIX_POSBUF; + } + + if (WARN_ONCE(!azx_dev->period_bytes, + "hda-intel: zero azx_dev->period_bytes")) + return -1; /* this shouldn't happen! */ + if (wallclk < (azx_dev->period_wallclk * 5) / 4 && + pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) + /* NG - it's below the first next period boundary */ + return bdl_pos_adj[chip->dev_index] ? 0 : -1; + azx_dev->start_wallclk += wallclk; + return 1; /* OK, it's fine */ +} +static int +azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, + struct hda_pcm *cpcm) +{ + struct azx *chip = bus->private_data; + struct snd_pcm *pcm; + struct azx_pcm *apcm; + int pcm_dev = cpcm->device; + int s, err; + + if (pcm_dev >= HDA_MAX_PCMS) { + snd_printk(KERN_ERR T30SFX "Invalid PCM device number %d\n", + pcm_dev); + return -EINVAL; + } + if (chip->pcm[pcm_dev]) { + snd_printk(KERN_ERR T30SFX "PCM %d already exists\n", pcm_dev); + return -EBUSY; + } + err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, + cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, + cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, + &pcm); + if (err < 0) + return err; + strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); + apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); + if (apcm == NULL) + return -ENOMEM; + apcm->chip = chip; + apcm->codec = codec; + pcm->private_data = apcm; + pcm->private_free = azx_pcm_free; + if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) + pcm->dev_class = SNDRV_PCM_CLASS_MODEM; + chip->pcm[pcm_dev] = pcm; + cpcm->pcm = pcm; + for (s = 0; s < 2; s++) { + apcm->hinfo[s] = &cpcm->stream[s]; + if (cpcm->stream[s].substreams) + snd_pcm_set_ops(pcm, s, &azx_pcm_ops); + } + /* buffer pre-allocation */ + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, + &chip->pdev->dev, + 1024 * 64, 32 * 1024 * 1024); + return 0; +} + + + +#ifdef CONFIG_PM +/* + * power management + */ +static int nv_tegra_hda_controller_suspend(struct platform_device *pdev) +{ +#if 0 + struct snd_card *card = dev_get_drvdata(&pdev->dev); + struct azx *chip = card->private_data; + clk_disable(chip->clk); +#endif + return 0; +} + +static int nv_tegra_hda_controller_resume(struct platform_device *pdev) +{ +#if 0 + struct snd_card *card = dev_get_drvdata(&pdev->dev); + struct azx *chip = card->private_data; + clk_enable(chip->clk); +#endif + return 0; +} + +static int nv_tegra_azx_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct snd_card *card = dev_get_drvdata(&pdev->dev); + struct azx *chip = card->private_data; + int i; + + snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); + azx_clear_irq_pending(chip); + for (i = 0; i < HDA_MAX_PCMS; i++) + snd_pcm_suspend_all(chip->pcm[i]); + if (chip->initialized) + snd_hda_suspend(chip->bus); + azx_stop_chip(chip); + if (chip->irq >= 0) { + free_irq(chip->irq, chip); + chip->irq = -1; + } + + return nv_tegra_hda_controller_suspend(pdev); +} + +static int nv_tegra_azx_resume(struct platform_device *pdev) +{ + struct snd_card *card = dev_get_drvdata(&pdev->dev); + struct azx *chip = card->private_data; + int rc; + + rc = nv_tegra_hda_controller_resume(pdev); + if (rc) + return rc; + + chip->msi = 0; + if (azx_acquire_irq(chip, 1) < 0) + return -EIO; + + if (snd_hda_codecs_inuse(chip->bus)) + azx_init_chip(chip, 1); + + snd_hda_resume(chip->bus); + snd_power_change_state(card, SNDRV_CTL_POWER_D0); + return 0; +} + +#endif /* CONFIG_PM */ + +/* + * destructor + */ +static int azx_free(struct azx *chip) +{ + int i; + + azx_notifier_unregister(chip); + + if (chip->initialized) { + azx_clear_irq_pending(chip); + for (i = 0; i < chip->num_streams; i++) + azx_stream_stop(chip, &chip->azx_dev[i]); + azx_stop_chip(chip); + } + + if (chip->irq >= 0) + free_irq(chip->irq, (void *)chip); + if (chip->remap_addr) + iounmap(chip->remap_addr); + + if (chip->azx_dev) { + for (i = 0; i < chip->num_streams; i++) + if (chip->azx_dev[i].bdl.area) + snd_dma_free_pages(&chip->azx_dev[i].bdl); + } + if (chip->rb.area) + snd_dma_free_pages(&chip->rb); + if (chip->posbuf.area) + snd_dma_free_pages(&chip->posbuf); + kfree(chip->azx_dev); + kfree(chip); + + return 0; +} + +static int azx_dev_free(struct snd_device *device) +{ + return azx_free(device->device_data); +} +static int __devinit check_position_fix(struct azx *chip, int fix) +{ + chip->via_dmapos_patch = 0; + return POS_FIX_AUTO; +} + +#define AZX_FORCE_CODEC_MASK 0x100 + +static void __devinit check_probe_mask(struct azx *chip, int dev) +{ + chip->codec_probe_mask = probe_mask[dev]; + + /* check forced option */ + if (chip->codec_probe_mask != -1 && + (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { + chip->codec_mask = chip->codec_probe_mask & 0xff; + printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", + chip->codec_mask); + } +} + +/* + * constructor + */ +static int __devinit azx_create(struct snd_card *card, + struct platform_device *pdev, + int dev, struct azx **rchip) +{ + struct azx *chip; + int i, err; + unsigned short gcap; + struct resource *res ; + static struct snd_device_ops ops = { + .dev_free = azx_dev_free, + }; + + *rchip = NULL; + + /* acquire resource.*/ + /* get mapped config*/ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -EINVAL; + chip = kzalloc(sizeof(*chip), GFP_KERNEL); + if (!chip) { + snd_printk(KERN_ERR T30SFX "cannot allocate chip\n"); + return -ENOMEM; + } + + spin_lock_init(&chip->reg_lock); + mutex_init(&chip->open_mutex); + chip->card = card; + chip->pdev = pdev; + chip->irq = -1; + chip->msi = 0; + chip->dev_index = dev; + INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); + + chip->position_fix[0] = chip->position_fix[1] = + check_position_fix(chip, position_fix[dev]); + check_probe_mask(chip, dev); + chip->single_cmd = single_cmd; + + if (bdl_pos_adj[dev] < 0) + bdl_pos_adj[dev] = 32; + chip->addr = res->start + TEGRA_HDA_BAR0_OFFSET ; + chip->remap_addr = devm_ioremap(&pdev->dev, res->start, + res->end - res->start + 1) + TEGRA_HDA_BAR0_OFFSET;; + chip->pciconfig_addr = devm_ioremap(&pdev->dev, res->start, + res->end - res->start + 1) + TEGRA_HDA_CONFIG_OFFSET ; + + if (chip->remap_addr == NULL) { + snd_printk(KERN_ERR T30SFX "ioremap error\n"); + err = -ENXIO; + goto errout; + } + + if (azx_acquire_irq(chip, 0) < 0) { + err = -EBUSY; + goto errout; + } + + synchronize_irq(chip->irq); + + gcap = azx_readw(chip, GCAP); + snd_printdd("chipset global capabilities = 0x%x\n", gcap); + + /* read number of streams from GCAP register instead of using + * hardcoded value + */ + chip->capture_streams = (gcap >> 8) & 0x0f; + chip->playback_streams = (gcap >> 12) & 0x0f; + /* read number of streams from GCAP register instead of using + * hardcoded value + */ + chip->capture_streams = (gcap >> 8) & 0x0f; + chip->playback_streams = (gcap >> 12) & 0x0f; + if (!chip->playback_streams && !chip->capture_streams) { + /* gcap didn't give any info, switching to old method */ + + chip->playback_streams = ICH6_NUM_PLAYBACK; + chip->capture_streams = ICH6_NUM_CAPTURE; + } + chip->capture_index_offset = 0; + chip->playback_index_offset = chip->capture_streams; + chip->num_streams = chip->playback_streams + chip->capture_streams; + chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), + GFP_KERNEL); + if (!chip->azx_dev) { + snd_printk(KERN_ERR "cannot malloc azx_dev\n"); + goto errout; + } + + for (i = 0; i < chip->num_streams; i++) { + /* allocate memory for the BDL for each stream */ + err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, + &chip->pdev->dev, + BDL_SIZE, &chip->azx_dev[i].bdl); + if (err < 0) { + snd_printk(KERN_ERR T30SFX "cannot allocate BDL\n"); + goto errout; + } + } + /* allocate memory for the position buffer */ + err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, + &chip->pdev->dev, + chip->num_streams * 8, &chip->posbuf); + if (err < 0) { + snd_printk(KERN_ERR T30SFX "cannot allocate posbuf\n"); + goto errout; + } + /* allocate CORB/RIRB */ + err = azx_alloc_cmd_io(chip); + if (err < 0) + goto errout; + + /* initialize streams */ + azx_init_stream(chip); + + /* initialize chip */ + azx_init_chip(chip, (probe_only[dev] & 2) == 0); + + /* codec detection */ + if (!chip->codec_mask) { + snd_printk(KERN_ERR T30SFX "no codecs found!\n"); + err = -ENODEV; + goto errout; + } + + err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); + if (err < 0) { + snd_printk(KERN_ERR T30SFX "Error creating device [card]!\n"); + goto errout; + } + + strcpy(card->driver, "HDA-Tegra"); + strcpy(card->shortname, "tegra-hda"); + sprintf(card->longname, "%s at 0x%lx irq %i", + card->shortname, chip->addr, chip->irq); + *rchip = chip; + return 0; + + errout: + azx_free(chip); + return err; +} + +static int nv_tegra_hda_controller_init(struct platform_device *pdev) +{ + void __iomem *mmio = NULL, *hda_config = NULL , *hda_reg = NULL ; + struct resource *regs; + u32 temp, intr_mask; + u16 codec_mask; + int err = 0, count, i; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!regs) + { + snd_printk(KERN_ERR T30SFX "no memory resource\n"); + return -ENOMEM; + } + + /* HDA Reg */ + hda_reg = devm_ioremap(&pdev->dev, regs->start, + regs->end - regs->start + 1); + + hda_config = hda_reg + TEGRA_HDA_CONFIG_OFFSET; + mmio = hda_reg + TEGRA_HDA_BAR0_OFFSET; + clk_hda = clk_get_sys("hda", NULL); + if (IS_ERR(clk_hda)) { + snd_printk(KERN_ERR T30SFX "%s: can't get hda clock\n", __func__); + return -1; + } + clk_hda2codec = clk_get_sys("hda2codec_2x", NULL); + if (IS_ERR(clk_hda2codec)) { + snd_printk(KERN_ERR T30SFX "%s: can't get hda clock\n", __func__); + return -1; + } + + clk_enable(clk_hda); + clk_enable(clk_hda2codec); + + /*Enable the PCI access */ + temp = readl(hda_reg + IPFS_HDA_CONFIGURATION_0); + temp |= IPFS_EN_FPCI; + writel(temp, (hda_reg + IPFS_HDA_CONFIGURATION_0)); + + /* Program config space registers */ + /* Enable MEM/IO space and bus master */ + temp = readl(hda_config + NV_TEGRA_HDA_CFG_CMD_OFFSET); + temp |= (NV_TEGRA_HDA_ENABLE_MEM_SPACE | NV_TEGRA_HDA_ENABLE_IO_SPACE | + NV_TEGRA_HDA_ENABLE_BUS_MASTER | NV_TEGRA_HDA_ENABLE_SERR); + temp &= (~NV_TEGRA_HDA_DISABLE_INTR); + writel(temp, hda_config + NV_TEGRA_HDA_CFG_CMD_OFFSET); + + /* program bar0 space */ + /* write 1's to bar0 register */ + writel(NV_TEGRA_HDA_BAR0_INIT_PROGRAM, + hda_config + NV_TEGRA_HDA_CFG_BAR0_OFFSET); + /* flush */ + temp = readl(hda_config + NV_TEGRA_HDA_CFG_BAR0_OFFSET); + writel(NV_TEGRA_HDA_BAR0_FINAL_PROGRAM, + hda_config + NV_TEGRA_HDA_CFG_BAR0_OFFSET); + /* flush */ + readl(hda_config + NV_TEGRA_HDA_CFG_BAR0_OFFSET); + + writel(FPCI_BAR0_START, ( hda_reg + IPFS_HDA_FPCI_BAR0) ); + intr_mask = readl((hda_reg+ IPFS_HDA_INTR_MASK)); + intr_mask &= ~(1 << 16) ; + intr_mask |= (1 << 16) ; + + writel(intr_mask, (hda_reg+ IPFS_HDA_INTR_MASK)); + /* Turn on the link by de-asserting the Controller Reset# bit */ + writel(readl(mmio + ICH6_REG_GCTL) | + ICH6_GCTL_RESET, mmio + ICH6_REG_GCTL); + count = TIMEOUT_CODEC; + while (!(readl(mmio + ICH6_REG_GCTL) & 0x0f) && --count) + msleep(1); + /* Clear STATESTS bits */ + writel(readl(mmio + ICH6_REG_WAKEEN) | (STATESTS_INT_MASK << 16), + mmio + ICH6_REG_WAKEEN); + /* Turn off the link by writing 0 to the Controller Reset# bit */ + writel(readl(mmio + ICH6_REG_GCTL) & + ~ICH6_GCTL_RESET, mmio + ICH6_REG_GCTL); + count = TIMEOUT_CODEC; + while ((readl(mmio + ICH6_REG_GCTL) & 0x0f) && --count) + msleep(1); + /* Turn on the Link again by writing 1 to the Controller Reset# bit */ + writel(readl(mmio + ICH6_REG_GCTL) | + ICH6_GCTL_RESET, mmio + ICH6_REG_GCTL); + count = TIMEOUT_CODEC; + while (!(readl(mmio + ICH6_REG_GCTL) & 0x0f) && --count) + msleep(1); + /* Get the codec mask */ + codec_mask = (readl(mmio + ICH6_REG_WAKEEN) & + (STATESTS_INT_MASK << 16)) >> 16; + if (!codec_mask) + snd_printk(KERN_ERR T30SFX "preinit: no codecs found!\n"); + /* Load Realtek ALC269 verbs table */ + for (i = 0; i < sizeof(alc269_verb_table); i++) { + count = TIMEOUT_CODEC; + while (count--) { + /* check ICB busy bit */ + if (!((readl(mmio + ICH6_REG_IRS) & ICH6_IRS_BUSY))) { + /* Clear IRV valid bit */ + writel(readl(mmio + ICH6_REG_IRS) | + ICH6_IRS_VALID, mmio + ICH6_REG_IRS); + writel(alc269_verb_table[i], + mmio + ICH6_REG_IC); + writel(readl(mmio + ICH6_REG_IRS) | + ICH6_IRS_BUSY, mmio + ICH6_REG_IRS); + break; + } + udelay(1); + if (!count) { + snd_printk(KERN_ERR T30SFX "preinit: send verb \ + table timeout!\n"); + goto fail; + } + } + } + + /* unmap the resources we mapped above */ + if (hda_reg) + devm_iounmap(&pdev->dev, hda_reg); + return 0; +fail: + /* unmap the resources we mapped above */ + if (hda_reg) + devm_iounmap(&pdev->dev, hda_reg); + return err; +} + +static int __devinit nv_tegra_azx_probe(struct platform_device *pdev) +{ + static int dev; + struct snd_card *card; + struct azx *chip; + int err; + + if (dev >= SNDRV_CARDS) + return -ENODEV; + if (!enable[dev]) { + dev++; + return -ENOENT; + } + /* Call tegra init routine */ + err = nv_tegra_hda_controller_init(pdev); + + if (err != 0) { + dev_printk(KERN_ERR, &pdev->dev, "NV TEGRA HDA init failed\n"); + return err; + } + + err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); + if (err < 0) { + snd_printk(KERN_ERR T30SFX "Error creating card!\n"); + return err; + } + + /* set this here since it's referred in snd_hda_load_patch() */ + snd_card_set_dev(card, &pdev->dev); + + err = azx_create(card, pdev, dev, &chip); + if (err < 0) + goto out_free; + card->private_data = chip; + +#ifdef CONFIG_SND_HDA_INPUT_BEEP + chip->beep_mode = beep_mode[dev]; +#endif + /* create codec instances */ + err = azx_codec_create(chip, model[dev]); + if (err < 0) + goto out_free; +#ifdef CONFIG_SND_HDA_PATCH_LOADER + if (patch[dev]) { + snd_printk(KERN_ERR T30SFX "Applying patch firmware '%s'\n", + patch[dev]); + err = snd_hda_load_patch(chip->bus, patch[dev]); + if (err < 0) + goto out_free; + } +#endif + if ((probe_only[dev] & 1) == 0) { + err = azx_codec_configure(chip); + if (err < 0) + goto out_free; + } + + /* create PCM streams */ + err = snd_hda_build_pcms(chip->bus); + if (err < 0) + goto out_free; + + /* create mixer controls */ + err = azx_mixer_create(chip); + if (err < 0) + goto out_free; + + err = snd_card_register(card); + if (err < 0) + goto out_free; + + dev_set_drvdata(&pdev->dev, card); + chip->running = 1; + power_down_all_codecs(chip); + azx_notifier_register(chip); + + dev++; + return err; +out_free: + snd_card_free(card); + return err; +} + +static int __devexit nv_tegra_azx_remove(struct platform_device *pdev) +{ + snd_card_free(dev_get_drvdata(&pdev->dev)); + dev_set_drvdata(&pdev->dev, NULL); + return 0; +} + +/* platform_driver definition */ +static struct platform_driver tegra_platform_hda_driver = { + .driver = { + .name = "tegra-hda", + }, + .probe = nv_tegra_azx_probe, + .remove = __devexit_p(nv_tegra_azx_remove), +#ifdef CONFIG_PM + .suspend = nv_tegra_azx_suspend, + .resume = nv_tegra_azx_resume, +#endif +}; + +static int __init alsa_card_azx_init(void) +{ + return platform_driver_register(&tegra_platform_hda_driver); +} + +static void __exit alsa_card_azx_exit(void) +{ + platform_driver_unregister(&tegra_platform_hda_driver); +} + +module_init(alsa_card_azx_init) +module_exit(alsa_card_azx_exit) diff --git a/sound/arm/tegra/patch_nvhdmi_tegra.c b/sound/arm/tegra/patch_nvhdmi_tegra.c new file mode 100644 index 000000000000..be776e0949ac --- /dev/null +++ b/sound/arm/tegra/patch_nvhdmi_tegra.c @@ -0,0 +1,590 @@ +/* + * Universal Interface for Intel High Definition Audio Codec + * + * HD audio interface patch for NVIDIA HDMI codecs + * + * Copyright (c) 2010 NVIDIA Corp. All rights reserved. + * Copyright (c) 2010 Wei Ni <wni@nvidia.com> + * + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <sound/core.h> +#include "../../pci/hda/hda_codec.h" +#include "../../pci/hda/hda_local.h" + +struct hdmi_audio_infoframe { + u8 type; /* 0x84 */ + u8 ver; /* 0x01 */ + u8 len; /* 0x0a */ + + u8 checksum; /* PB0 */ + u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ + u8 SS01_SF24; + u8 CXT04; + u8 CA; + u8 LFEPBL01_LSV36_DM_INH7; +}; + +/* + * CEA speaker placement: + * + * FLH FCH FRH + * FLW FL FLC FC FRC FR FRW + * + * LFE + * TC + * + * RL RLC RC RRC RR + * + * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to + * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC. + */ +enum cea_speaker_placement { + FL = (1 << 0), /* Front Left */ + FC = (1 << 1), /* Front Center */ + FR = (1 << 2), /* Front Right */ + FLC = (1 << 3), /* Front Left Center */ + FRC = (1 << 4), /* Front Right Center */ + RL = (1 << 5), /* Rear Left */ + RC = (1 << 6), /* Rear Center */ + RR = (1 << 7), /* Rear Right */ + RLC = (1 << 8), /* Rear Left Center */ + RRC = (1 << 9), /* Rear Right Center */ + LFE = (1 << 10), /* Low Frequency Effect */ + FLW = (1 << 11), /* Front Left Wide */ + FRW = (1 << 12), /* Front Right Wide */ + FLH = (1 << 13), /* Front Left High */ + FCH = (1 << 14), /* Front Center High */ + FRH = (1 << 15), /* Front Right High */ + TC = (1 << 16), /* Top Center */ +}; + +struct cea_channel_speaker_allocation { + int ca_index; + int speakers[8]; + + /* derived values, just for convenience */ + int channels; + int spk_mask; +}; + +/* + * ALSA sequence is: + * + * surround40 surround41 surround50 surround51 surround71 + * ch0 front left = = = = + * ch1 front right = = = = + * ch2 rear left = = = = + * ch3 rear right = = = = + * ch4 LFE center center center + * ch5 LFE LFE + * ch6 side left + * ch7 side right + * + * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR} + */ +static int hdmi_channel_mapping[0x32][8] = { + /* stereo */ + [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, + /* 2.1 */ + [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, + /* Dolby Surround */ + [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 }, + /* surround40 */ + [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, + /* 4ch */ + [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, + /* surround41 */ + [0x09] = { 0x00, 0x11, 0x24, 0x34, 0x43, 0xf2, 0xf6, 0xf7 }, + /* surround50 */ + [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, + /* surround51 */ + [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, + /* 7.1 */ + [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 }, +}; + +/* + * This is an ordered list! + * + * The preceding ones have better chances to be selected by + * hdmi_setup_channel_allocation(). + */ +static struct cea_channel_speaker_allocation channel_allocations[] = { +/* channel: 7 6 5 4 3 2 1 0 */ +{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, + /* 2.1 */ +{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, + /* Dolby Surround */ +{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, + /* surround40 */ +{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, + /* surround41 */ +{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, + /* surround50 */ +{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, + /* surround51 */ +{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, + /* 6.1 */ +{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, + /* surround71 */ +{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, + +{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, +{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, +{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, +{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, +{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, +{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, +{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, +{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, +{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, +{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, +{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, +{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, +{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, +{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, +}; + +struct nvhdmi_spec { + struct hda_multi_out multiout; + struct hda_pcm pcm_rec; + /* + * HDMI sink attached to each pin + */ + struct hdmi_eld sink_eld[1]; + unsigned int codec_type; +}; + +#define AC_DIPXMIT_DISABLE (0x0<<6) +#define AC_DIPXMIT_BEST (0x3<<6) + +#define MAX_CHANNEL_MAPPING 0x08 + +#define AC_VERB_SET_CVT_CHAN_COUNT 0x72d +#define AC_VERB_SET_HDMI_DIP_INDEX 0x730 +#define AC_VERB_SET_HDMI_DIP_DATA 0x731 +#define AC_VERB_SET_HDMI_DIP_XMIT 0x732 +#define AC_VERB_SET_HDMI_CHAN_SLOT 0x734 + +#define Nv_VERB_SET_Audio_Protection_On 0xF98 + +#define Nv_Master_Convert_nid 0x04 +#define Nv_Master_Pin_nid 0x05 + +static struct hda_verb nvhdmi_basic_init_tegra[] = { + /* enable digital output on pin widget */ + { 0x5, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE}, + { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT}, + {} /* terminator */ +}; + +static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, + int packet_index, int byte_index) +{ + int val; + val = (packet_index << 5) | (byte_index & 0x1f); + snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); +} + +static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, + unsigned char val) +{ + snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); +} + +/* + * Enable Audio InfoFrame Transmission + */ +static void hdmi_start_infoframe_trans(struct hda_codec *codec, + hda_nid_t pin_nid) +{ + hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); + snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, + AC_DIPXMIT_BEST); +} + +/* + * Disable Audio InfoFrame Transmission + */ +static void hdmi_stop_infoframe_trans(struct hda_codec *codec, + hda_nid_t pin_nid) +{ + hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); + snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, + AC_DIPXMIT_DISABLE); +} + +static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid) +{ + return 1 + snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_CVT_CHAN_COUNT, 0); +} + +static void hdmi_set_channel_count(struct hda_codec *codec, + hda_nid_t nid, int chs) +{ + if (chs != hdmi_get_channel_count(codec, nid)) + snd_hda_codec_write(codec, nid, 0, + AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); +} + +static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *ai) +{ + ai->checksum = 0; +} + +static void hdmi_fill_audio_infoframe(struct hda_codec *codec, + hda_nid_t pin_nid, + struct hdmi_audio_infoframe *ai) +{ + u8 *bytes = (u8 *)ai; + int i; + + hdmi_checksum_audio_infoframe(ai); + hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); + for (i = 0; i < sizeof(*ai); i++) + hdmi_write_dip_byte(codec, pin_nid, bytes[i]); +} + +/* + * Compute derived values in channel_allocations[]. + */ +static void init_channel_allocations(void) +{ + int i, j; + struct cea_channel_speaker_allocation *p; + + for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { + p = channel_allocations + i; + p->channels = 0; + p->spk_mask = 0; + for (j = 0; j < ARRAY_SIZE(p->speakers); j++) + if (p->speakers[j]) { + p->channels++; + p->spk_mask |= p->speakers[j]; + } + } +} + +/* + * The transformation takes two steps: + * + * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask + * spk_mask => (channel_allocations[]) => ai->CA + * + * TODO: it could select the wrong CA from multiple candidates. +*/ +static int hdmi_setup_channel_allocation(struct hda_codec *codec, hda_nid_t nid, + struct hdmi_audio_infoframe *ai) +{ + int channels = 1 + (ai->CC02_CT47 & 0x7); + + switch (channels) { + default: + case 0: + case 2: + ai->CA = channel_allocations[0].ca_index; + break; + case 4: + ai->CA = channel_allocations[3].ca_index; + break; + case 6: + ai->CA = channel_allocations[6].ca_index; + break; + case 8: + ai->CA = channel_allocations[8].ca_index; + break; + } + return ai->CA; +} + +static void hdmi_setup_channel_mapping(struct hda_codec *codec, hda_nid_t nid, + struct hdmi_audio_infoframe *ai) +{ + int i; + int ca = ai->CA; + int err; + + if (hdmi_channel_mapping[ca][1] == 0) { + for (i = 0; i < channel_allocations[ca].channels; i++) + hdmi_channel_mapping[ca][i] = i | (i << 4); + for (; i < MAX_CHANNEL_MAPPING; i++) + hdmi_channel_mapping[ca][i] = 0xf | (i << 4); + } + + for (i = 0; i < 8; i++) { + err = snd_hda_codec_write(codec, nid, 0, + AC_VERB_SET_HDMI_CHAN_SLOT, + hdmi_channel_mapping[ca][i]); + if (err) { + snd_printdd(KERN_INFO "HDMI: channel mapping failed\n"); + break; + } + } +} + +static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, + struct hdmi_audio_infoframe *ai) +{ + u8 *bytes = (u8 *)ai; + u8 val; + int i; + + if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) + != AC_DIPXMIT_BEST) + return false; + + hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); + for (i = 0; i < sizeof(*ai); i++) { + val = snd_hda_codec_read(codec, pin_nid, 0, + AC_VERB_GET_HDMI_DIP_DATA, 0); + if (val != bytes[i]) + return false; + } + + return true; +} + +static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid, + struct snd_pcm_substream *substream) +{ + hda_nid_t pin_nid; + struct hdmi_audio_infoframe ai = { + .type = 0x84, + .ver = 0x01, + .len = 0x0a, + .CC02_CT47 = substream->runtime->channels - 1, + }; + + hdmi_setup_channel_allocation(codec, nid, &ai); + + pin_nid = Nv_Master_Pin_nid; + hdmi_setup_channel_mapping(codec, pin_nid, &ai); + + if (!hdmi_infoframe_uptodate(codec, pin_nid, &ai)) { + hdmi_stop_infoframe_trans(codec, pin_nid); + hdmi_fill_audio_infoframe(codec, pin_nid, &ai); + hdmi_start_infoframe_trans(codec, pin_nid); + } +} + +/* + * Callbacks + */ + +static void hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid, + u32 stream_tag, int format) +{ + int tag; + int fmt; + + tag = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0) >> 4; + fmt = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_STREAM_FORMAT, 0); + + snd_printdd("hdmi_setup_stream: " + "NID=0x%x, %sstream=0x%x, %sformat=0x%x\n", + nid, + tag == stream_tag ? "" : "new-", + stream_tag, + fmt == format ? "" : "new-", + format); + if (tag != stream_tag) + snd_hda_codec_write(codec, nid, 0, + AC_VERB_SET_CHANNEL_STREAMID, stream_tag << 4); + if (fmt != format) + snd_hda_codec_write(codec, nid, 0, + AC_VERB_SET_STREAM_FORMAT, format); +} + +/* + * Controls + */ +static int nvhdmi_build_controls(struct hda_codec *codec) +{ + struct nvhdmi_spec *spec = codec->spec; + int err; + + err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid); + if (err < 0) + return err; + + return 0; +} + +static int nvhdmi_init(struct hda_codec *codec) +{ + snd_hda_sequence_write(codec, nvhdmi_basic_init_tegra); + return 0; +} + +/* + * Digital out + */ +static int nvhdmi_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, + struct hda_codec *codec, + struct snd_pcm_substream *substream) +{ + struct nvhdmi_spec *spec = codec->spec; + return snd_hda_multi_out_dig_open(codec, &spec->multiout); +} + +static int nvhdmi_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, + struct hda_codec *codec, + struct snd_pcm_substream *substream) +{ + return 0; +} + +static int nvhdmi_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, + struct hda_codec *codec, + unsigned int stream_tag, + unsigned int format, + struct snd_pcm_substream *substream) +{ + hdmi_set_channel_count(codec, hinfo->nid, + substream->runtime->channels); + + hdmi_setup_audio_infoframe(codec, hinfo->nid, substream); + + hdmi_setup_stream(codec, hinfo->nid, stream_tag, format); + return 0; +} + +static struct hda_pcm_stream nvhdmi_pcm_digital_playback_tegra = { + .substreams = 1, + .channels_min = 1, + .channels_max = 8, + /* NID to query formats and rates and setup streams */ + .nid = Nv_Master_Convert_nid, + .ops = { + .open = nvhdmi_dig_playback_pcm_open, + .close = nvhdmi_dig_playback_pcm_close, + .prepare = nvhdmi_dig_playback_pcm_prepare + }, +}; + +static int nvhdmi_build_pcms(struct hda_codec *codec) +{ + struct nvhdmi_spec *spec = codec->spec; + struct hda_pcm *info = &spec->pcm_rec; + + codec->num_pcms = 1; + codec->pcm_info = info; + + info->name = "NVIDIA HDMI"; + info->pcm_type = HDA_PCM_TYPE_HDMI; + + info->stream[SNDRV_PCM_STREAM_PLAYBACK] + = nvhdmi_pcm_digital_playback_tegra; + + return 0; +} + +static void nvhdmi_free(struct hda_codec *codec) +{ + kfree(codec->spec); +} + +static struct hda_codec_ops nvhdmi_patch_ops = { + .build_controls = nvhdmi_build_controls, + .build_pcms = nvhdmi_build_pcms, + .init = nvhdmi_init, + .free = nvhdmi_free, +}; + +static int patch_nvhdmi(struct hda_codec *codec) +{ + struct nvhdmi_spec *spec; + + spec = kzalloc(sizeof(*spec), GFP_KERNEL); + if (spec == NULL) + return -ENOMEM; + + codec->spec = spec; + + spec->multiout.num_dacs = 0; /* no analog */ + spec->multiout.max_channels = 8; + spec->multiout.dig_out_nid = Nv_Master_Convert_nid; + + codec->patch_ops = nvhdmi_patch_ops; + + init_channel_allocations(); + + return 0; +} + +/* + * patch entries + */ +struct hda_codec_preset snd_hda_preset_nvhdmi[] = { + { .id = 0x10de0020, .name = "Tegra HDMI", .patch = patch_nvhdmi }, + {} /* terminator */ +}; + +MODULE_ALIAS("snd-hda-codec-id:10de0020"); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("NVIDIA HDMI HD-audio codec"); + +static struct hda_codec_preset_list nvhdmi_list = { + .preset = snd_hda_preset_nvhdmi, + .owner = THIS_MODULE, +}; + +static int __init patch_nvhdmi_init(void) +{ + return snd_hda_add_codec_preset(&nvhdmi_list); +} + +static void __exit patch_nvhdmi_exit(void) +{ + snd_hda_delete_codec_preset(&nvhdmi_list); +} + +module_init(patch_nvhdmi_init) +module_exit(patch_nvhdmi_exit) diff --git a/sound/core/memalloc.c b/sound/core/memalloc.c index 9e92441f9b78..a314c926d542 100644 --- a/sound/core/memalloc.c +++ b/sound/core/memalloc.c @@ -135,7 +135,9 @@ static void *snd_malloc_dev_pages(struct device *dev, size_t size, dma_addr_t *d return NULL; pg = get_order(size); gfp_flags = GFP_KERNEL +#ifndef CONFIG_SND_HDA_TEGRA | __GFP_COMP /* compound page lets parts be mapped */ +#endif /* CONFIG_SND_HDA_TEGRA */ | __GFP_NORETRY /* don't trigger OOM-killer */ | __GFP_NOWARN; /* no stack trace print - this call is non-critical */ res = dma_alloc_coherent(dev, PAGE_SIZE << pg, dma, gfp_flags); diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig index e7a8cd058efb..dc3f8a79be49 100644 --- a/sound/pci/Kconfig +++ b/sound/pci/Kconfig @@ -549,8 +549,6 @@ config SND_FM801_TEA575X depends on SND_FM801_TEA575X_BOOL default SND_FM801 -source "sound/pci/hda/Kconfig" - config SND_HDSP tristate "RME Hammerfall DSP Audio" select SND_HWDEP diff --git a/sound/pci/hda/Kconfig b/sound/pci/hda/Kconfig index 9194c3c1d04a..fde5410ddd18 100644 --- a/sound/pci/hda/Kconfig +++ b/sound/pci/hda/Kconfig @@ -1,3 +1,4 @@ +if !SND_HDA_TEGRA menuconfig SND_HDA_INTEL tristate "Intel HD Audio" select SND_PCM @@ -11,8 +12,9 @@ menuconfig SND_HDA_INTEL To compile this driver as a module, choose M here: the module will be called snd-hda-intel. +endif -if SND_HDA_INTEL +if (SND_HDA_INTEL || SND_HDA_TEGRA) config SND_HDA_HWDEP bool "Build hwdep interface for HD-audio driver" diff --git a/sound/pci/hda/Makefile b/sound/pci/hda/Makefile index 24bc195b02da..8d994685c0cd 100644 --- a/sound/pci/hda/Makefile +++ b/sound/pci/hda/Makefile @@ -1,4 +1,4 @@ -snd-hda-intel-objs := hda_intel.o +snd-hda-intel-objs := hda_intel.o lib_hda_intel.o snd-hda-codec-y := hda_codec.o snd-hda-codec-$(CONFIG_SND_HDA_GENERIC) += hda_generic.o diff --git a/sound/pci/hda/hda_beep.c b/sound/pci/hda/hda_beep.c index 29714c818b53..23a105f52f08 100644 --- a/sound/pci/hda/hda_beep.c +++ b/sound/pci/hda/hda_beep.c @@ -148,7 +148,11 @@ static int snd_hda_do_attach(struct hda_beep *beep) input_dev->evbit[0] = BIT_MASK(EV_SND); input_dev->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); input_dev->event = snd_hda_beep_event; +#if !defined(CONFIG_SND_HDA_TEGRA) input_dev->dev.parent = &codec->bus->pci->dev; +#else + input_dev->dev.parent = &codec->bus->pdev->dev; +#endif /* !CONFIG_SND_HDA_TEGRA */ input_set_drvdata(input_dev, beep); err = input_register_device(input_dev); diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c index b959c9f1e6fb..c23e30237ce8 100644 --- a/sound/pci/hda/hda_codec.c +++ b/sound/pci/hda/hda_codec.c @@ -3675,6 +3675,7 @@ int __devinit snd_hda_build_pcms(struct hda_bus *bus) } EXPORT_SYMBOL_HDA(snd_hda_build_pcms); +#if !defined(CONFIG_SND_HDA_TEGRA) /** * snd_hda_check_board_config - compare the current codec with the config table * @codec: the HDA codec @@ -3730,6 +3731,7 @@ int snd_hda_check_board_config(struct hda_codec *codec, return -1; } EXPORT_SYMBOL_HDA(snd_hda_check_board_config); +#endif /* !CONFIG_SND_HDA_TEGRA */ /** * snd_hda_check_board_codec_sid_config - compare the current codec diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h index c3ad37470f8f..11d11dfc78c8 100644 --- a/sound/pci/hda/hda_codec.h +++ b/sound/pci/hda/hda_codec.h @@ -25,6 +25,7 @@ #include <sound/control.h> #include <sound/pcm.h> #include <sound/hwdep.h> +#include <linux/platform_device.h> #if defined(CONFIG_PM) || defined(CONFIG_SND_HDA_POWER_SAVE) #define SND_HDA_NEEDS_RESUME /* resume control code is required */ @@ -620,7 +621,10 @@ struct hda_bus_ops { /* template to pass to the bus constructor */ struct hda_bus_template { void *private_data; - struct pci_dev *pci; + union { + struct pci_dev *pci; + struct platform_device *pdev; + }; const char *modelname; int *power_save; struct hda_bus_ops ops; @@ -637,7 +641,10 @@ struct hda_bus { /* copied from template */ void *private_data; - struct pci_dev *pci; + union { + struct pci_dev *pci; + struct platform_device *pdev; + }; const char *modelname; int *power_save; struct hda_bus_ops ops; diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index a8c6f3420344..6b5eb7642007 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -31,25 +31,10 @@ * CHANGES: * * 2004.12.01 Major rewrite by tiwai, merged the work of pshou - * + * */ -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/dma-mapping.h> -#include <linux/moduleparam.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/pci.h> -#include <linux/mutex.h> -#include <linux/reboot.h> -#include <sound/core.h> -#include <sound/initval.h> -#include "hda_codec.h" - +#include "lib_hda_intel.h" static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; @@ -478,40 +463,7 @@ static char *driver_short_names[] __devinitdata = { [AZX_DRIVER_GENERIC] = "HD-Audio Generic", }; -/* - * macros for easy use - */ -#define azx_writel(chip,reg,value) \ - writel(value, (chip)->remap_addr + ICH6_REG_##reg) -#define azx_readl(chip,reg) \ - readl((chip)->remap_addr + ICH6_REG_##reg) -#define azx_writew(chip,reg,value) \ - writew(value, (chip)->remap_addr + ICH6_REG_##reg) -#define azx_readw(chip,reg) \ - readw((chip)->remap_addr + ICH6_REG_##reg) -#define azx_writeb(chip,reg,value) \ - writeb(value, (chip)->remap_addr + ICH6_REG_##reg) -#define azx_readb(chip,reg) \ - readb((chip)->remap_addr + ICH6_REG_##reg) - -#define azx_sd_writel(dev,reg,value) \ - writel(value, (dev)->sd_addr + ICH6_REG_##reg) -#define azx_sd_readl(dev,reg) \ - readl((dev)->sd_addr + ICH6_REG_##reg) -#define azx_sd_writew(dev,reg,value) \ - writew(value, (dev)->sd_addr + ICH6_REG_##reg) -#define azx_sd_readw(dev,reg) \ - readw((dev)->sd_addr + ICH6_REG_##reg) -#define azx_sd_writeb(dev,reg,value) \ - writeb(value, (dev)->sd_addr + ICH6_REG_##reg) -#define azx_sd_readb(dev,reg) \ - readb((dev)->sd_addr + ICH6_REG_##reg) - -/* for pcm support */ -#define get_azx_dev(substream) (substream->runtime->private_data) - -static int azx_acquire_irq(struct azx *chip, int do_disconnect); -static int azx_send_cmd(struct hda_bus *bus, unsigned int val); + /* * Interface for HD codec */ @@ -534,501 +486,8 @@ static int azx_alloc_cmd_io(struct azx *chip) return 0; } -static void azx_init_cmd_io(struct azx *chip) -{ - spin_lock_irq(&chip->reg_lock); - /* CORB set up */ - chip->corb.addr = chip->rb.addr; - chip->corb.buf = (u32 *)chip->rb.area; - azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); - azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); - - /* set the corb size to 256 entries (ULI requires explicitly) */ - azx_writeb(chip, CORBSIZE, 0x02); - /* set the corb write pointer to 0 */ - azx_writew(chip, CORBWP, 0); - /* reset the corb hw read pointer */ - azx_writew(chip, CORBRP, ICH6_CORBRP_RST); - /* enable corb dma */ - azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); - - /* RIRB set up */ - chip->rirb.addr = chip->rb.addr + 2048; - chip->rirb.buf = (u32 *)(chip->rb.area + 2048); - chip->rirb.wp = chip->rirb.rp = 0; - memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); - azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); - azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); - - /* set the rirb size to 256 entries (ULI requires explicitly) */ - azx_writeb(chip, RIRBSIZE, 0x02); - /* reset the rirb hw write pointer */ - azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); - /* set N=1, get RIRB response interrupt for new entry */ - if (chip->driver_type == AZX_DRIVER_CTX) - azx_writew(chip, RINTCNT, 0xc0); - else - azx_writew(chip, RINTCNT, 1); - /* enable rirb dma and response irq */ - azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); - spin_unlock_irq(&chip->reg_lock); -} - -static void azx_free_cmd_io(struct azx *chip) -{ - spin_lock_irq(&chip->reg_lock); - /* disable ringbuffer DMAs */ - azx_writeb(chip, RIRBCTL, 0); - azx_writeb(chip, CORBCTL, 0); - spin_unlock_irq(&chip->reg_lock); -} - -static unsigned int azx_command_addr(u32 cmd) -{ - unsigned int addr = cmd >> 28; - - if (addr >= AZX_MAX_CODECS) { - snd_BUG(); - addr = 0; - } - - return addr; -} - -static unsigned int azx_response_addr(u32 res) -{ - unsigned int addr = res & 0xf; - - if (addr >= AZX_MAX_CODECS) { - snd_BUG(); - addr = 0; - } - - return addr; -} - -/* send a command */ -static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) -{ - struct azx *chip = bus->private_data; - unsigned int addr = azx_command_addr(val); - unsigned int wp; - - spin_lock_irq(&chip->reg_lock); - - /* add command to corb */ - wp = azx_readb(chip, CORBWP); - wp++; - wp %= ICH6_MAX_CORB_ENTRIES; - - chip->rirb.cmds[addr]++; - chip->corb.buf[wp] = cpu_to_le32(val); - azx_writel(chip, CORBWP, wp); - - spin_unlock_irq(&chip->reg_lock); - - return 0; -} - -#define ICH6_RIRB_EX_UNSOL_EV (1<<4) - -/* retrieve RIRB entry - called from interrupt handler */ -static void azx_update_rirb(struct azx *chip) -{ - unsigned int rp, wp; - unsigned int addr; - u32 res, res_ex; - - wp = azx_readb(chip, RIRBWP); - if (wp == chip->rirb.wp) - return; - chip->rirb.wp = wp; - - while (chip->rirb.rp != wp) { - chip->rirb.rp++; - chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; - - rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ - res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); - res = le32_to_cpu(chip->rirb.buf[rp]); - addr = azx_response_addr(res_ex); - if (res_ex & ICH6_RIRB_EX_UNSOL_EV) - snd_hda_queue_unsol_event(chip->bus, res, res_ex); - else if (chip->rirb.cmds[addr]) { - chip->rirb.res[addr] = res; - smp_wmb(); - chip->rirb.cmds[addr]--; - } else - snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " - "last cmd=%#08x\n", - res, res_ex, - chip->last_cmd[addr]); - } -} - -/* receive a response */ -static unsigned int azx_rirb_get_response(struct hda_bus *bus, - unsigned int addr) -{ - struct azx *chip = bus->private_data; - unsigned long timeout; - int do_poll = 0; - - again: - timeout = jiffies + msecs_to_jiffies(1000); - for (;;) { - if (chip->polling_mode || do_poll) { - spin_lock_irq(&chip->reg_lock); - azx_update_rirb(chip); - spin_unlock_irq(&chip->reg_lock); - } - if (!chip->rirb.cmds[addr]) { - smp_rmb(); - bus->rirb_error = 0; - - if (!do_poll) - chip->poll_count = 0; - return chip->rirb.res[addr]; /* the last value */ - } - if (time_after(jiffies, timeout)) - break; - if (bus->needs_damn_long_delay) - msleep(2); /* temporary workaround */ - else { - udelay(10); - cond_resched(); - } - } - - if (!chip->polling_mode && chip->poll_count < 2) { - snd_printdd(SFX "azx_get_response timeout, " - "polling the codec once: last cmd=0x%08x\n", - chip->last_cmd[addr]); - do_poll = 1; - chip->poll_count++; - goto again; - } - - - if (!chip->polling_mode) { - snd_printk(KERN_WARNING SFX "azx_get_response timeout, " - "switching to polling mode: last cmd=0x%08x\n", - chip->last_cmd[addr]); - chip->polling_mode = 1; - goto again; - } - - if (chip->msi) { - snd_printk(KERN_WARNING SFX "No response from codec, " - "disabling MSI: last cmd=0x%08x\n", - chip->last_cmd[addr]); - free_irq(chip->irq, chip); - chip->irq = -1; - pci_disable_msi(chip->pci); - chip->msi = 0; - if (azx_acquire_irq(chip, 1) < 0) { - bus->rirb_error = 1; - return -1; - } - goto again; - } - - if (chip->probing) { - /* If this critical timeout happens during the codec probing - * phase, this is likely an access to a non-existing codec - * slot. Better to return an error and reset the system. - */ - return -1; - } - - /* a fatal communication error; need either to reset or to fallback - * to the single_cmd mode - */ - bus->rirb_error = 1; - if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { - bus->response_reset = 1; - return -1; /* give a chance to retry */ - } - - snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " - "switching to single_cmd mode: last cmd=0x%08x\n", - chip->last_cmd[addr]); - chip->single_cmd = 1; - bus->response_reset = 0; - /* release CORB/RIRB */ - azx_free_cmd_io(chip); - /* disable unsolicited responses */ - azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); - return -1; -} - -/* - * Use the single immediate command instead of CORB/RIRB for simplicity - * - * Note: according to Intel, this is not preferred use. The command was - * intended for the BIOS only, and may get confused with unsolicited - * responses. So, we shouldn't use it for normal operation from the - * driver. - * I left the codes, however, for debugging/testing purposes. - */ -/* receive a response */ -static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) -{ - int timeout = 50; - - while (timeout--) { - /* check IRV busy bit */ - if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { - /* reuse rirb.res as the response return value */ - chip->rirb.res[addr] = azx_readl(chip, IR); - return 0; - } - udelay(1); - } - if (printk_ratelimit()) - snd_printd(SFX "get_response timeout: IRS=0x%x\n", - azx_readw(chip, IRS)); - chip->rirb.res[addr] = -1; - return -EIO; -} - -/* send a command */ -static int azx_single_send_cmd(struct hda_bus *bus, u32 val) -{ - struct azx *chip = bus->private_data; - unsigned int addr = azx_command_addr(val); - int timeout = 50; - - bus->rirb_error = 0; - while (timeout--) { - /* check ICB busy bit */ - if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { - /* Clear IRV valid bit */ - azx_writew(chip, IRS, azx_readw(chip, IRS) | - ICH6_IRS_VALID); - azx_writel(chip, IC, val); - azx_writew(chip, IRS, azx_readw(chip, IRS) | - ICH6_IRS_BUSY); - return azx_single_wait_for_response(chip, addr); - } - udelay(1); - } - if (printk_ratelimit()) - snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", - azx_readw(chip, IRS), val); - return -EIO; -} -/* receive a response */ -static unsigned int azx_single_get_response(struct hda_bus *bus, - unsigned int addr) -{ - struct azx *chip = bus->private_data; - return chip->rirb.res[addr]; -} - -/* - * The below are the main callbacks from hda_codec. - * - * They are just the skeleton to call sub-callbacks according to the - * current setting of chip->single_cmd. - */ - -/* send a command */ -static int azx_send_cmd(struct hda_bus *bus, unsigned int val) -{ - struct azx *chip = bus->private_data; - - chip->last_cmd[azx_command_addr(val)] = val; - if (chip->single_cmd) - return azx_single_send_cmd(bus, val); - else - return azx_corb_send_cmd(bus, val); -} - -/* get a response */ -static unsigned int azx_get_response(struct hda_bus *bus, - unsigned int addr) -{ - struct azx *chip = bus->private_data; - if (chip->single_cmd) - return azx_single_get_response(bus, addr); - else - return azx_rirb_get_response(bus, addr); -} - -#ifdef CONFIG_SND_HDA_POWER_SAVE -static void azx_power_notify(struct hda_bus *bus); -#endif - -/* reset codec link */ -static int azx_reset(struct azx *chip, int full_reset) -{ - int count; - - if (!full_reset) - goto __skip; - - /* clear STATESTS */ - azx_writeb(chip, STATESTS, STATESTS_INT_MASK); - - /* reset controller */ - azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); - - count = 50; - while (azx_readb(chip, GCTL) && --count) - msleep(1); - - /* delay for >= 100us for codec PLL to settle per spec - * Rev 0.9 section 5.5.1 - */ - msleep(1); - - /* Bring controller out of reset */ - azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); - - count = 50; - while (!azx_readb(chip, GCTL) && --count) - msleep(1); - - /* Brent Chartrand said to wait >= 540us for codecs to initialize */ - msleep(1); - - __skip: - /* check to see if controller is ready */ - if (!azx_readb(chip, GCTL)) { - snd_printd(SFX "azx_reset: controller not ready!\n"); - return -EBUSY; - } - - /* Accept unsolicited responses */ - if (!chip->single_cmd) - azx_writel(chip, GCTL, azx_readl(chip, GCTL) | - ICH6_GCTL_UNSOL); - - /* detect codecs */ - if (!chip->codec_mask) { - chip->codec_mask = azx_readw(chip, STATESTS); - snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask); - } - - return 0; -} - - -/* - * Lowlevel interface - */ - -/* enable interrupts */ -static void azx_int_enable(struct azx *chip) -{ - /* enable controller CIE and GIE */ - azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | - ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); -} - -/* disable interrupts */ -static void azx_int_disable(struct azx *chip) -{ - int i; - - /* disable interrupts in stream descriptor */ - for (i = 0; i < chip->num_streams; i++) { - struct azx_dev *azx_dev = &chip->azx_dev[i]; - azx_sd_writeb(azx_dev, SD_CTL, - azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); - } - - /* disable SIE for all streams */ - azx_writeb(chip, INTCTL, 0); - - /* disable controller CIE and GIE */ - azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & - ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); -} - -/* clear interrupts */ -static void azx_int_clear(struct azx *chip) -{ - int i; - - /* clear stream status */ - for (i = 0; i < chip->num_streams; i++) { - struct azx_dev *azx_dev = &chip->azx_dev[i]; - azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); - } - - /* clear STATESTS */ - azx_writeb(chip, STATESTS, STATESTS_INT_MASK); - - /* clear rirb status */ - azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); - - /* clear int status */ - azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); -} - -/* start a stream */ -static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) -{ - /* - * Before stream start, initialize parameter - */ - azx_dev->insufficient = 1; - - /* enable SIE */ - azx_writel(chip, INTCTL, - azx_readl(chip, INTCTL) | (1 << azx_dev->index)); - /* set DMA start and interrupt mask */ - azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | - SD_CTL_DMA_START | SD_INT_MASK); -} - -/* stop DMA */ -static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) -{ - azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & - ~(SD_CTL_DMA_START | SD_INT_MASK)); - azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ -} - -/* stop a stream */ -static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) -{ - azx_stream_clear(chip, azx_dev); - /* disable SIE */ - azx_writel(chip, INTCTL, - azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); -} - - -/* - * reset and start the controller registers - */ -static void azx_init_chip(struct azx *chip, int full_reset) -{ - if (chip->initialized) - return; - - /* reset controller */ - azx_reset(chip, full_reset); - - /* initialize interrupts */ - azx_int_clear(chip); - azx_int_enable(chip); - - /* initialize the codec command I/O */ - if (!chip->single_cmd) - azx_init_cmd_io(chip); - - /* program the position buffer */ - azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); - azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); - - chip->initialized = 1; -} /* * initialize the PCI registers @@ -1095,111 +554,11 @@ static void azx_init_pci(struct azx *chip) static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); -/* - * interrupt handler - */ -static irqreturn_t azx_interrupt(int irq, void *dev_id) -{ - struct azx *chip = dev_id; - struct azx_dev *azx_dev; - u32 status; - u8 sd_status; - int i, ok; - - spin_lock(&chip->reg_lock); - - status = azx_readl(chip, INTSTS); - if (status == 0) { - spin_unlock(&chip->reg_lock); - return IRQ_NONE; - } - - for (i = 0; i < chip->num_streams; i++) { - azx_dev = &chip->azx_dev[i]; - if (status & azx_dev->sd_int_sta_mask) { - sd_status = azx_sd_readb(azx_dev, SD_STS); - azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); - if (!azx_dev->substream || !azx_dev->running || - !(sd_status & SD_INT_COMPLETE)) - continue; - /* check whether this IRQ is really acceptable */ - ok = azx_position_ok(chip, azx_dev); - if (ok == 1) { - azx_dev->irq_pending = 0; - spin_unlock(&chip->reg_lock); - snd_pcm_period_elapsed(azx_dev->substream); - spin_lock(&chip->reg_lock); - } else if (ok == 0 && chip->bus && chip->bus->workq) { - /* bogus IRQ, process it later */ - azx_dev->irq_pending = 1; - queue_work(chip->bus->workq, - &chip->irq_pending_work); - } - } - } - - /* clear rirb int */ - status = azx_readb(chip, RIRBSTS); - if (status & RIRB_INT_MASK) { - if (status & RIRB_INT_RESPONSE) { - if (chip->driver_type == AZX_DRIVER_CTX) - udelay(80); - azx_update_rirb(chip); - } - azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); - } - -#if 0 - /* clear state status int */ - if (azx_readb(chip, STATESTS) & 0x04) - azx_writeb(chip, STATESTS, 0x04); -#endif - spin_unlock(&chip->reg_lock); - - return IRQ_HANDLED; -} - - -/* - * set up a BDL entry - */ -static int setup_bdle(struct snd_pcm_substream *substream, - struct azx_dev *azx_dev, u32 **bdlp, - int ofs, int size, int with_ioc) -{ - u32 *bdl = *bdlp; - - while (size > 0) { - dma_addr_t addr; - int chunk; - - if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) - return -EINVAL; - - addr = snd_pcm_sgbuf_get_addr(substream, ofs); - /* program the address field of the BDL entry */ - bdl[0] = cpu_to_le32((u32)addr); - bdl[1] = cpu_to_le32(upper_32_bits(addr)); - /* program the size field of the BDL entry */ - chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size); - bdl[2] = cpu_to_le32(chunk); - /* program the IOC to enable interrupt - * only when the whole fragment is processed - */ - size -= chunk; - bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); - bdl += 4; - azx_dev->frags++; - ofs += chunk; - } - *bdlp = bdl; - return ofs; -} /* * set up BDL entries */ -static int azx_setup_periods(struct azx *chip, +int azx_setup_periods(struct azx *chip, struct snd_pcm_substream *substream, struct azx_dev *azx_dev) { @@ -1258,126 +617,11 @@ static int azx_setup_periods(struct azx *chip, azx_dev->bufsize, period_bytes); return -EINVAL; } - -/* reset stream */ -static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) -{ - unsigned char val; - int timeout; - - azx_stream_clear(chip, azx_dev); - - azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | - SD_CTL_STREAM_RESET); - udelay(3); - timeout = 300; - while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && - --timeout) - ; - val &= ~SD_CTL_STREAM_RESET; - azx_sd_writeb(azx_dev, SD_CTL, val); - udelay(3); - - timeout = 300; - /* waiting for hardware to report that the stream is out of reset */ - while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && - --timeout) - ; - - /* reset first position - may not be synced with hw at this time */ - *azx_dev->posbuf = 0; -} - -/* - * set up the SD for streaming - */ -static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) -{ - /* make sure the run bit is zero for SD */ - azx_stream_clear(chip, azx_dev); - /* program the stream_tag */ - azx_sd_writel(azx_dev, SD_CTL, - (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| - (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); - - /* program the length of samples in cyclic buffer */ - azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); - - /* program the stream format */ - /* this value needs to be the same as the one programmed */ - azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); - - /* program the stream LVI (last valid index) of the BDL */ - azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); - - /* program the BDL address */ - /* lower BDL address */ - azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); - /* upper BDL address */ - azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); - - /* enable the position buffer */ - if (chip->position_fix[0] == POS_FIX_POSBUF || - chip->position_fix[0] == POS_FIX_AUTO || - chip->position_fix[1] == POS_FIX_POSBUF || - chip->position_fix[1] == POS_FIX_AUTO || - chip->via_dmapos_patch) { - if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) - azx_writel(chip, DPLBASE, - (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); } - - /* set the interrupt enable bits in the descriptor control register */ - azx_sd_writel(azx_dev, SD_CTL, - azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); - - return 0; -} - -/* - * Probe the given codec address - */ -static int probe_codec(struct azx *chip, int addr) -{ - unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | - (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; - unsigned int res; - - mutex_lock(&chip->bus->cmd_mutex); - chip->probing = 1; - azx_send_cmd(chip->bus, cmd); - res = azx_get_response(chip->bus, addr); - chip->probing = 0; - mutex_unlock(&chip->bus->cmd_mutex); - if (res == -1) - return -EIO; - snd_printdd(SFX "codec #%d probed OK\n", addr); - return 0; } static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, struct hda_pcm *cpcm); -static void azx_stop_chip(struct azx *chip); - -static void azx_bus_reset(struct hda_bus *bus) -{ - struct azx *chip = bus->private_data; - - bus->in_reset = 1; - azx_stop_chip(chip); - azx_init_chip(chip, 1); -#ifdef CONFIG_PM - if (chip->initialized) { - int i; - - for (i = 0; i < HDA_MAX_PCMS; i++) - snd_pcm_suspend_all(chip->pcm[i]); - snd_hda_suspend(chip->bus); - snd_hda_resume(chip->bus); - } -#endif - bus->in_reset = 0; -} /* * Codec initialization @@ -1461,438 +705,6 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model) } return 0; } - -/* configure each codec instance */ -static int __devinit azx_codec_configure(struct azx *chip) -{ - struct hda_codec *codec; - list_for_each_entry(codec, &chip->bus->codec_list, list) { - snd_hda_codec_configure(codec); - } - return 0; -} - - -/* - * PCM support - */ - -/* assign a stream for the PCM */ -static inline struct azx_dev * -azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) -{ - int dev, i, nums; - struct azx_dev *res = NULL; - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - dev = chip->playback_index_offset; - nums = chip->playback_streams; - } else { - dev = chip->capture_index_offset; - nums = chip->capture_streams; - } - for (i = 0; i < nums; i++, dev++) - if (!chip->azx_dev[dev].opened) { - res = &chip->azx_dev[dev]; - if (res->device == substream->pcm->device) - break; - } - if (res) { - res->opened = 1; - res->device = substream->pcm->device; - } - return res; -} - -/* release the assigned stream */ -static inline void azx_release_device(struct azx_dev *azx_dev) -{ - azx_dev->opened = 0; -} - -static struct snd_pcm_hardware azx_pcm_hw = { - .info = (SNDRV_PCM_INFO_MMAP | - SNDRV_PCM_INFO_INTERLEAVED | - SNDRV_PCM_INFO_BLOCK_TRANSFER | - SNDRV_PCM_INFO_MMAP_VALID | - /* No full-resume yet implemented */ - /* SNDRV_PCM_INFO_RESUME |*/ - SNDRV_PCM_INFO_PAUSE | - SNDRV_PCM_INFO_SYNC_START), - .formats = SNDRV_PCM_FMTBIT_S16_LE, - .rates = SNDRV_PCM_RATE_48000, - .rate_min = 48000, - .rate_max = 48000, - .channels_min = 2, - .channels_max = 2, - .buffer_bytes_max = AZX_MAX_BUF_SIZE, - .period_bytes_min = 128, - .period_bytes_max = AZX_MAX_BUF_SIZE / 2, - .periods_min = 2, - .periods_max = AZX_MAX_FRAG, - .fifo_size = 0, -}; - -struct azx_pcm { - struct azx *chip; - struct hda_codec *codec; - struct hda_pcm_stream *hinfo[2]; -}; - -static int azx_pcm_open(struct snd_pcm_substream *substream) -{ - struct azx_pcm *apcm = snd_pcm_substream_chip(substream); - struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; - struct azx *chip = apcm->chip; - struct azx_dev *azx_dev; - struct snd_pcm_runtime *runtime = substream->runtime; - unsigned long flags; - int err; - - mutex_lock(&chip->open_mutex); - azx_dev = azx_assign_device(chip, substream); - if (azx_dev == NULL) { - mutex_unlock(&chip->open_mutex); - return -EBUSY; - } - runtime->hw = azx_pcm_hw; - runtime->hw.channels_min = hinfo->channels_min; - runtime->hw.channels_max = hinfo->channels_max; - runtime->hw.formats = hinfo->formats; - runtime->hw.rates = hinfo->rates; - snd_pcm_limit_hw_rates(runtime); - snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); - snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, - 128); - snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, - 128); - snd_hda_power_up(apcm->codec); - err = hinfo->ops.open(hinfo, apcm->codec, substream); - if (err < 0) { - azx_release_device(azx_dev); - snd_hda_power_down(apcm->codec); - mutex_unlock(&chip->open_mutex); - return err; - } - snd_pcm_limit_hw_rates(runtime); - /* sanity check */ - if (snd_BUG_ON(!runtime->hw.channels_min) || - snd_BUG_ON(!runtime->hw.channels_max) || - snd_BUG_ON(!runtime->hw.formats) || - snd_BUG_ON(!runtime->hw.rates)) { - azx_release_device(azx_dev); - hinfo->ops.close(hinfo, apcm->codec, substream); - snd_hda_power_down(apcm->codec); - mutex_unlock(&chip->open_mutex); - return -EINVAL; - } - spin_lock_irqsave(&chip->reg_lock, flags); - azx_dev->substream = substream; - azx_dev->running = 0; - spin_unlock_irqrestore(&chip->reg_lock, flags); - - runtime->private_data = azx_dev; - snd_pcm_set_sync(substream); - mutex_unlock(&chip->open_mutex); - return 0; -} - -static int azx_pcm_close(struct snd_pcm_substream *substream) -{ - struct azx_pcm *apcm = snd_pcm_substream_chip(substream); - struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; - struct azx *chip = apcm->chip; - struct azx_dev *azx_dev = get_azx_dev(substream); - unsigned long flags; - - mutex_lock(&chip->open_mutex); - spin_lock_irqsave(&chip->reg_lock, flags); - azx_dev->substream = NULL; - azx_dev->running = 0; - spin_unlock_irqrestore(&chip->reg_lock, flags); - azx_release_device(azx_dev); - hinfo->ops.close(hinfo, apcm->codec, substream); - snd_hda_power_down(apcm->codec); - mutex_unlock(&chip->open_mutex); - return 0; -} - -static int azx_pcm_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *hw_params) -{ - struct azx_dev *azx_dev = get_azx_dev(substream); - - azx_dev->bufsize = 0; - azx_dev->period_bytes = 0; - azx_dev->format_val = 0; - return snd_pcm_lib_malloc_pages(substream, - params_buffer_bytes(hw_params)); -} - -static int azx_pcm_hw_free(struct snd_pcm_substream *substream) -{ - struct azx_pcm *apcm = snd_pcm_substream_chip(substream); - struct azx_dev *azx_dev = get_azx_dev(substream); - struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; - - /* reset BDL address */ - azx_sd_writel(azx_dev, SD_BDLPL, 0); - azx_sd_writel(azx_dev, SD_BDLPU, 0); - azx_sd_writel(azx_dev, SD_CTL, 0); - azx_dev->bufsize = 0; - azx_dev->period_bytes = 0; - azx_dev->format_val = 0; - - snd_hda_codec_cleanup(apcm->codec, hinfo, substream); - - return snd_pcm_lib_free_pages(substream); -} - -static int azx_pcm_prepare(struct snd_pcm_substream *substream) -{ - struct azx_pcm *apcm = snd_pcm_substream_chip(substream); - struct azx *chip = apcm->chip; - struct azx_dev *azx_dev = get_azx_dev(substream); - struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; - struct snd_pcm_runtime *runtime = substream->runtime; - unsigned int bufsize, period_bytes, format_val, stream_tag; - int err; - - azx_stream_reset(chip, azx_dev); - format_val = snd_hda_calc_stream_format(runtime->rate, - runtime->channels, - runtime->format, - hinfo->maxbps, - apcm->codec->spdif_ctls); - if (!format_val) { - snd_printk(KERN_ERR SFX - "invalid format_val, rate=%d, ch=%d, format=%d\n", - runtime->rate, runtime->channels, runtime->format); - return -EINVAL; - } - - bufsize = snd_pcm_lib_buffer_bytes(substream); - period_bytes = snd_pcm_lib_period_bytes(substream); - - snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", - bufsize, format_val); - - if (bufsize != azx_dev->bufsize || - period_bytes != azx_dev->period_bytes || - format_val != azx_dev->format_val) { - azx_dev->bufsize = bufsize; - azx_dev->period_bytes = period_bytes; - azx_dev->format_val = format_val; - err = azx_setup_periods(chip, substream, azx_dev); - if (err < 0) - return err; - } - - /* wallclk has 24Mhz clock source */ - azx_dev->period_wallclk = (((runtime->period_size * 24000) / - runtime->rate) * 1000); - azx_setup_controller(chip, azx_dev); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; - else - azx_dev->fifo_size = 0; - - stream_tag = azx_dev->stream_tag; - /* CA-IBG chips need the playback stream starting from 1 */ - if (chip->driver_type == AZX_DRIVER_CTX && - stream_tag > chip->capture_streams) - stream_tag -= chip->capture_streams; - return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, - azx_dev->format_val, substream); -} - -static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) -{ - struct azx_pcm *apcm = snd_pcm_substream_chip(substream); - struct azx *chip = apcm->chip; - struct azx_dev *azx_dev; - struct snd_pcm_substream *s; - int rstart = 0, start, nsync = 0, sbits = 0; - int nwait, timeout; - - switch (cmd) { - case SNDRV_PCM_TRIGGER_START: - rstart = 1; - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - case SNDRV_PCM_TRIGGER_RESUME: - start = 1; - break; - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_STOP: - start = 0; - break; - default: - return -EINVAL; - } - - snd_pcm_group_for_each_entry(s, substream) { - if (s->pcm->card != substream->pcm->card) - continue; - azx_dev = get_azx_dev(s); - sbits |= 1 << azx_dev->index; - nsync++; - snd_pcm_trigger_done(s, substream); - } - - spin_lock(&chip->reg_lock); - if (nsync > 1) { - /* first, set SYNC bits of corresponding streams */ - azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); - } - snd_pcm_group_for_each_entry(s, substream) { - if (s->pcm->card != substream->pcm->card) - continue; - azx_dev = get_azx_dev(s); - if (start) { - azx_dev->start_wallclk = azx_readl(chip, WALLCLK); - if (!rstart) - azx_dev->start_wallclk -= - azx_dev->period_wallclk; - azx_stream_start(chip, azx_dev); - } else { - azx_stream_stop(chip, azx_dev); - } - azx_dev->running = start; - } - spin_unlock(&chip->reg_lock); - if (start) { - if (nsync == 1) - return 0; - /* wait until all FIFOs get ready */ - for (timeout = 5000; timeout; timeout--) { - nwait = 0; - snd_pcm_group_for_each_entry(s, substream) { - if (s->pcm->card != substream->pcm->card) - continue; - azx_dev = get_azx_dev(s); - if (!(azx_sd_readb(azx_dev, SD_STS) & - SD_STS_FIFO_READY)) - nwait++; - } - if (!nwait) - break; - cpu_relax(); - } - } else { - /* wait until all RUN bits are cleared */ - for (timeout = 5000; timeout; timeout--) { - nwait = 0; - snd_pcm_group_for_each_entry(s, substream) { - if (s->pcm->card != substream->pcm->card) - continue; - azx_dev = get_azx_dev(s); - if (azx_sd_readb(azx_dev, SD_CTL) & - SD_CTL_DMA_START) - nwait++; - } - if (!nwait) - break; - cpu_relax(); - } - } - if (nsync > 1) { - spin_lock(&chip->reg_lock); - /* reset SYNC bits */ - azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); - spin_unlock(&chip->reg_lock); - } - return 0; -} - -/* get the current DMA position with correction on VIA chips */ -static unsigned int azx_via_get_position(struct azx *chip, - struct azx_dev *azx_dev) -{ - unsigned int link_pos, mini_pos, bound_pos; - unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; - unsigned int fifo_size; - - link_pos = azx_sd_readl(azx_dev, SD_LPIB); - if (azx_dev->index >= 4) { - /* Playback, no problem using link position */ - return link_pos; - } - - /* Capture */ - /* For new chipset, - * use mod to get the DMA position just like old chipset - */ - mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); - mod_dma_pos %= azx_dev->period_bytes; - - /* azx_dev->fifo_size can't get FIFO size of in stream. - * Get from base address + offset. - */ - fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); - - if (azx_dev->insufficient) { - /* Link position never gather than FIFO size */ - if (link_pos <= fifo_size) - return 0; - - azx_dev->insufficient = 0; - } - - if (link_pos <= fifo_size) - mini_pos = azx_dev->bufsize + link_pos - fifo_size; - else - mini_pos = link_pos - fifo_size; - - /* Find nearest previous boudary */ - mod_mini_pos = mini_pos % azx_dev->period_bytes; - mod_link_pos = link_pos % azx_dev->period_bytes; - if (mod_link_pos >= fifo_size) - bound_pos = link_pos - mod_link_pos; - else if (mod_dma_pos >= mod_mini_pos) - bound_pos = mini_pos - mod_mini_pos; - else { - bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; - if (bound_pos >= azx_dev->bufsize) - bound_pos = 0; - } - - /* Calculate real DMA position we want */ - return bound_pos + mod_dma_pos; -} - -static unsigned int azx_get_position(struct azx *chip, - struct azx_dev *azx_dev) -{ - unsigned int pos; - - if (chip->via_dmapos_patch) - pos = azx_via_get_position(chip, azx_dev); - else { - int stream = azx_dev->substream->stream; - if (chip->position_fix[stream] == POS_FIX_POSBUF || - chip->position_fix[stream] == POS_FIX_AUTO) { - /* use the position buffer */ - pos = le32_to_cpu(*azx_dev->posbuf); - } else { - /* read LPIB */ - pos = azx_sd_readl(azx_dev, SD_LPIB); - } - } - if (pos >= azx_dev->bufsize) - pos = 0; - return pos; -} - -static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) -{ - struct azx_pcm *apcm = snd_pcm_substream_chip(substream); - struct azx *chip = apcm->chip; - struct azx_dev *azx_dev = get_azx_dev(substream); - return bytes_to_frames(substream->runtime, - azx_get_position(chip, azx_dev)); -} - /* * Check whether the current DMA position is acceptable for updating * periods. Returns non-zero if it's OK. @@ -1902,7 +714,7 @@ static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) * data is processed. So, we need to process it afterwords in a * workqueue. */ -static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) +int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) { u32 wallclk; unsigned int pos; @@ -1936,81 +748,6 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) return 1; /* OK, it's fine */ } -/* - * The work for pending PCM period updates. - */ -static void azx_irq_pending_work(struct work_struct *work) -{ - struct azx *chip = container_of(work, struct azx, irq_pending_work); - int i, pending, ok; - - if (!chip->irq_pending_warned) { - printk(KERN_WARNING - "hda-intel: IRQ timing workaround is activated " - "for card #%d. Suggest a bigger bdl_pos_adj.\n", - chip->card->number); - chip->irq_pending_warned = 1; - } - - for (;;) { - pending = 0; - spin_lock_irq(&chip->reg_lock); - for (i = 0; i < chip->num_streams; i++) { - struct azx_dev *azx_dev = &chip->azx_dev[i]; - if (!azx_dev->irq_pending || - !azx_dev->substream || - !azx_dev->running) - continue; - ok = azx_position_ok(chip, azx_dev); - if (ok > 0) { - azx_dev->irq_pending = 0; - spin_unlock(&chip->reg_lock); - snd_pcm_period_elapsed(azx_dev->substream); - spin_lock(&chip->reg_lock); - } else if (ok < 0) { - pending = 0; /* too early */ - } else - pending++; - } - spin_unlock_irq(&chip->reg_lock); - if (!pending) - return; - msleep(1); - } -} - -/* clear irq_pending flags and assure no on-going workq */ -static void azx_clear_irq_pending(struct azx *chip) -{ - int i; - - spin_lock_irq(&chip->reg_lock); - for (i = 0; i < chip->num_streams; i++) - chip->azx_dev[i].irq_pending = 0; - spin_unlock_irq(&chip->reg_lock); -} - -static struct snd_pcm_ops azx_pcm_ops = { - .open = azx_pcm_open, - .close = azx_pcm_close, - .ioctl = snd_pcm_lib_ioctl, - .hw_params = azx_pcm_hw_params, - .hw_free = azx_pcm_hw_free, - .prepare = azx_pcm_prepare, - .trigger = azx_pcm_trigger, - .pointer = azx_pcm_pointer, - .page = snd_pcm_sgbuf_ops_page, -}; - -static void azx_pcm_free(struct snd_pcm *pcm) -{ - struct azx_pcm *apcm = pcm->private_data; - if (apcm) { - apcm->chip->pcm[pcm->device] = NULL; - kfree(apcm); - } -} - static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, struct hda_pcm *cpcm) @@ -2061,114 +798,12 @@ azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, } /* - * mixer creation - all stuff is implemented in hda module - */ -static int __devinit azx_mixer_create(struct azx *chip) -{ - return snd_hda_build_controls(chip->bus); -} - - -/* - * initialize SD streams - */ -static int __devinit azx_init_stream(struct azx *chip) -{ - int i; - - /* initialize each stream (aka device) - * assign the starting bdl address to each stream (device) - * and initialize - */ - for (i = 0; i < chip->num_streams; i++) { - struct azx_dev *azx_dev = &chip->azx_dev[i]; - azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); - /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ - azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); - /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ - azx_dev->sd_int_sta_mask = 1 << i; - /* stream tag: must be non-zero and unique */ - azx_dev->index = i; - azx_dev->stream_tag = i + 1; - } - - return 0; -} - -static int azx_acquire_irq(struct azx *chip, int do_disconnect) -{ - if (request_irq(chip->pci->irq, azx_interrupt, - chip->msi ? 0 : IRQF_SHARED, - "hda_intel", chip)) { - printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " - "disabling device\n", chip->pci->irq); - if (do_disconnect) - snd_card_disconnect(chip->card); - return -1; - } - chip->irq = chip->pci->irq; - pci_intx(chip->pci, !chip->msi); - return 0; -} - - -static void azx_stop_chip(struct azx *chip) -{ - if (!chip->initialized) - return; - - /* disable interrupts */ - azx_int_disable(chip); - azx_int_clear(chip); - - /* disable CORB/RIRB */ - azx_free_cmd_io(chip); - - /* disable position buffer */ - azx_writel(chip, DPLBASE, 0); - azx_writel(chip, DPUBASE, 0); - - chip->initialized = 0; -} - -#ifdef CONFIG_SND_HDA_POWER_SAVE -/* power-up/down the controller */ -static void azx_power_notify(struct hda_bus *bus) -{ - struct azx *chip = bus->private_data; - struct hda_codec *c; - int power_on = 0; - - list_for_each_entry(c, &bus->codec_list, list) { - if (c->power_on) { - power_on = 1; - break; - } - } - if (power_on) - azx_init_chip(chip, 1); - else if (chip->running && power_save_controller && - !bus->power_keep_link_on) - azx_stop_chip(chip); -} -#endif /* CONFIG_SND_HDA_POWER_SAVE */ #ifdef CONFIG_PM /* * power management */ -static int snd_hda_codecs_inuse(struct hda_bus *bus) -{ - struct hda_codec *codec; - - list_for_each_entry(codec, &bus->codec_list, list) { - if (snd_hda_codec_needs_resume(codec)) - return 1; - } - return 0; -} - static int azx_suspend(struct pci_dev *pci, pm_message_t state) { struct snd_card *card = pci_get_drvdata(pci); @@ -2224,30 +859,6 @@ static int azx_resume(struct pci_dev *pci) } #endif /* CONFIG_PM */ - -/* - * reboot notifier for hang-up problem at power-down - */ -static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) -{ - struct azx *chip = container_of(nb, struct azx, reboot_notifier); - snd_hda_bus_reboot_notify(chip->bus); - azx_stop_chip(chip); - return NOTIFY_OK; -} - -static void azx_notifier_register(struct azx *chip) -{ - chip->reboot_notifier.notifier_call = azx_halt; - register_reboot_notifier(&chip->reboot_notifier); -} - -static void azx_notifier_unregister(struct azx *chip) -{ - if (chip->reboot_notifier.notifier_call) - unregister_reboot_notifier(&chip->reboot_notifier); -} - /* * destructor */ @@ -2265,7 +876,7 @@ static int azx_free(struct azx *chip) } if (chip->irq >= 0) - free_irq(chip->irq, (void*)chip); + free_irq(chip->irq, (void *)chip); if (chip->msi) pci_disable_msi(chip->pci); if (chip->remap_addr) @@ -2651,19 +1262,6 @@ static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, return err; } -static void power_down_all_codecs(struct azx *chip) -{ -#ifdef CONFIG_SND_HDA_POWER_SAVE - /* The codecs were powered up in snd_hda_codec_new(). - * Now all initialization done, so turn them down if possible - */ - struct hda_codec *codec; - list_for_each_entry(codec, &chip->bus->codec_list, list) { - snd_hda_power_down(codec); - } -#endif -} - static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { diff --git a/sound/pci/hda/lib_hda_intel.c b/sound/pci/hda/lib_hda_intel.c new file mode 100644 index 000000000000..293480b0308d --- /dev/null +++ b/sound/pci/hda/lib_hda_intel.c @@ -0,0 +1,1411 @@ +/* + * + * lib_hda_intel.c - Common functions for Intel HD Audio drivers. + * + * Copyright(c) 2004 Intel Corporation. All rights reserved. + * + * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> + * PeiSen Hou <pshou@realtek.com.tw> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * CONTACTS: + * + * Matt Jared matt.jared@intel.com + * Andy Kopp andy.kopp@intel.com + * Dan Kogan dan.d.kogan@intel.com + * + * CHANGES: + * + * 2004.12.01 Major rewrite by tiwai, merged the work of pshou + * + */ + +#include "lib_hda_intel.h" + +/* + * Interface for HD codec + */ + +void azx_init_cmd_io(struct azx *chip) +{ + spin_lock_irq(&chip->reg_lock); + /* CORB set up */ + chip->corb.addr = chip->rb.addr; + chip->corb.buf = (u32 *)chip->rb.area; + azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); + azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); + + /* set the corb size to 256 entries (ULI requires explicitly) */ + azx_writeb(chip, CORBSIZE, 0x02); + /* set the corb write pointer to 0 */ + azx_writew(chip, CORBWP, 0); + /* reset the corb hw read pointer */ + azx_writew(chip, CORBRP, ICH6_CORBRP_RST); + /* enable corb dma */ + azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); + + /* RIRB set up */ + chip->rirb.addr = chip->rb.addr + 2048; + chip->rirb.buf = (u32 *)(chip->rb.area + 2048); + chip->rirb.wp = chip->rirb.rp = 0; + memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); + azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); + azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); + + /* set the rirb size to 256 entries (ULI requires explicitly) */ + azx_writeb(chip, RIRBSIZE, 0x02); + /* reset the rirb hw write pointer */ + azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); + /* set N=1, get RIRB response interrupt for new entry */ + if (chip->driver_type == AZX_DRIVER_CTX) + azx_writew(chip, RINTCNT, 0xc0); + else + azx_writew(chip, RINTCNT, 1); + /* enable rirb dma and response irq */ + azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); + spin_unlock_irq(&chip->reg_lock); +} + +void azx_free_cmd_io(struct azx *chip) +{ + spin_lock_irq(&chip->reg_lock); + /* disable ringbuffer DMAs */ + azx_writeb(chip, RIRBCTL, 0); + azx_writeb(chip, CORBCTL, 0); + spin_unlock_irq(&chip->reg_lock); +} + +unsigned int azx_command_addr(u32 cmd) +{ + unsigned int addr = cmd >> 28; + + if (addr >= AZX_MAX_CODECS) { + snd_BUG(); + addr = 0; + } + + return addr; +} + +unsigned int azx_response_addr(u32 res) +{ + unsigned int addr = res & 0xf; + + if (addr >= AZX_MAX_CODECS) { + snd_BUG(); + addr = 0; + } + + return addr; +} + +/* send a command */ +int azx_corb_send_cmd(struct hda_bus *bus, u32 val) +{ + struct azx *chip = bus->private_data; + unsigned int addr = azx_command_addr(val); + unsigned int wp; + + spin_lock_irq(&chip->reg_lock); + + /* add command to corb */ + wp = azx_readb(chip, CORBWP); + wp++; + wp %= ICH6_MAX_CORB_ENTRIES; + + chip->rirb.cmds[addr]++; + chip->corb.buf[wp] = cpu_to_le32(val); + wmb(); + azx_writel(chip, CORBWP, wp); + + spin_unlock_irq(&chip->reg_lock); + + return 0; +} + +#define ICH6_RIRB_EX_UNSOL_EV (1<<4) + +/* retrieve RIRB entry - called from interrupt handler */ +void azx_update_rirb(struct azx *chip) +{ + unsigned int rp, wp; + unsigned int addr; + u32 res, res_ex; + + wp = azx_readb(chip, RIRBWP); + if (wp == chip->rirb.wp) + return; + chip->rirb.wp = wp; + + while (chip->rirb.rp != wp) { + chip->rirb.rp++; + chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; + + rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ + res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); + res = le32_to_cpu(chip->rirb.buf[rp]); + addr = azx_response_addr(res_ex); + if (res_ex & ICH6_RIRB_EX_UNSOL_EV) + snd_hda_queue_unsol_event(chip->bus, res, res_ex); + else if (chip->rirb.cmds[addr]) { + chip->rirb.res[addr] = res; + smp_wmb(); + chip->rirb.cmds[addr]--; + } else + snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " + "last cmd=%#08x\n", + res, res_ex, + chip->last_cmd[addr]); + } +} + +/* receive a response */ +unsigned int azx_rirb_get_response(struct hda_bus *bus, + unsigned int addr) +{ + struct azx *chip = bus->private_data; + unsigned long timeout; + int do_poll = 0; + + again: + timeout = jiffies + msecs_to_jiffies(1000); + for (;;) { + if (chip->polling_mode || do_poll) { + spin_lock_irq(&chip->reg_lock); + azx_update_rirb(chip); + spin_unlock_irq(&chip->reg_lock); + } + if (!chip->rirb.cmds[addr]) { + smp_rmb(); + bus->rirb_error = 0; + + if (!do_poll) + chip->poll_count = 0; + return chip->rirb.res[addr]; /* the last value */ + } + if (time_after(jiffies, timeout)) + break; + if (bus->needs_damn_long_delay) + msleep(2); /* temporary workaround */ + else { + udelay(10); + cond_resched(); + } + } + + if (!chip->polling_mode && chip->poll_count < 2) { + snd_printdd(SFX "azx_get_response timeout, " + "polling the codec once: last cmd=0x%08x\n", + chip->last_cmd[addr]); + do_poll = 1; + chip->poll_count++; + goto again; + } + + + if (!chip->polling_mode) { + snd_printk(KERN_WARNING SFX "azx_get_response timeout, " + "switching to polling mode: last cmd=0x%08x\n", + chip->last_cmd[addr]); + chip->polling_mode = 1; + goto again; + } +#if !defined(CONFIG_SND_HDA_TEGRA) + if (chip->msi) { + snd_printk(KERN_WARNING SFX "No response from codec, " + "disabling MSI: last cmd=0x%08x\n", + chip->last_cmd[addr]); + free_irq(chip->irq, chip); + chip->irq = -1; + pci_disable_msi(chip->pci); + chip->msi = 0; + if (azx_acquire_irq(chip, 1) < 0) { + bus->rirb_error = 1; + return -1; + } + goto again; + } +#endif /* !CONFIG_SND_HDA_TEGRA */ + + if (chip->probing) { + /* If this critical timeout happens during the codec probing + * phase, this is likely an access to a non-existing codec + * slot. Better to return an error and reset the system. + */ + return -1; + } + + /* a fatal communication error; need either to reset or to fallback + * to the single_cmd mode + */ + bus->rirb_error = 1; + if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { + bus->response_reset = 1; + return -1; /* give a chance to retry */ + } + + snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " + "switching to single_cmd mode: last cmd=0x%08x\n", + chip->last_cmd[addr]); + chip->single_cmd = 1; + bus->response_reset = 0; + /* release CORB/RIRB */ + azx_free_cmd_io(chip); + /* disable unsolicited responses */ + azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); + return -1; +} + +/* + * Use the single immediate command instead of CORB/RIRB for simplicity + * + * Note: according to Intel, this is not preferred use. The command was + * intended for the BIOS only, and may get confused with unsolicited + * responses. So, we shouldn't use it for normal operation from the + * driver. + * I left the codes, however, for debugging/testing purposes. + */ + +/* receive a response */ +int azx_single_wait_for_response(struct azx *chip, unsigned int addr) +{ + int timeout = 50; + + while (timeout--) { + /* check IRV busy bit */ + if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { + /* reuse rirb.res as the response return value */ + chip->rirb.res[addr] = azx_readl(chip, IR); + return 0; + } + udelay(1); + } + if (printk_ratelimit()) + snd_printd(SFX "get_response timeout: IRS=0x%x\n", + azx_readw(chip, IRS)); + chip->rirb.res[addr] = -1; + return -EIO; +} + +/* send a command */ +int azx_single_send_cmd(struct hda_bus *bus, u32 val) +{ + struct azx *chip = bus->private_data; + unsigned int addr = azx_command_addr(val); + int timeout = 50; + + bus->rirb_error = 0; + while (timeout--) { + /* check ICB busy bit */ + if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { + /* Clear IRV valid bit */ + azx_writew(chip, IRS, azx_readw(chip, IRS) | + ICH6_IRS_VALID); + azx_writel(chip, IC, val); + azx_writew(chip, IRS, azx_readw(chip, IRS) | + ICH6_IRS_BUSY); + return azx_single_wait_for_response(chip, addr); + } + udelay(1); + } + if (printk_ratelimit()) + snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", + azx_readw(chip, IRS), val); + return -EIO; +} + +/* receive a response */ +unsigned int azx_single_get_response(struct hda_bus *bus, + unsigned int addr) +{ + struct azx *chip = bus->private_data; + return chip->rirb.res[addr]; +} + +/* + * The below are the main callbacks from hda_codec. + * + * They are just the skeleton to call sub-callbacks according to the + * current setting of chip->single_cmd. + */ + +/* send a command */ +int azx_send_cmd(struct hda_bus *bus, unsigned int val) +{ + struct azx *chip = bus->private_data; + + chip->last_cmd[azx_command_addr(val)] = val; + if (chip->single_cmd) + return azx_single_send_cmd(bus, val); + else + return azx_corb_send_cmd(bus, val); +} + +/* get a response */ +unsigned int azx_get_response(struct hda_bus *bus, + unsigned int addr) +{ + struct azx *chip = bus->private_data; + if (chip->single_cmd) + return azx_single_get_response(bus, addr); + else + return azx_rirb_get_response(bus, addr); +} + +#ifdef CONFIG_SND_HDA_POWER_SAVE +void azx_power_notify(struct hda_bus *bus); +#endif + +/* reset codec link */ + int azx_reset(struct azx *chip, int full_reset) +{ + int count; + + if (!full_reset) + goto __skip; + + /* clear STATESTS */ + azx_writeb(chip, STATESTS, STATESTS_INT_MASK); + + /* reset controller */ + azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); + + count = 50; + while (azx_readb(chip, GCTL) && --count) + msleep(1); + + /* delay for >= 100us for codec PLL to settle per spec + * Rev 0.9 section 5.5.1 + */ + msleep(1); + + /* Bring controller out of reset */ + azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); + + count = 50; + while (!azx_readb(chip, GCTL) && --count) + msleep(1); + + /* Brent Chartrand said to wait >= 540us for codecs to initialize */ + msleep(1); + + __skip: + /* check to see if controller is ready */ + if (!azx_readb(chip, GCTL)) { + snd_printd(SFX "azx_reset: controller not ready!\n"); + return -EBUSY; + } + + /* Accept unsolicited responses */ + if (!chip->single_cmd) + azx_writel(chip, GCTL, azx_readl(chip, GCTL) | + ICH6_GCTL_UNSOL); + + /* detect codecs */ + if (!chip->codec_mask) { + chip->codec_mask = azx_readw(chip, STATESTS); + snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask); + } + + return 0; +} + + +/* + * Lowlevel interface + */ + +/* enable interrupts */ +void azx_int_enable(struct azx *chip) +{ + /* enable controller CIE and GIE */ + azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | + ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); +} + +/* disable interrupts */ +void azx_int_disable(struct azx *chip) +{ + int i; + + /* disable interrupts in stream descriptor */ + for (i = 0; i < chip->num_streams; i++) { + struct azx_dev *azx_dev = &chip->azx_dev[i]; + azx_sd_writeb(azx_dev, SD_CTL, + azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); + } + + /* disable SIE for all streams */ + azx_writeb(chip, INTCTL, 0); + + /* disable controller CIE and GIE */ + azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & + ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); +} + +/* clear interrupts */ +void azx_int_clear(struct azx *chip) +{ + int i; + + /* clear stream status */ + for (i = 0; i < chip->num_streams; i++) { + struct azx_dev *azx_dev = &chip->azx_dev[i]; + azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); + } + + /* clear STATESTS */ + azx_writeb(chip, STATESTS, STATESTS_INT_MASK); + + /* clear rirb status */ + azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); + + /* clear int status */ + azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); +} + +/* start a stream */ +void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) +{ + /* + * Before stream start, initialize parameter + */ + azx_dev->insufficient = 1; + + /* enable SIE */ + azx_writel(chip, INTCTL, + azx_readl(chip, INTCTL) | (1 << azx_dev->index)); + /* set DMA start and interrupt mask */ + azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | + SD_CTL_DMA_START | SD_INT_MASK); +} + +/* stop DMA */ +void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) +{ + azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & + ~(SD_CTL_DMA_START | SD_INT_MASK)); + azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ +} + +/* stop a stream */ +void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) +{ + azx_stream_clear(chip, azx_dev); + /* disable SIE */ + azx_writel(chip, INTCTL, + azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); +} + + +/* + * reset and start the controller registers + */ + void azx_init_chip(struct azx *chip, int full_reset) +{ + if (chip->initialized) + return; + + /* reset controller */ + azx_reset(chip, full_reset); + + /* initialize interrupts */ + azx_int_clear(chip); + azx_int_enable(chip); + + /* initialize the codec command I/O */ + if (!chip->single_cmd) + azx_init_cmd_io(chip); + + /* program the position buffer */ + azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); + azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); + + chip->initialized = 1; +} + +int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); + +/* + * interrupt handler + */ +irqreturn_t azx_interrupt(int irq, void *dev_id) +{ + struct azx *chip = dev_id; + struct azx_dev *azx_dev; + u32 status; + u8 sd_status; + int i, ok; + + spin_lock(&chip->reg_lock); + + status = azx_readl(chip, INTSTS); + if (status == 0) { + spin_unlock(&chip->reg_lock); + return IRQ_NONE; + } + + for (i = 0; i < chip->num_streams; i++) { + azx_dev = &chip->azx_dev[i]; + if (status & azx_dev->sd_int_sta_mask) { + sd_status = azx_sd_readb(azx_dev, SD_STS); + azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); + if (!azx_dev->substream || !azx_dev->running || + !(sd_status & SD_INT_COMPLETE)) + continue; + /* check whether this IRQ is really acceptable */ + ok = azx_position_ok(chip, azx_dev); + if (ok == 1) { + azx_dev->irq_pending = 0; + spin_unlock(&chip->reg_lock); + snd_pcm_period_elapsed(azx_dev->substream); + spin_lock(&chip->reg_lock); + } else if (ok == 0 && chip->bus && chip->bus->workq) { + /* bogus IRQ, process it later */ + azx_dev->irq_pending = 1; + queue_work(chip->bus->workq, + &chip->irq_pending_work); + } + } + } + + /* clear rirb int */ + status = azx_readb(chip, RIRBSTS); + if (status & RIRB_INT_MASK) { + if (status & RIRB_INT_RESPONSE) { + if (chip->driver_type == AZX_DRIVER_CTX) + udelay(80); + azx_update_rirb(chip); + } + azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); + } + +#if 0 + /* clear state status int */ + if (azx_readb(chip, STATESTS) & 0x04) + azx_writeb(chip, STATESTS, 0x04); +#endif + spin_unlock(&chip->reg_lock); + + return IRQ_HANDLED; +} + + +/* + * set up a BDL entry + */ +int setup_bdle(struct snd_pcm_substream *substream, + struct azx_dev *azx_dev, u32 **bdlp, + int ofs, int size, int with_ioc) +{ + u32 *bdl = *bdlp; + + while (size > 0) { + dma_addr_t addr; + int chunk; + + if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) + return -EINVAL; + + addr = snd_pcm_sgbuf_get_addr(substream, ofs); + /* program the address field of the BDL entry */ + bdl[0] = cpu_to_le32((u32)addr); + bdl[1] = cpu_to_le32(upper_32_bits(addr)); + /* program the size field of the BDL entry */ + chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size); + bdl[2] = cpu_to_le32(chunk); + /* program the IOC to enable interrupt + * only when the whole fragment is processed + */ + size -= chunk; + bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); + bdl += 4; + azx_dev->frags++; + ofs += chunk; + } + *bdlp = bdl; + return ofs; +} + +/* reset stream */ +void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) +{ + unsigned char val; + int timeout; + + azx_stream_clear(chip, azx_dev); + + azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | + SD_CTL_STREAM_RESET); + udelay(3); + timeout = 300; + while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && + --timeout) + ; + val &= ~SD_CTL_STREAM_RESET; + azx_sd_writeb(azx_dev, SD_CTL, val); + udelay(3); + + timeout = 300; + /* waiting for hardware to report that the stream is out of reset */ + while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && + --timeout) + ; + + /* reset first position - may not be synced with hw at this time */ + *azx_dev->posbuf = 0; +} + +/* + * set up the SD for streaming + */ +int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) +{ + /* make sure the run bit is zero for SD */ + azx_stream_clear(chip, azx_dev); + /* program the stream_tag */ + azx_sd_writel(azx_dev, SD_CTL, + (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| + (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); + + /* program the length of samples in cyclic buffer */ + azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); + + /* program the stream format */ + /* this value needs to be the same as the one programmed */ + azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); + + /* program the stream LVI (last valid index) of the BDL */ + azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); + + /* program the BDL address */ + /* lower BDL address */ + azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); + /* upper BDL address */ + azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); + + /* enable the position buffer */ + if (chip->position_fix[0] == POS_FIX_POSBUF || + chip->position_fix[0] == POS_FIX_AUTO || + chip->position_fix[1] == POS_FIX_POSBUF || + chip->position_fix[1] == POS_FIX_AUTO || + chip->via_dmapos_patch) { + if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) + azx_writel(chip, DPLBASE, + (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); + } + + /* set the interrupt enable bits in the descriptor control register */ + azx_sd_writel(azx_dev, SD_CTL, + azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); + + return 0; +} + +/* + * Probe the given codec address + */ +int probe_codec(struct azx *chip, int addr) +{ + unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | + (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; + unsigned int res; + + mutex_lock(&chip->bus->cmd_mutex); + chip->probing = 1; + azx_send_cmd(chip->bus, cmd); + res = azx_get_response(chip->bus, addr); + chip->probing = 0; + mutex_unlock(&chip->bus->cmd_mutex); + if (res == -1) + return -EIO; + snd_printdd(SFX "codec #%d probed OK\n", addr); + return 0; +} + +void azx_stop_chip(struct azx *chip); + +void azx_bus_reset(struct hda_bus *bus) +{ + struct azx *chip = bus->private_data; + + bus->in_reset = 1; + azx_stop_chip(chip); + azx_init_chip(chip, 1); +#ifdef CONFIG_PM + if (chip->initialized) { + int i; + + for (i = 0; i < HDA_MAX_PCMS; i++) + snd_pcm_suspend_all(chip->pcm[i]); + snd_hda_suspend(chip->bus); + snd_hda_resume(chip->bus); + } +#endif + bus->in_reset = 0; +} + +/* configure each codec instance */ +int __devinit azx_codec_configure(struct azx *chip) +{ + struct hda_codec *codec; + list_for_each_entry(codec, &chip->bus->codec_list, list) { + snd_hda_codec_configure(codec); + } + return 0; +} + + +/* + * PCM support + */ + +/* assign a stream for the PCM */ +inline struct azx_dev * +azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) +{ + int dev, i, nums; + struct azx_dev *res = NULL; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + dev = chip->playback_index_offset; + nums = chip->playback_streams; + } else { + dev = chip->capture_index_offset; + nums = chip->capture_streams; + } + for (i = 0; i < nums; i++, dev++) + if (!chip->azx_dev[dev].opened) { + res = &chip->azx_dev[dev]; + if (res->device == substream->pcm->device) + break; + } + if (res) { + res->opened = 1; + res->device = substream->pcm->device; + } + return res; +} + +/* release the assigned stream */ +inline void azx_release_device(struct azx_dev *azx_dev) +{ + azx_dev->opened = 0; +} + +static struct snd_pcm_hardware azx_pcm_hw = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP_VALID | + /* No full-resume yet implemented */ + /* SNDRV_PCM_INFO_RESUME |*/ + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_SYNC_START), + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = AZX_MAX_BUF_SIZE, + .period_bytes_min = 128, + .period_bytes_max = AZX_MAX_BUF_SIZE / 2, + .periods_min = 2, + .periods_max = AZX_MAX_FRAG, + .fifo_size = 0, +}; + +int azx_pcm_open(struct snd_pcm_substream *substream) +{ + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; + struct azx *chip = apcm->chip; + struct azx_dev *azx_dev; + struct snd_pcm_runtime *runtime = substream->runtime; + unsigned long flags; + int err; + + mutex_lock(&chip->open_mutex); + azx_dev = azx_assign_device(chip, substream); + if (azx_dev == NULL) { + mutex_unlock(&chip->open_mutex); + return -EBUSY; + } + runtime->hw = azx_pcm_hw; + runtime->hw.channels_min = hinfo->channels_min; + runtime->hw.channels_max = hinfo->channels_max; + runtime->hw.formats = hinfo->formats; + runtime->hw.rates = hinfo->rates; + snd_pcm_limit_hw_rates(runtime); + snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, + 128); + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, + 128); + snd_hda_power_up(apcm->codec); + err = hinfo->ops.open(hinfo, apcm->codec, substream); + if (err < 0) { + azx_release_device(azx_dev); + snd_hda_power_down(apcm->codec); + mutex_unlock(&chip->open_mutex); + return err; + } + snd_pcm_limit_hw_rates(runtime); + /* sanity check */ + if (snd_BUG_ON(!runtime->hw.channels_min) || + snd_BUG_ON(!runtime->hw.channels_max) || + snd_BUG_ON(!runtime->hw.formats) || + snd_BUG_ON(!runtime->hw.rates)) { + azx_release_device(azx_dev); + hinfo->ops.close(hinfo, apcm->codec, substream); + snd_hda_power_down(apcm->codec); + mutex_unlock(&chip->open_mutex); + return -EINVAL; + } + spin_lock_irqsave(&chip->reg_lock, flags); + azx_dev->substream = substream; + azx_dev->running = 0; + spin_unlock_irqrestore(&chip->reg_lock, flags); + + runtime->private_data = azx_dev; + snd_pcm_set_sync(substream); + mutex_unlock(&chip->open_mutex); + return 0; +} + +int azx_pcm_close(struct snd_pcm_substream *substream) +{ + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; + struct azx *chip = apcm->chip; + struct azx_dev *azx_dev = get_azx_dev(substream); + unsigned long flags; + + mutex_lock(&chip->open_mutex); + spin_lock_irqsave(&chip->reg_lock, flags); + azx_dev->substream = NULL; + azx_dev->running = 0; + spin_unlock_irqrestore(&chip->reg_lock, flags); + azx_release_device(azx_dev); + hinfo->ops.close(hinfo, apcm->codec, substream); + snd_hda_power_down(apcm->codec); + mutex_unlock(&chip->open_mutex); + return 0; +} + +int azx_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + struct azx_dev *azx_dev = get_azx_dev(substream); + + azx_dev->bufsize = 0; + azx_dev->period_bytes = 0; + azx_dev->format_val = 0; + return snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); +} + +int azx_pcm_hw_free(struct snd_pcm_substream *substream) +{ + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct azx_dev *azx_dev = get_azx_dev(substream); + struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; + + /* reset BDL address */ + azx_sd_writel(azx_dev, SD_BDLPL, 0); + azx_sd_writel(azx_dev, SD_BDLPU, 0); + azx_sd_writel(azx_dev, SD_CTL, 0); + azx_dev->bufsize = 0; + azx_dev->period_bytes = 0; + azx_dev->format_val = 0; + + snd_hda_codec_cleanup(apcm->codec, hinfo, substream); + + return snd_pcm_lib_free_pages(substream); +} + +int azx_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct azx *chip = apcm->chip; + struct azx_dev *azx_dev = get_azx_dev(substream); + struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; + struct snd_pcm_runtime *runtime = substream->runtime; + unsigned int bufsize, period_bytes, format_val, stream_tag; + int err; + + azx_stream_reset(chip, azx_dev); + format_val = snd_hda_calc_stream_format(runtime->rate, + runtime->channels, + runtime->format, + hinfo->maxbps, + apcm->codec->spdif_ctls); + if (!format_val) { + snd_printk(KERN_ERR SFX + "invalid format_val, rate=%d, ch=%d, format=%d\n", + runtime->rate, runtime->channels, runtime->format); + return -EINVAL; + } + + bufsize = snd_pcm_lib_buffer_bytes(substream); + period_bytes = snd_pcm_lib_period_bytes(substream); + + snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", + bufsize, format_val); + + if (bufsize != azx_dev->bufsize || + period_bytes != azx_dev->period_bytes || + format_val != azx_dev->format_val) { + azx_dev->bufsize = bufsize; + azx_dev->period_bytes = period_bytes; + azx_dev->format_val = format_val; + err = azx_setup_periods(chip, substream, azx_dev); + if (err < 0) + return err; + } + + /* wallclk has 24Mhz clock source */ + azx_dev->period_wallclk = (((runtime->period_size * 24000) / + runtime->rate) * 1000); + azx_setup_controller(chip, azx_dev); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; + else + azx_dev->fifo_size = 0; + + stream_tag = azx_dev->stream_tag; + /* CA-IBG chips need the playback stream starting from 1 */ + if (chip->driver_type == AZX_DRIVER_CTX && + stream_tag > chip->capture_streams) + stream_tag -= chip->capture_streams; + return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, + azx_dev->format_val, substream); +} + +int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct azx *chip = apcm->chip; + struct azx_dev *azx_dev; + struct snd_pcm_substream *s; + int rstart = 0, start, nsync = 0, sbits = 0; + int nwait, timeout; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + rstart = 1; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_RESUME: + start = 1; + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + start = 0; + break; + default: + return -EINVAL; + } + + snd_pcm_group_for_each_entry(s, substream) { + if (s->pcm->card != substream->pcm->card) + continue; + azx_dev = get_azx_dev(s); + sbits |= 1 << azx_dev->index; + nsync++; + snd_pcm_trigger_done(s, substream); + } + + spin_lock(&chip->reg_lock); + if (nsync > 1) { + /* first, set SYNC bits of corresponding streams */ + azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); + } + snd_pcm_group_for_each_entry(s, substream) { + if (s->pcm->card != substream->pcm->card) + continue; + azx_dev = get_azx_dev(s); + if (start) { + azx_dev->start_wallclk = azx_readl(chip, WALLCLK); + if (!rstart) + azx_dev->start_wallclk -= + azx_dev->period_wallclk; + azx_stream_start(chip, azx_dev); + } else { + azx_stream_stop(chip, azx_dev); + } + azx_dev->running = start; + } + spin_unlock(&chip->reg_lock); + if (start) { + if (nsync == 1) + return 0; + /* wait until all FIFOs get ready */ + for (timeout = 5000; timeout; timeout--) { + nwait = 0; + snd_pcm_group_for_each_entry(s, substream) { + if (s->pcm->card != substream->pcm->card) + continue; + azx_dev = get_azx_dev(s); + if (!(azx_sd_readb(azx_dev, SD_STS) & + SD_STS_FIFO_READY)) + nwait++; + } + if (!nwait) + break; + cpu_relax(); + } + } else { + /* wait until all RUN bits are cleared */ + for (timeout = 5000; timeout; timeout--) { + nwait = 0; + snd_pcm_group_for_each_entry(s, substream) { + if (s->pcm->card != substream->pcm->card) + continue; + azx_dev = get_azx_dev(s); + if (azx_sd_readb(azx_dev, SD_CTL) & + SD_CTL_DMA_START) + nwait++; + } + if (!nwait) + break; + cpu_relax(); + } + } + if (nsync > 1) { + spin_lock(&chip->reg_lock); + /* reset SYNC bits */ + azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); + spin_unlock(&chip->reg_lock); + } + return 0; +} + +/* get the current DMA position with correction on VIA chips */ +unsigned int azx_via_get_position(struct azx *chip, + struct azx_dev *azx_dev) +{ + unsigned int link_pos, mini_pos, bound_pos; + unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; + unsigned int fifo_size; + + link_pos = azx_sd_readl(azx_dev, SD_LPIB); + if (azx_dev->index >= 4) { + /* Playback, no problem using link position */ + return link_pos; + } + + /* Capture */ + /* For new chipset, + * use mod to get the DMA position just like old chipset + */ + mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); + mod_dma_pos %= azx_dev->period_bytes; + + /* azx_dev->fifo_size can't get FIFO size of in stream. + * Get from base address + offset. + */ + fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); + + if (azx_dev->insufficient) { + /* Link position never gather than FIFO size */ + if (link_pos <= fifo_size) + return 0; + + azx_dev->insufficient = 0; + } + + if (link_pos <= fifo_size) + mini_pos = azx_dev->bufsize + link_pos - fifo_size; + else + mini_pos = link_pos - fifo_size; + + /* Find nearest previous boudary */ + mod_mini_pos = mini_pos % azx_dev->period_bytes; + mod_link_pos = link_pos % azx_dev->period_bytes; + if (mod_link_pos >= fifo_size) + bound_pos = link_pos - mod_link_pos; + else if (mod_dma_pos >= mod_mini_pos) + bound_pos = mini_pos - mod_mini_pos; + else { + bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; + if (bound_pos >= azx_dev->bufsize) + bound_pos = 0; + } + + /* Calculate real DMA position we want */ + return bound_pos + mod_dma_pos; +} + +unsigned int azx_get_position(struct azx *chip, + struct azx_dev *azx_dev) +{ + unsigned int pos; + + if (chip->via_dmapos_patch) + pos = azx_via_get_position(chip, azx_dev); + else { + int stream = azx_dev->substream->stream; + if (chip->position_fix[stream] == POS_FIX_POSBUF || + chip->position_fix[stream] == POS_FIX_AUTO) { + /* use the position buffer */ + pos = le32_to_cpu(*azx_dev->posbuf); + } else { + /* read LPIB */ + pos = azx_sd_readl(azx_dev, SD_LPIB); + } + } + if (pos >= azx_dev->bufsize) + pos = 0; + return pos; +} + +snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct azx *chip = apcm->chip; + struct azx_dev *azx_dev = get_azx_dev(substream); + return bytes_to_frames(substream->runtime, + azx_get_position(chip, azx_dev)); +} + +/* + * The work for pending PCM period updates. + */ +void azx_irq_pending_work(struct work_struct *work) +{ + struct azx *chip = container_of(work, struct azx, irq_pending_work); + int i, pending, ok; + + if (!chip->irq_pending_warned) { + printk(KERN_WARNING + "hda-intel: IRQ timing workaround is activated " + "for card #%d. Suggest a bigger bdl_pos_adj.\n", + chip->card->number); + chip->irq_pending_warned = 1; + } + + for (;;) { + pending = 0; + spin_lock_irq(&chip->reg_lock); + for (i = 0; i < chip->num_streams; i++) { + struct azx_dev *azx_dev = &chip->azx_dev[i]; + if (!azx_dev->irq_pending || + !azx_dev->substream || + !azx_dev->running) + continue; + ok = azx_position_ok(chip, azx_dev); + if (ok > 0) { + azx_dev->irq_pending = 0; + spin_unlock(&chip->reg_lock); + snd_pcm_period_elapsed(azx_dev->substream); + spin_lock(&chip->reg_lock); + } else if (ok < 0) { + pending = 0; /* too early */ + } else + pending++; + } + spin_unlock_irq(&chip->reg_lock); + if (!pending) + return; + msleep(1); + } +} + +/* clear irq_pending flags and assure no on-going workq */ +void azx_clear_irq_pending(struct azx *chip) +{ + int i; + + spin_lock_irq(&chip->reg_lock); + for (i = 0; i < chip->num_streams; i++) + chip->azx_dev[i].irq_pending = 0; + spin_unlock_irq(&chip->reg_lock); +} + +void azx_pcm_free(struct snd_pcm *pcm) +{ + struct azx_pcm *apcm = pcm->private_data; + if (apcm) { + apcm->chip->pcm[pcm->device] = NULL; + kfree(apcm); + } +} + +/* + * mixer creation - all stuff is implemented in hda module + */ +int __devinit azx_mixer_create(struct azx *chip) +{ + return snd_hda_build_controls(chip->bus); +} + + +/* + * initialize SD streams + */ +int __devinit azx_init_stream(struct azx *chip) +{ + int i; + + /* initialize each stream (aka device) + * assign the starting bdl address to each stream (device) + * and initialize + */ + for (i = 0; i < chip->num_streams; i++) { + struct azx_dev *azx_dev = &chip->azx_dev[i]; + azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); + /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ + azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); + /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ + azx_dev->sd_int_sta_mask = 1 << i; + /* stream tag: must be non-zero and unique */ + azx_dev->index = i; + azx_dev->stream_tag = i + 1; + } + + return 0; +} + +#if !defined(CONFIG_SND_HDA_TEGRA) +int azx_acquire_irq(struct azx *chip, int do_disconnect) +{ + if (request_irq(chip->pci->irq, azx_interrupt, + chip->msi ? 0 : IRQF_SHARED, + "hda_intel", chip)) { + printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " + "disabling device\n", chip->pci->irq); + if (do_disconnect) + snd_card_disconnect(chip->card); + return -1; + } + chip->irq = chip->pci->irq; + pci_intx(chip->pci, !chip->msi); + return 0; +} +#else +int azx_acquire_irq(struct azx *chip, int do_disconnect) +{ + chip->irq = platform_get_irq(chip->pdev, 0); + if (request_irq(chip->irq, azx_interrupt, + chip->msi ? 0 : IRQF_SHARED, + "tegra-hda", chip)) { + printk(KERN_ERR "hda-tegra: unable to grab IRQ %d, " + "disabling device\n", chip->irq); + if (do_disconnect) + snd_card_disconnect(chip->card); + return -1; + } + return 0; +} +#endif /* !CONFIG_SND_HDA_TEGRA */ + +void azx_stop_chip(struct azx *chip) +{ + if (!chip->initialized) + return; + + /* disable interrupts */ + azx_int_disable(chip); + azx_int_clear(chip); + + /* disable CORB/RIRB */ + azx_free_cmd_io(chip); + + /* disable position buffer */ + azx_writel(chip, DPLBASE, 0); + azx_writel(chip, DPUBASE, 0); + + chip->initialized = 0; +} + +#ifdef CONFIG_SND_HDA_POWER_SAVE +/* power-up/down the controller */ +void azx_power_notify(struct hda_bus *bus) +{ + struct azx *chip = bus->private_data; + struct hda_codec *c; + int power_on = 0; + + list_for_each_entry(c, &bus->codec_list, list) { + if (c->power_on) { + power_on = 1; + break; + } + } + if (power_on) + azx_init_chip(chip, 1); + else if (chip->running && power_save_controller && + !bus->power_keep_link_on) + azx_stop_chip(chip); +} +#endif /* CONFIG_SND_HDA_POWER_SAVE */ + +#ifdef CONFIG_PM +/* + * power management + */ + +int snd_hda_codecs_inuse(struct hda_bus *bus) +{ + struct hda_codec *codec; + + list_for_each_entry(codec, &bus->codec_list, list) { + if (snd_hda_codec_needs_resume(codec)) + return 1; + } + return 0; +} + +#endif /* CONFIG_PM */ + + +/* + * reboot notifier for hang-up problem at power-down + */ +int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) +{ + struct azx *chip = container_of(nb, struct azx, reboot_notifier); + snd_hda_bus_reboot_notify(chip->bus); + azx_stop_chip(chip); + return NOTIFY_OK; +} + +void azx_notifier_register(struct azx *chip) +{ + chip->reboot_notifier.notifier_call = azx_halt; + register_reboot_notifier(&chip->reboot_notifier); +} + +void azx_notifier_unregister(struct azx *chip) +{ + if (chip->reboot_notifier.notifier_call) + unregister_reboot_notifier(&chip->reboot_notifier); +} + +void power_down_all_codecs(struct azx *chip) +{ +#ifdef CONFIG_SND_HDA_POWER_SAVE + /* The codecs were powered up in snd_hda_codec_new(). + * Now all initialization done, so turn them down if possible + */ + struct hda_codec *codec; + list_for_each_entry(codec, &chip->bus->codec_list, list) { + snd_hda_power_down(codec); + } +#endif +} diff --git a/sound/pci/hda/lib_hda_intel.h b/sound/pci/hda/lib_hda_intel.h new file mode 100644 index 000000000000..adf3bd1a3f1c --- /dev/null +++ b/sound/pci/hda/lib_hda_intel.h @@ -0,0 +1,621 @@ +/* + * Copyright(c) 2004 Intel Corporation. All rights reserved. + * + * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> + * PeiSen Hou <pshou@realtek.com.tw> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * CONTACTS: + * + * Matt Jared matt.jared@intel.com + * Andy Kopp andy.kopp@intel.com + * Dan Kogan dan.d.kogan@intel.com + * + */ + +#ifndef __LINUX_LIB_HDA_INTEL_H__ +#define __LINUX_LIB_HDA_INTEL_H__ + +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/dma-mapping.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/pci.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/reboot.h> +#include <sound/core.h> +#include <sound/initval.h> +#include "hda_codec.h" + +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," + "{Intel, ICH6M}," + "{Intel, ICH7}," + "{Intel, ESB2}," + "{Intel, ICH8}," + "{Intel, ICH9}," + "{Intel, ICH10}," + "{Intel, PCH}," + "{Intel, CPT}," + "{Intel, PBG}," + "{Intel, SCH}," + "{ATI, SB450}," + "{ATI, SB600}," + "{ATI, RS600}," + "{ATI, RS690}," + "{ATI, RS780}," + "{ATI, R600}," + "{ATI, RV630}," + "{ATI, RV610}," + "{ATI, RV670}," + "{ATI, RV635}," + "{ATI, RV620}," + "{ATI, RV770}," + "{VIA, VT8251}," + "{VIA, VT8237A}," + "{SiS, SIS966}," + "{ULI, M5461}}"); +MODULE_DESCRIPTION("Intel HDA driver"); + +#ifdef CONFIG_SND_VERBOSE_PRINTK +#define SFX /* nop */ +#else +#define SFX "hda-intel: " +#endif + +/* + * registers + */ +#define ICH6_REG_GCAP 0x00 +#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ +#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ +#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ +#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ +#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ +#define ICH6_REG_VMIN 0x02 +#define ICH6_REG_VMAJ 0x03 +#define ICH6_REG_OUTPAY 0x04 +#define ICH6_REG_INPAY 0x06 +#define ICH6_REG_GCTL 0x08 +#define ICH6_GCTL_RESET (1 << 0) /* controller reset */ +#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ +#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ +#define ICH6_REG_WAKEEN 0x0c +#define ICH6_REG_STATESTS 0x0e +#define ICH6_REG_GSTS 0x10 +#define ICH6_GSTS_FSTS (1 << 1) /* flush status */ +#define ICH6_REG_INTCTL 0x20 +#define ICH6_REG_INTSTS 0x24 +#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ +#define ICH6_REG_SYNC 0x34 +#define ICH6_REG_CORBLBASE 0x40 +#define ICH6_REG_CORBUBASE 0x44 +#define ICH6_REG_CORBWP 0x48 +#define ICH6_REG_CORBRP 0x4a +#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ +#define ICH6_REG_CORBCTL 0x4c +#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ +#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ +#define ICH6_REG_CORBSTS 0x4d +#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ +#define ICH6_REG_CORBSIZE 0x4e + +#define ICH6_REG_RIRBLBASE 0x50 +#define ICH6_REG_RIRBUBASE 0x54 +#define ICH6_REG_RIRBWP 0x58 +#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ +#define ICH6_REG_RINTCNT 0x5a +#define ICH6_REG_RIRBCTL 0x5c +#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ +#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ +#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ +#define ICH6_REG_RIRBSTS 0x5d +#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ +#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ +#define ICH6_REG_RIRBSIZE 0x5e + +#define ICH6_REG_IC 0x60 +#define ICH6_REG_IR 0x64 +#define ICH6_REG_IRS 0x68 +#define ICH6_IRS_VALID (1<<1) +#define ICH6_IRS_BUSY (1<<0) + +#define ICH6_REG_DPLBASE 0x70 +#define ICH6_REG_DPUBASE 0x74 +#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ + +/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ +enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; + +/* stream register offsets from stream base */ +#define ICH6_REG_SD_CTL 0x00 +#define ICH6_REG_SD_STS 0x03 +#define ICH6_REG_SD_LPIB 0x04 +#define ICH6_REG_SD_CBL 0x08 +#define ICH6_REG_SD_LVI 0x0c +#define ICH6_REG_SD_FIFOW 0x0e +#define ICH6_REG_SD_FIFOSIZE 0x10 +#define ICH6_REG_SD_FORMAT 0x12 +#define ICH6_REG_SD_BDLPL 0x18 +#define ICH6_REG_SD_BDLPU 0x1c + +/* PCI space */ +#define ICH6_PCIREG_TCSEL 0x44 + +/* + * other constants + */ + +/* max number of SDs */ +/* ICH, ATI and VIA have 4 playback and 4 capture */ +#define ICH6_NUM_CAPTURE 4 +#define ICH6_NUM_PLAYBACK 4 + +/* ULI has 6 playback and 5 capture */ +#define ULI_NUM_CAPTURE 5 +#define ULI_NUM_PLAYBACK 6 + +/* ATI HDMI has 1 playback and 0 capture */ +#define ATIHDMI_NUM_CAPTURE 0 +#define ATIHDMI_NUM_PLAYBACK 1 + +/* TERA has 4 playback and 3 capture */ +#define TERA_NUM_CAPTURE 3 +#define TERA_NUM_PLAYBACK 4 + +/* this number is statically defined for simplicity */ +#define MAX_AZX_DEV 16 + +/* max number of fragments - we may use more if allocating more pages for BDL */ +#define BDL_SIZE 4096 +#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) +#define AZX_MAX_FRAG 32 +/* max buffer size - no h/w limit, you can increase as you like */ +#define AZX_MAX_BUF_SIZE (1024*1024*1024) + +/* RIRB int mask: overrun[2], response[0] */ +#define RIRB_INT_RESPONSE 0x01 +#define RIRB_INT_OVERRUN 0x04 +#define RIRB_INT_MASK 0x05 + +/* STATESTS int mask: S3,SD2,SD1,SD0 */ +#define AZX_MAX_CODECS 8 +#define AZX_DEFAULT_CODECS 4 +#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) + +/* SD_CTL bits */ +#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ +#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ +#define SD_CTL_STRIPE (3 << 16) /* stripe control */ +#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ +#define SD_CTL_DIR (1 << 19) /* bi-directional stream */ +#define SD_CTL_STREAM_TAG_MASK (0xf << 20) +#define SD_CTL_STREAM_TAG_SHIFT 20 + +/* SD_CTL and SD_STS */ +#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ +#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ +#define SD_INT_COMPLETE 0x04 /* completion interrupt */ +#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ + SD_INT_COMPLETE) + +/* SD_STS */ +#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ + +/* INTCTL and INTSTS */ +#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ +#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ +#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ + +/* below are so far hardcoded - should read registers in future */ +#define ICH6_MAX_CORB_ENTRIES 256 +#define ICH6_MAX_RIRB_ENTRIES 256 + +/* position fix mode */ +enum { + POS_FIX_AUTO, + POS_FIX_LPIB, + POS_FIX_POSBUF, +}; + +/* Defines for ATI HD Audio support in SB450 south bridge */ +#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 +#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 + +/* Defines for Nvidia HDA support */ +#define NVIDIA_HDA_TRANSREG_ADDR 0x4e +#define NVIDIA_HDA_ENABLE_COHBITS 0x0f +#define NVIDIA_HDA_ISTRM_COH 0x4d +#define NVIDIA_HDA_OSTRM_COH 0x4c +#define NVIDIA_HDA_ENABLE_COHBIT 0x01 + +/* Defines for Intel SCH HDA snoop control */ +#define INTEL_SCH_HDA_DEVC 0x78 +#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) + +/* Define IN stream 0 FIFO size offset in VIA controller */ +#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 +/* Define VIA HD Audio Device ID*/ +#define VIA_HDAC_DEVICE_ID 0x3288 + +/* HD Audio class code */ +#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 + +/* + */ + +struct azx_dev { + struct snd_dma_buffer bdl; /* BDL buffer */ + u32 *posbuf; /* position buffer pointer */ + + unsigned int bufsize; /* size of the play buffer in bytes */ + unsigned int period_bytes; /* size of the period in bytes */ + unsigned int frags; /* number for period in the play buffer */ + unsigned int fifo_size; /* FIFO size */ + unsigned long start_wallclk; /* start + minimum wallclk */ + unsigned long period_wallclk; /* wallclk for period */ + + void __iomem *sd_addr; /* stream descriptor pointer */ + + u32 sd_int_sta_mask; /* stream int status mask */ + + /* pcm support */ + struct snd_pcm_substream *substream; /* assigned substream, + * set in PCM open + */ + unsigned int format_val; /* format value to be set in the + * controller and the codec + */ + unsigned char stream_tag; /* assigned stream */ + unsigned char index; /* stream index */ + int device; /* last device number assigned to */ + + unsigned int opened :1; + unsigned int running :1; + unsigned int irq_pending :1; + /* + * For VIA: + * A flag to ensure DMA position is 0 + * when link position is not greater than FIFO size + */ + unsigned int insufficient :1; +}; + +/* CORB/RIRB */ +struct azx_rb { + u32 *buf; /* CORB/RIRB buffer + * Each CORB entry is 4byte, RIRB is 8byte + */ + dma_addr_t addr; /* physical address of CORB/RIRB buffer */ + /* for RIRB */ + unsigned short rp, wp; /* read/write pointers */ + int cmds[AZX_MAX_CODECS]; /* number of pending requests */ + u32 res[AZX_MAX_CODECS]; /* last read value */ +}; + +struct azx { + struct snd_card *card; + struct pci_dev *pci; + struct platform_device *pdev; + int dev_index; + + /* chip type specific */ + int driver_type; + int playback_streams; + int playback_index_offset; + int capture_streams; + int capture_index_offset; + int num_streams; + + /* pci resources */ + unsigned long addr; + void __iomem *remap_addr; + void __iomem *pciconfig_addr; + int irq; + + /* locks */ + spinlock_t reg_lock; + struct mutex open_mutex; + + /* streams (x num_streams) */ + struct azx_dev *azx_dev; + + /* PCM */ + struct snd_pcm *pcm[HDA_MAX_PCMS]; + + /* HD codec */ + unsigned short codec_mask; + int codec_probe_mask; /* copied from probe_mask option */ + struct hda_bus *bus; + unsigned int beep_mode; + + /* CORB/RIRB */ + struct azx_rb corb; + struct azx_rb rirb; + + /* CORB/RIRB and position buffers */ + struct snd_dma_buffer rb; + struct snd_dma_buffer posbuf; + + /* flags */ + int position_fix[2]; /* for both playback/capture streams */ + int poll_count; + unsigned int running :1; + unsigned int initialized :1; + unsigned int single_cmd :1; + unsigned int polling_mode :1; + unsigned int msi :1; + unsigned int irq_pending_warned :1; + unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */ + unsigned int probing :1; /* codec probing phase */ + + /* for debugging */ + unsigned int last_cmd[AZX_MAX_CODECS]; + + /* for pending irqs */ + struct work_struct irq_pending_work; + + /* reboot notifier (for mysterious hangup problem at power-down) */ + struct notifier_block reboot_notifier; +}; + +/* driver types */ +enum { + AZX_DRIVER_ICH, + AZX_DRIVER_PCH, + AZX_DRIVER_SCH, + AZX_DRIVER_ATI, + AZX_DRIVER_ATIHDMI, + AZX_DRIVER_VIA, + AZX_DRIVER_SIS, + AZX_DRIVER_ULI, + AZX_DRIVER_NVIDIA, + AZX_DRIVER_TERA, + AZX_DRIVER_CTX, + AZX_DRIVER_GENERIC, + AZX_NUM_DRIVERS, /* keep this as last entry */ +}; + +/* + * macros for easy use + */ +#define azx_writel(chip,reg,value) \ + writel(value, (chip)->remap_addr + ICH6_REG_##reg) +#define azx_readl(chip,reg) \ + readl((chip)->remap_addr + ICH6_REG_##reg) + +#define azx_sd_writel(dev, reg, value) \ + writel(value, (dev)->sd_addr + ICH6_REG_##reg) +#define azx_sd_readl(dev, reg) \ + readl((dev)->sd_addr + ICH6_REG_##reg) + +#ifdef CONFIG_SND_HDA_TEGRA +#define MASK_D(reg) (ICH6_REG_##reg & 0xfc) +#define MASK_W(reg) (ICH6_REG_##reg & 0x02) +#define MASK_B(reg) (ICH6_REG_##reg & 0x03) +#define MASK_L_B 0xff +#define MASK_L_W 0xffff +#define reg_mask_byte(idx) \ + ((0xff000000 * ((idx == 3) ? 0 : 1)) + \ + (0xff0000 * ((idx == 2) ? 0 : 1)) + (0xff00 * ((idx == 1) ? 0 : 1)) \ + + (0xff * ((idx == 0) ? 0 : 1))) +#define reg_mask_word(idx) \ + (0xffff0000 * ((idx == 2) ? 0 : 1) + 0xffff * ((idx == 0) ? 0 : 1)) + +#define nv_readl(chip, reg) \ + readl((chip)->remap_addr + reg) + +#define nv_sd_readl(dev, reg) \ + readl((dev)->sd_addr + reg) + +#define reg_shift(shiftbits) (shiftbits * 8) + +#define azx_writew(chip, reg, value) \ + writel((((value) << reg_shift(MASK_W(reg))) + \ + (nv_readl(chip, MASK_D(reg)) & reg_mask_word(MASK_W(reg)))), \ + ((chip)->remap_addr + MASK_D(reg))) + +#define azx_readw(chip, reg) \ + ((readl((chip)->remap_addr + MASK_D(reg)) >>\ + reg_shift(MASK_W(reg))) & MASK_L_W) + +#define azx_writeb(chip, reg, value) \ + writel((((value) << reg_shift(MASK_B(reg))) + \ + (nv_readl(chip, MASK_D(reg)) & reg_mask_byte(MASK_B(reg)))), \ + ((chip)->remap_addr + MASK_D(reg))) + +#define azx_readb(chip, reg) \ + ((readl((chip)->remap_addr + MASK_D(reg)) >>\ + reg_shift(MASK_B(reg))) & MASK_L_B) + +#define azx_sd_writew(dev, reg, value) \ + writel((((value) << reg_shift(MASK_W(reg))) + \ + (nv_sd_readl(dev, MASK_D(reg)) & reg_mask_word(MASK_W(reg)))), \ + ((dev)->sd_addr + MASK_D(reg))) + +#define azx_sd_readw(dev, reg) \ + ((readl((dev)->sd_addr + MASK_D(reg)) >>\ + reg_shift(MASK_W(reg))) & MASK_L_W) + +#define azx_sd_writeb(dev, reg, value) \ + writel(((value) << reg_shift(MASK_B(reg))) + \ + (nv_sd_readl(dev, MASK_D(reg)) & reg_mask_byte(MASK_B(reg))), \ + ((dev)->sd_addr + MASK_D(reg))) + +#define azx_sd_readb(dev, reg) \ + ((readl((dev)->sd_addr + MASK_D(reg)) >>\ + reg_shift(MASK_B(reg))) & MASK_L_B) + +#else /* CONFIG_SND_HDA_TEGRA */ + +#define azx_writew(chip,reg,value) \ + writew(value, (chip)->remap_addr + ICH6_REG_##reg) +#define azx_readw(chip,reg) \ + readw((chip)->remap_addr + ICH6_REG_##reg) +#define azx_writeb(chip,reg,value) \ + writeb(value, (chip)->remap_addr + ICH6_REG_##reg) +#define azx_readb(chip,reg) \ + readb((chip)->remap_addr + ICH6_REG_##reg) + +#define azx_sd_writew(dev,reg,value) \ + writew(value, (dev)->sd_addr + ICH6_REG_##reg) +#define azx_sd_readw(dev,reg) \ + readw((dev)->sd_addr + ICH6_REG_##reg) +#define azx_sd_writeb(dev,reg,value) \ + writeb(value, (dev)->sd_addr + ICH6_REG_##reg) +#define azx_sd_readb(dev,reg) \ + readb((dev)->sd_addr + ICH6_REG_##reg) +#endif /* CONFIG_SND_HDA_TEGRA */ + +/* for pcm support */ +#define get_azx_dev(substream) (substream->runtime->private_data) + +/* + * Interface for HD codec + */ + +/* + * CORB / RIRB interface + */ +void azx_init_cmd_io(struct azx *chip); + +void azx_free_cmd_io(struct azx *chip); + +int azx_corb_send_cmd(struct hda_bus *bus, u32 val); + +void azx_update_rirb(struct azx *chip); + +unsigned int azx_rirb_get_response(struct hda_bus *bus, unsigned int addr); + +int azx_single_send_cmd(struct hda_bus *bus, u32 val); + +unsigned int azx_single_get_response(struct hda_bus *bus, unsigned int addr); + +int azx_send_cmd(struct hda_bus *bus, unsigned int val); + +unsigned int azx_get_response(struct hda_bus *bus, unsigned int addr); + +#ifdef CONFIG_SND_HDA_POWER_SAVE +void azx_power_notify(struct hda_bus *bus); +#endif + +int azx_reset(struct azx *chip, int full_reset); + + +void azx_int_enable(struct azx *chip); + +void azx_int_disable(struct azx *chip); + +void azx_int_clear(struct azx *chip); + +void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev); + +void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev); + +void azx_init_chip(struct azx *chip, int full_reset); + +int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); + +irqreturn_t azx_interrupt(int irq, void *dev_id); + +int setup_bdle(struct snd_pcm_substream *substream, + struct azx_dev *azx_dev, u32 **bdlp, + int ofs, int size, int with_ioc); + +int azx_setup_periods(struct azx *chip, + struct snd_pcm_substream *substream, + struct azx_dev *azx_dev); + +int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev); + +int probe_codec(struct azx *chip, int addr); + +void azx_stop_chip(struct azx *chip); + +inline struct azx_dev * +azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream); + +inline void azx_release_device(struct azx_dev *azx_dev); + +int azx_pcm_open(struct snd_pcm_substream *substream); + +int azx_pcm_close(struct snd_pcm_substream *substream); + +int azx_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params); + +int azx_pcm_hw_free(struct snd_pcm_substream *substream); + +int azx_pcm_prepare(struct snd_pcm_substream *substream); + +int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd); + +unsigned int azx_via_get_position(struct azx *chip, + struct azx_dev *azx_dev); + +unsigned int azx_get_position(struct azx *chip, + struct azx_dev *azx_dev); + +snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream); + +int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); + +void azx_irq_pending_work(struct work_struct *work); + +void azx_clear_irq_pending(struct azx *chip); + +void azx_pcm_free(struct snd_pcm *pcm); + +int __devinit azx_mixer_create(struct azx *chip); + +int __devinit azx_init_stream(struct azx *chip); + +#ifdef CONFIG_SND_HDA_POWER_SAVE +void azx_power_notify(struct hda_bus *bus); +#endif /* CONFIG_SND_HDA_POWER_SAVE */ + +#ifdef CONFIG_PM +int snd_hda_codecs_inuse(struct hda_bus *bus); +#endif /* CONFIG_PM */ + +int azx_halt(struct notifier_block *nb, unsigned long event, void *buf); + +void azx_notifier_register(struct azx *chip); + +void azx_notifier_unregister(struct azx *chip); + +void power_down_all_codecs(struct azx *chip); + +int azx_acquire_irq(struct azx *chip, int do_disconnect); + +void azx_bus_reset(struct hda_bus *bus); + +int __devinit azx_codec_configure(struct azx *chip); + +struct azx_pcm { + struct azx *chip; + struct hda_codec *codec; + struct hda_pcm_stream *hinfo[2]; +}; + +#endif /* __LINUX_LIB_HDA_INTEL_H__ */ diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index d375c53c954f..fdc265aaae0d 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -1317,8 +1317,10 @@ static int alc_auto_parse_customize_define(struct hda_codec *codec) spec->cdefine.enable_pcbeep = 1; /* assume always enabled */ ass = codec->subsystem_id & 0xffff; - if (ass != codec->bus->pci->subsystem_device && (ass & 1)) +#if !defined(CONFIG_SND_HDA_TEGRA) + if ((ass != codec->bus->pci->subsystem_device) && (ass & 1)) goto do_sku; +#endif /* !defined(CONFIG_SND_HDA_TEGRA) */ nid = 0x1d; if (codec->vendor_id == 0x10ec0260) @@ -1512,6 +1514,7 @@ static void alc_pick_fixup(struct hda_codec *codec, const struct alc_fixup *fix, int pre_init) { +#if !defined(CONFIG_SND_HDA_TEGRA) const struct alc_pincfg *cfg; quirk = snd_pci_quirk_lookup(codec->bus->pci, quirk); @@ -1534,6 +1537,7 @@ static void alc_pick_fixup(struct hda_codec *codec, #endif add_verb(codec->spec, fix->verbs); } +#endif /* !defined(CONFIG_SND_HDA_TEGRA) */ } static int alc_read_coef_idx(struct hda_codec *codec, @@ -14715,9 +14719,13 @@ static int patch_alc269(struct hda_codec *codec) } else alc_fix_pll_init(codec, 0x20, 0x04, 15); +#if !defined(CONFIG_SND_HDA_TEGRA) board_config = snd_hda_check_board_config(codec, ALC269_MODEL_LAST, alc269_models, alc269_cfg_tbl); +#else + board_config = -1; +#endif /* !defined(CONFIG_SND_HDA_TEGRA) */ if (board_config < 0) { printk(KERN_INFO "hda_codec: %s: BIOS auto-probing.\n", @@ -19532,11 +19540,14 @@ static int patch_alc680(struct hda_codec *codec) * patch entries */ static struct hda_codec_preset snd_hda_preset_realtek[] = { +#if !defined(CONFIG_SND_HDA_TEGRA) { .id = 0x10ec0260, .name = "ALC260", .patch = patch_alc260 }, { .id = 0x10ec0262, .name = "ALC262", .patch = patch_alc262 }, { .id = 0x10ec0267, .name = "ALC267", .patch = patch_alc268 }, { .id = 0x10ec0268, .name = "ALC268", .patch = patch_alc268 }, +#endif /* !defined(CONFIG_SND_HDA_TEGRA) */ { .id = 0x10ec0269, .name = "ALC269", .patch = patch_alc269 }, +#if !defined(CONFIG_SND_HDA_TEGRA) { .id = 0x10ec0270, .name = "ALC270", .patch = patch_alc269 }, { .id = 0x10ec0272, .name = "ALC272", .patch = patch_alc662 }, { .id = 0x10ec0275, .name = "ALC275", .patch = patch_alc269 }, @@ -19567,6 +19578,7 @@ static struct hda_codec_preset snd_hda_preset_realtek[] = { { .id = 0x10ec0888, .name = "ALC888", .patch = patch_alc888 }, { .id = 0x10ec0889, .name = "ALC889", .patch = patch_alc882 }, { .id = 0x10ec0892, .name = "ALC892", .patch = patch_alc662 }, +#endif /* !defined(CONFIG_SND_HDA_TEGRA) */ {} /* terminator */ }; diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig index 8c78ccedd6a8..57594d7e3caf 100644 --- a/sound/soc/tegra/Kconfig +++ b/sound/soc/tegra/Kconfig @@ -22,3 +22,19 @@ config TEGRA_GENERIC_CODEC config TEGRA_JACK tristate "Tegra wired accessory jack support" + +config SND_HDA_TEGRA + depends on (!ARCH_TEGRA_2x_SOC) + bool "Tegra HD Audio" + select SND_PCM + select SND_VMASTER + select SND_JACK if INPUT=y || INPUT=SND + help + Say Y here to include support for Tegra "High Definition + Audio" (Azalia) and its compatible devices. + +if (SND_HDA_TEGRA || SND_PCI) + +source "sound/pci/hda/Kconfig" + +endif |