diff options
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 20 |
2 files changed, 12 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 69e5bc7366dc..805a9c785278 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -694,6 +694,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) switch (mode) { case TEGRA_SUSPEND_LP0: + rate = clk_get_rate_all_locked(tegra_pclk); if (pdata->combined_req) { reg |= TEGRA_POWER_PWRREQ_OE; reg &= ~TEGRA_POWER_CPU_PWRREQ_OE; diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 0d7a16bd7c5e..93c2d5dc6af7 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -512,8 +512,19 @@ tegra3_tear_down_core: * r7 = TEGRA_TMRUS_BASE */ tegra3_cpu_clk32k: + ldr r0, [r4, #PMC_CTRL] + tst r0, #PMC_CTRL_SIDE_EFFECT_LP0 + beq lp1_clocks_prepare + + /* enable PLLM via PMC in LP0 */ + ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] + orr r0, r0, #((1<<12) | (1 << 11)) + str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] + mov pc, lr + /* start by jumping to clkm to safely disable PLLs, then jump * to clks */ +lp1_clocks_prepare: mov r0, #(1 << 28) str r0, [r5, #CLK_RESET_SCLK_BURST] str r0, [r5, #CLK_RESET_CCLK_BURST] @@ -538,20 +549,11 @@ tegra3_cpu_clk32k: #endif /* disable PLLM via PMC in LP1 */ - ldr r0, [r4, #PMC_CTRL] - tst r0, #PMC_CTRL_SIDE_EFFECT_LP0 - bne enable_pllm_lp0 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] bic r0, r0, #(1<<12) str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] b powerdown_pll_pcx -enable_pllm_lp0: - /* enable PLLM via PMC in LP0 */ - ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] - orr r0, r0, #((1<<12) | (1 << 11)) - str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] - powerdown_pll_pcx: /* disable PLLP, PLLA, PLLC, and PLLX in LP0 and LP1 states */ ldr r0, [r4, #PMC_CTRL] |