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authorChen-Yu Tsai <wens@csie.org>2014-09-06 14:45:10 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-09-13 10:07:24 +0200
commitcfe4c93b58924b3764cd7269d3d953049405e938 (patch)
tree915e04f56e9f9a243e9862100763c4fcca2284c4 /include/linux/clk.h
parent7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9 (diff)
clk: sunxi: add correct divider table for sun4i-apb0 clock
The sun4i-apb0 clock, as found on all platforms using it, is a power-of-two-based divider clock, with a special divider of 2 for value 0. This was causing the clock framework to incorrectly calculate the clock rate for apb1 and related modules on sun6i and sun8i. On sun[4/5/7]i, u-boot SPL configures the divider with value 1 for /2 divider, so no suprises there. This patch adds a proper divider table for it, so the correct clock rate can be calculated. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'include/linux/clk.h')
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