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authorMike Frysinger <michael.frysinger@analog.com>2007-08-05 17:06:48 +0800
committerBryan Wu <bryan.wu@analog.com>2007-08-05 17:06:48 +0800
commitdbcc78bebe9daed8998d9f7c4e30bd3b73a4a169 (patch)
tree245245141a698ed20592b29e4416a3b066854202 /include/asm-blackfin/mach-bf533
parentf0b5d12f2b3226c85258519d7725e63d9daf5e90 (diff)
Blackfin arch: all our other ports call this SIZE rather than SPI_LEN
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf533')
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 6a3cf93f8b57..81b4af17c6a3 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -928,7 +928,7 @@
#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
-#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */