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authorBen Skeggs <bskeggs@redhat.com>2012-09-26 15:01:39 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-10-03 13:13:16 +1000
commit8a57d279d6e1bf19d2d2e54f51d4f40c46c7d1a8 (patch)
tree3c9310d87287df9d9231ce510306c1b90c7d08ef /drivers
parentdc73b45ad456b173610a211c588d003f7ea77957 (diff)
drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie
We don't need to pull the page address out of the page tables on nv4x chips that have a real GART. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c17
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
index 5ad76f74416f..9f4cc2f31994 100644
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
@@ -44,21 +44,24 @@ nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
struct nouveau_dmaobj *dmaobj,
struct nouveau_gpuobj **pgpuobj)
{
+ struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaeng);
struct nouveau_gpuobj *gpuobj;
u32 flags0 = nv_mclass(dmaobj);
u32 flags2 = 0x00000000;
- u32 offset = (dmaobj->start & 0xfffff000);
- u32 adjust = (dmaobj->start & 0x00000fff);
+ u64 offset = dmaobj->start & 0xfffff000;
+ u64 adjust = dmaobj->start & 0x00000fff;
u32 length = dmaobj->limit - dmaobj->start;
int ret;
if (dmaobj->target == NV_MEM_TARGET_VM) {
- gpuobj = nv04_vmmgr(dmaeng)->vm->pgt[0].obj[0];
- if (dmaobj->start == 0)
- return nouveau_gpuobj_dup(parent, gpuobj, pgpuobj);
+ if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) {
+ struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
+ if (!dmaobj->start)
+ return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
+ offset = nv_ro32(pgt, 8 + (offset >> 10));
+ offset &= 0xfffff000;
+ }
- offset = nv_ro32(gpuobj, 8 + (offset >> 10));
- offset &= 0xfffff000;
dmaobj->target = NV_MEM_TARGET_PCI;
dmaobj->access = NV_MEM_ACCESS_RW;
}