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authorRicardo Neri <ricardo.neri@ti.com>2012-01-31 15:56:16 -0600
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-02-21 09:40:22 +0200
commitf15511e23db4e1deb6bf6a3c88c04ba85434e142 (patch)
tree95a9785a6a6f5f528de86ea439f43ff6f6f43e2f /drivers/video/omap2
parentd8989d96eb35335e4e464369da7bdb28e8c84a9f (diff)
OMAPDSS: HDMI: Modify logic to configure MCLK
The MCLK mode defines a factor to divide the clock that is used to generate the Audio Clock Regeneration packets, MCLK. The divisor is not used when the CTS value is calculated by HW. When the value is calculated by SW, it depends on the silicon revision. Signed-off-by: Ricardo Neri <ricardo.neri@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2')
-rw-r--r--drivers/video/omap2/dss/hdmi.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index ec902b3c2de2..012ee49c78de 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -667,13 +667,15 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
core_cfg.aud_par_busclk = 0;
core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
- core_cfg.use_mclk = false;
+ core_cfg.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
} else {
core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
core_cfg.use_mclk = true;
- core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
}
+
+ if (core_cfg.use_mclk)
+ core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
core_cfg.en_spdif = false;
/* Use sample frequency from channel status word */