diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-05-23 22:08:42 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:43:18 -0800 |
| commit | e332c8fbea9d2ac34dbb91dc0752a8661f910076 (patch) | |
| tree | 7a333b02e0d9febd52c80e6743210e22223de8a3 /drivers/tty/serial | |
| parent | 2f3257d437e9efa0138850c11801039477634fae (diff) | |
arm: tegra: Clean up SOC conditionals
Change SOC conditionals to make them more forward-looking.
Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9
Reviewed-on: http://git-master/r/32706
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: R76b6fcc3d93e57451c6d93b62c6d6ec57a919fa5
Diffstat (limited to 'drivers/tty/serial')
| -rw-r--r-- | drivers/tty/serial/tegra_hsuart.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/tty/serial/tegra_hsuart.c b/drivers/tty/serial/tegra_hsuart.c index acded86ee36f..d2976c02f2d8 100644 --- a/drivers/tty/serial/tegra_hsuart.c +++ b/drivers/tty/serial/tegra_hsuart.c @@ -363,7 +363,10 @@ static void wait_sym_time(struct tegra_uart_port *t, unsigned int syms) static void tegra_fifo_reset(struct tegra_uart_port *t, u8 fcr_bits) { unsigned char fcr = t->fcr_shadow; -#ifdef CONFIG_ARCH_TEGRA_3x_SOC +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + uart_writeb(t, fcr, UART_FCR); +#else /*Hw issue: Resetting tx fifo with non-fifo mode to avoid any extra character to be sent*/ fcr &= ~UART_FCR_ENABLE_FIFO; @@ -373,9 +376,6 @@ static void tegra_fifo_reset(struct tegra_uart_port *t, u8 fcr_bits) uart_writeb(t, fcr, UART_FCR); fcr |= UART_FCR_ENABLE_FIFO; uart_writeb(t, fcr, UART_FCR); -#else - fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); - uart_writeb(t, fcr, UART_FCR); #endif uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */ wait_sym_time(t, 1); /* Wait for the flush to propagate. */ |