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authorGreg Kroah-Hartman <gregkh@suse.de>2010-10-08 11:05:47 -0700
committerGreg Kroah-Hartman <gregkh@suse.de>2010-10-08 11:05:47 -0700
commit66cbd3ab35d35580ddf98304c280a6231685aa41 (patch)
tree64a55ec99419a0cd9a1114588964d15a5c1ad3a1 /drivers/staging/brcm80211/phy
parent370adc7cb052a29531b8177d3be770ae9e631bd2 (diff)
Staging: brcm80211: s/uint32/u32/
Use the kernel types, don't invent your own. Cc: Brett Rudley <brudley@broadcom.com> Cc: Henry Ptasinski <henryp@broadcom.com> Cc: Nohee Ko <noheek@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/brcm80211/phy')
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_cmn.c102
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_hal.h12
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_int.h76
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_lcn.c130
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_lcn.h18
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_n.c200
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c38
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h8
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_n.c100
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_n.h12
10 files changed, 348 insertions, 348 deletions
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_cmn.c b/drivers/staging/brcm80211/phy/wlc_phy_cmn.c
index 17f816f02eeb..643b1073f683 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_cmn.c
+++ b/drivers/staging/brcm80211/phy/wlc_phy_cmn.c
@@ -30,7 +30,7 @@
#include <wlc_phy_radio.h>
#include <wlc_phy_lcn.h>
-uint32 phyhal_msg_level = PHYHAL_ERROR;
+u32 phyhal_msg_level = PHYHAL_ERROR;
typedef struct _chan_info_basic {
u16 chan;
@@ -126,10 +126,10 @@ const u8 ofdm_rate_lookup[] = {
#define PHY_WREG_LIMIT 24
static void wlc_set_phy_uninitted(phy_info_t *pi);
-static uint32 wlc_phy_get_radio_ver(phy_info_t *pi);
+static u32 wlc_phy_get_radio_ver(phy_info_t *pi);
static void wlc_phy_timercb_phycal(void *arg);
-static bool wlc_phy_noise_calc_phy(phy_info_t *pi, uint32 *cmplx_pwr,
+static bool wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr,
s8 *pwr_ant);
static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay);
@@ -142,8 +142,8 @@ static void wlc_phy_txpower_reg_limit_calc(phy_info_t *pi,
static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi);
static s8 wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan,
- uint32 band, u8 rate);
-static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, uint32 band);
+ u32 band, u8 rate);
+static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band);
static s8 wlc_phy_env_measure_vbat(phy_info_t *pi);
static s8 wlc_phy_env_measure_temperature(phy_info_t *pi);
@@ -304,31 +304,31 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
}
}
-static uint32 read_radio_id(phy_info_t *pi)
+static u32 read_radio_id(phy_info_t *pi)
{
- uint32 id;
+ u32 id;
if (NORADIO_ENAB(pi->pubpi))
return NORADIO_IDCODE;
if (D11REV_GE(pi->sh->corerev, 24)) {
- uint32 b0, b1, b2;
+ u32 b0, b1, b2;
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 0);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
#endif
- b0 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
+ b0 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 1);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
#endif
- b1 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
+ b1 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 2);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
#endif
- b2 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
+ b2 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
& 0xf);
@@ -337,8 +337,8 @@ static uint32 read_radio_id(phy_info_t *pi)
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->phy4waddr);
#endif
- id = (uint32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);
- id |= (uint32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16;
+ id = (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);
+ id |= (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16;
}
pi->phy_wreg = 0;
return id;
@@ -396,7 +396,7 @@ void write_phy_channel_reg(phy_info_t *pi, uint val)
#if defined(BCMDBG)
static bool wlc_phy_war41476(phy_info_t *pi)
{
- uint32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
+ u32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
return ((mc & MCTL_EN_MAC) == 0)
|| ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK);
@@ -439,7 +439,7 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
if (addr == 0x72)
(void)R_REG(osh, &regs->phyregdata);
#else
- W_REG(osh, (volatile uint32 *)(uintptr) (&regs->phyregaddr),
+ W_REG(osh, (volatile u32 *)(uintptr) (&regs->phyregaddr),
addr | (val << 16));
if (BUSTYPE(pi->sh->bustype) == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
@@ -607,7 +607,7 @@ void BCMATTACHFN(wlc_phy_shared_detach) (shared_phy_t *phy_sh)
wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs,
int bandtype, char *vars) {
phy_info_t *pi;
- uint32 sflags = 0;
+ u32 sflags = 0;
uint phyversion;
int i;
osl_t *osh;
@@ -686,7 +686,7 @@ wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs,
pi->pubpi.radioid = NORADIO_ID;
pi->pubpi.radiorev = 5;
} else {
- uint32 idcode;
+ u32 idcode;
wlc_phy_anacore((wlc_phy_t *) pi, ON);
@@ -833,7 +833,7 @@ bool wlc_phy_get_encore(wlc_phy_t *pih)
return pi->pubpi.abgphy_encore;
}
-uint32 wlc_phy_get_coreflags(wlc_phy_t *pih)
+u32 wlc_phy_get_coreflags(wlc_phy_t *pih)
{
phy_info_t *pi = (phy_info_t *) pih;
return pi->pubpi.coreflags;
@@ -899,11 +899,11 @@ void wlc_phy_anacore(wlc_phy_t *pih, bool on)
}
}
-uint32 wlc_phy_clk_bwbits(wlc_phy_t *pih)
+u32 wlc_phy_clk_bwbits(wlc_phy_t *pih)
{
phy_info_t *pi = (phy_info_t *) pih;
- uint32 phy_bw_clkbits = 0;
+ u32 phy_bw_clkbits = 0;
if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
switch (pi->bw) {
@@ -973,7 +973,7 @@ void wlc_phy_hw_state_upd(wlc_phy_t *pih, bool newstate)
void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec)
{
- uint32 mc;
+ u32 mc;
initfn_t phy_init = NULL;
phy_info_t *pi = (phy_info_t *) pih;
@@ -1064,9 +1064,9 @@ int BCMUNINITFN(wlc_phy_down) (wlc_phy_t *pih)
return callbacks;
}
-static uint32 wlc_phy_get_radio_ver(phy_info_t *pi)
+static u32 wlc_phy_get_radio_ver(phy_info_t *pi)
{
- uint32 ver;
+ u32 ver;
ver = read_radio_id(pi);
@@ -1091,7 +1091,7 @@ wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
}
}
-void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val)
+void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val)
{
ASSERT((width == 8) || (width == 16) || (width == 32));
@@ -1126,7 +1126,7 @@ wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
uint tbl_width = ptbl_info->tbl_width;
const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
- const uint32 *ptbl_32b = (const uint32 *)ptbl_info->tbl_ptr;
+ const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
@@ -1169,7 +1169,7 @@ wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
uint tbl_width = ptbl_info->tbl_width;
u8 *ptbl_8b = (u8 *) (uintptr) ptbl_info->tbl_ptr;
u16 *ptbl_16b = (u16 *) (uintptr) ptbl_info->tbl_ptr;
- uint32 *ptbl_32b = (uint32 *) (uintptr) ptbl_info->tbl_ptr;
+ u32 *ptbl_32b = (u32 *) (uintptr) ptbl_info->tbl_ptr;
ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
@@ -1264,11 +1264,11 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
};
- uint32 *dummypkt;
+ u32 *dummypkt;
ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
- dummypkt = (uint32 *) (ofdm ? ofdmpkt : cckpkt);
+ dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
dummypkt);
@@ -1783,7 +1783,7 @@ wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, u8 *max_txpwr,
void
wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint bandunit, int32 *max_pwr,
- int32 *min_pwr, uint32 *step_pwr)
+ int32 *min_pwr, u32 *step_pwr)
{
return;
}
@@ -1813,7 +1813,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi)
u8 max_num_rate;
u8 start_rate = 0;
chanspec_t chspec;
- uint32 band = CHSPEC2WLC_BAND(pi->radio_chanspec);
+ u32 band = CHSPEC2WLC_BAND(pi->radio_chanspec);
initfn_t txpwr_recalc_fn = NULL;
chspec = pi->radio_chanspec;
@@ -1826,7 +1826,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi)
pactrl = 0;
if (ISLCNPHY(pi)) {
- uint32 offset_mcs, i;
+ u32 offset_mcs, i;
if (CHSPEC_IS40(pi->radio_chanspec)) {
offset_mcs = pi->mcs40_po;
@@ -2080,7 +2080,7 @@ void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent)
pi->txpwr_percent = txpwr_percent;
}
-void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap)
+void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap)
{
phy_info_t *pi = (phy_info_t *) ppi;
@@ -2270,14 +2270,14 @@ void wlc_phy_txpower_ipa_upd(phy_info_t *pi)
}
}
-static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi);
+static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi);
-static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
+static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
{
s16 tx0_status, tx1_status;
u16 estPower1, estPower2;
u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
- uint32 est_pwr;
+ u32 est_pwr;
estPower1 = read_phy_reg(pi, 0x118);
estPower2 = read_phy_reg(pi, 0x119);
@@ -2317,7 +2317,7 @@ static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
}
est_pwr =
- (uint32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1);
+ (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1);
return est_pwr;
}
@@ -2360,7 +2360,7 @@ wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power, uint channel)
}
if (ISNPHY(pi)) {
- uint32 est_pout;
+ u32 est_pout;
wlapi_suspend_mac_and_wait(pi->sh->physhim);
wlc_phyreg_enter((wlc_phy_t *) pi);
@@ -2504,7 +2504,7 @@ void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
}
static bool
-wlc_phy_noise_calc_phy(phy_info_t *pi, uint32 *cmplx_pwr, s8 *pwr_ant)
+wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr, s8 *pwr_ant)
{
s8 cmplx_pwr_dbm[PHY_CORE_MAX];
u8 i;
@@ -2616,7 +2616,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
MCMD_BG_NOISE);
} else {
phy_iq_est_t est[PHY_CORE_MAX];
- uint32 cmplx_pwr[PHY_CORE_MAX];
+ u32 cmplx_pwr[PHY_CORE_MAX];
s8 noise_dbm_ant[PHY_CORE_MAX];
u16 log_num_samps, num_samps, classif_state = 0;
u8 wait_time = 32;
@@ -2698,10 +2698,10 @@ static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm)
static s8 wlc_phy_noise_read_shmem(phy_info_t *pi)
{
- uint32 cmplx_pwr[PHY_CORE_MAX];
+ u32 cmplx_pwr[PHY_CORE_MAX];
s8 noise_dbm_ant[PHY_CORE_MAX];
u16 lo, hi;
- uint32 cmplx_pwr_tot = 0;
+ u32 cmplx_pwr_tot = 0;
s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
u8 idx, core;
@@ -2746,7 +2746,7 @@ void wlc_phy_noise_sample_intr(wlc_phy_t *pih)
s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
if (ISLCNPHY(pi)) {
- uint32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
+ u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
u16 lo, hi;
int32 pwr_offset_dB, gain_dB;
u16 status_0, status_1;
@@ -2836,10 +2836,10 @@ s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
0
};
-void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
+void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
{
u8 shift_ct, lsb, msb, secondmsb, i;
- uint32 tmp;
+ u32 tmp;
for (i = 0; i < core; i++) {
tmp = cmplx_pwr[i];
@@ -3021,7 +3021,7 @@ void wlc_phy_BSSinit(wlc_phy_t *pih, bool bonlyap, int rssi)
}
void
-wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real, int32 *eps_imag)
+wlc_phy_papd_decode_epsilon(u32 epsilon, int32 *eps_real, int32 *eps_imag)
{
*eps_imag = (epsilon >> 13);
if (*eps_imag > 0xfff)
@@ -3219,9 +3219,9 @@ u8 wlc_phy_nbits(int32 value)
return nbits;
}
-uint32 wlc_phy_sqrt_int(uint32 value)
+u32 wlc_phy_sqrt_int(u32 value)
{
- uint32 root = 0, shift = 0;
+ u32 root = 0, shift = 0;
for (shift = 0; shift < 32; shift += 2) {
if (((0x40000000 >> shift) + root) <= value) {
@@ -3363,7 +3363,7 @@ void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode)
}
static s8
-wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, uint32 band,
+wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, u32 band,
u8 rate)
{
s8 offset = 0;
@@ -3389,7 +3389,7 @@ static s8 wlc_phy_env_measure_temperature(phy_info_t *pi)
return 0;
}
-static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, uint32 band)
+static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band)
{
u8 i;
s8 temp, vbat;
@@ -3414,9 +3414,9 @@ wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset, s8 *ofdmoffset)
*ofdmoffset = 0;
}
-uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor, u8 precision)
+u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
{
- uint32 quotient, remainder, roundup, rbit;
+ u32 quotient, remainder, roundup, rbit;
ASSERT(divisor);
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_hal.h b/drivers/staging/brcm80211/phy/wlc_phy_hal.h
index 849530a8e00b..e92e4e6efda9 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_hal.h
+++ b/drivers/staging/brcm80211/phy/wlc_phy_hal.h
@@ -147,8 +147,8 @@ typedef struct shared_phy_params {
uint boardtype;
uint boardrev;
uint boardvendor;
- uint32 boardflags;
- uint32 boardflags2;
+ u32 boardflags;
+ u32 boardflags2;
} shared_phy_params_t;
#ifdef WLC_LOW
@@ -163,14 +163,14 @@ extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype,
u16 *phyrev, u16 *radioid,
u16 *radiover);
extern bool wlc_phy_get_encore(wlc_phy_t *pih);
-extern uint32 wlc_phy_get_coreflags(wlc_phy_t *pih);
+extern u32 wlc_phy_get_coreflags(wlc_phy_t *pih);
extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate);
extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate);
extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec);
extern void wlc_phy_watchdog(wlc_phy_t *ppi);
extern int wlc_phy_down(wlc_phy_t *ppi);
-extern uint32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
+extern u32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
extern void wlc_phy_cal_init(wlc_phy_t *ppi);
extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init);
@@ -205,7 +205,7 @@ extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
u8 *_max_, u8 *_min_);
extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, int32 *,
- int32 *, uint32 *);
+ int32 *, u32 *);
extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *,
chanspec_t chanspec);
extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override);
@@ -248,7 +248,7 @@ extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
-extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap);
+extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap);
extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_int.h b/drivers/staging/brcm80211/phy/wlc_phy_int.h
index 91e9f7ae776c..1c178117f0f8 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_int.h
+++ b/drivers/staging/brcm80211/phy/wlc_phy_int.h
@@ -27,7 +27,7 @@
#define PHYHAL_TRACE 0x0002
#define PHYHAL_INFORM 0x0004
-extern uint32 phyhal_msg_level;
+extern u32 phyhal_msg_level;
#define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM)
#define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL)
@@ -292,10 +292,10 @@ typedef struct _phy_table_info {
typedef struct phytbl_info {
const void *tbl_ptr;
- uint32 tbl_len;
- uint32 tbl_id;
- uint32 tbl_offset;
- uint32 tbl_width;
+ u32 tbl_len;
+ u32 tbl_id;
+ u32 tbl_offset;
+ u32 tbl_width;
} phytbl_info_t;
typedef struct {
@@ -485,8 +485,8 @@ typedef struct _nphy_txgains {
typedef struct _nphy_noisevar_buf {
int bufcount;
int tone_id[PHY_NOISEVAR_BUFSIZE];
- uint32 noise_vars[PHY_NOISEVAR_BUFSIZE];
- uint32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
+ u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
+ u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
} phy_noisevar_buf_t;
typedef struct {
@@ -510,7 +510,7 @@ typedef struct {
u16 txiqlocal_bestcoeffs[11];
u16 txiqlocal_bestcoeffs_valid;
- uint32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
+ u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
u16 analog_gain_ref;
u16 lut_begin;
u16 lut_end;
@@ -530,7 +530,7 @@ struct shared_phy {
si_t *sih;
void *physhim;
uint corerev;
- uint32 machwcap;
+ u32 machwcap;
bool up;
bool clk;
uint now;
@@ -543,8 +543,8 @@ struct shared_phy {
uint boardtype;
uint boardrev;
uint boardvendor;
- uint32 boardflags;
- uint32 boardflags2;
+ u32 boardflags;
+ u32 boardflags2;
uint bustype;
uint buscorerev;
uint fast_timer;
@@ -688,8 +688,8 @@ struct phy_info {
bool edcrs_threshold_lock;
- uint32 tr_R_gain_val;
- uint32 tr_T_gain_val;
+ u32 tr_R_gain_val;
+ u32 tr_T_gain_val;
s16 ofdm_analog_filt_bw_override;
s16 cck_analog_filt_bw_override;
@@ -701,11 +701,11 @@ struct phy_info {
u16 crsglitch_prev;
bool interference_mode_crs;
- uint32 phy_tx_tone_freq;
+ u32 phy_tx_tone_freq;
uint phy_lastcal;
bool phy_forcecal;
bool phy_fixed_noise;
- uint32 xtalfreq;
+ u32 xtalfreq;
u8 pdiv;
s8 carrier_suppr_disable;
@@ -781,16 +781,16 @@ struct phy_info {
bool nphy_tableloaded;
s8 nphy_rssisel;
- uint32 nphy_bb_mult_save;
+ u32 nphy_bb_mult_save;
u16 nphy_txiqlocal_bestc[11];
bool nphy_txiqlocal_coeffsvalid;
phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
u16 cck2gpo;
- uint32 ofdm2gpo;
- uint32 ofdm5gpo;
- uint32 ofdm5glpo;
- uint32 ofdm5ghpo;
+ u32 ofdm2gpo;
+ u32 ofdm5gpo;
+ u32 ofdm5glpo;
+ u32 ofdm5ghpo;
u8 bw402gpo;
u8 bw405gpo;
u8 bw405glpo;
@@ -811,7 +811,7 @@ struct phy_info {
u16 mcs5gpo[8];
u16 mcs5glpo[8];
u16 mcs5ghpo[8];
- uint32 nphy_rxcalparams;
+ u32 nphy_rxcalparams;
u8 phy_spuravoid;
bool phy_isspuravoid;
@@ -863,7 +863,7 @@ struct phy_info {
u8 nphy_papd_cal_gain_index[2];
s16 nphy_papd_epsilon_offset[2];
bool nphy_papd_recal_enable;
- uint32 nphy_papd_recal_counter;
+ u32 nphy_papd_recal_counter;
bool nphy_force_papd_cal;
bool nphy_papdcomp;
bool ipa2g_on;
@@ -935,8 +935,8 @@ struct phy_info {
s8 txpwrindex[PHY_CORE_MAX];
u8 phycal_tempdelta;
- uint32 mcs20_po;
- uint32 mcs40_po;
+ u32 mcs20_po;
+ u32 mcs40_po;
};
typedef int32 fixed;
@@ -948,8 +948,8 @@ typedef struct _cint32 {
typedef struct radio_regs {
u16 address;
- uint32 init_a;
- uint32 init_g;
+ u32 init_a;
+ u32 init_g;
u8 do_init_a;
u8 do_init_g;
} radio_regs_t;
@@ -1018,15 +1018,15 @@ extern void wlc_phy_write_table(phy_info_t *pi,
extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
u16 tblAddr, u16 tblDataHi,
u16 tblDataLo);
-extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val);
+extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val);
extern void write_phy_channel_reg(phy_info_t *pi, uint val);
extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
extern void wlc_phy_cordic(fixed theta, cint32 *val);
extern u8 wlc_phy_nbits(int32 value);
-extern uint32 wlc_phy_sqrt_int(uint32 value);
-extern void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_dB, u8 core);
+extern u32 wlc_phy_sqrt_int(u32 value);
+extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
radio_20xx_regs_t *radioregs);
@@ -1036,7 +1036,7 @@ extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
-extern void wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real,
+extern void wlc_phy_papd_decode_epsilon(u32 epsilon, int32 *eps_real,
int32 *eps_imag);
extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
@@ -1094,7 +1094,7 @@ extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
extern void wlc_2064_vco_cal(phy_info_t *pi);
extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
-extern uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor,
+extern u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor,
u8 precision);
#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
@@ -1133,8 +1133,8 @@ extern int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index);
typedef struct _phy_iq_est {
int32 iq_prod;
- uint32 i_pwr;
- uint32 q_pwr;
+ u32 i_pwr;
+ u32 q_pwr;
} phy_iq_est_t;
extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
@@ -1148,10 +1148,10 @@ extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
0x72, 0x74, 0x73)
#define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v))
-extern void wlc_phy_table_read_nphy(phy_info_t *pi, uint32, uint32 l, uint32 o,
- uint32 w, void *d);
-extern void wlc_phy_table_write_nphy(phy_info_t *pi, uint32, uint32, uint32,
- uint32, const void *);
+extern void wlc_phy_table_read_nphy(phy_info_t *pi, u32, u32 l, u32 o,
+ u32 w, void *d);
+extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
+ u32, const void *);
#define PHY_IPA(pi) \
((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
@@ -1206,7 +1206,7 @@ extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower,
bool debug);
-extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val,
+extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
u8 mode, u8, bool);
extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf,
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_lcn.c b/drivers/staging/brcm80211/phy/wlc_phy_lcn.c
index 1b90f79eaa57..cfaf01353214 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_lcn.c
+++ b/drivers/staging/brcm80211/phy/wlc_phy_lcn.c
@@ -180,9 +180,9 @@ typedef struct {
} lcnphy_unsign16_struct;
typedef struct {
- uint32 iq_prod;
- uint32 i_pwr;
- uint32 q_pwr;
+ u32 iq_prod;
+ u32 i_pwr;
+ u32 q_pwr;
} lcnphy_iq_est_t;
typedef struct {
@@ -423,7 +423,7 @@ lcnphy_rx_iqcomp_t lcnphy_rx_iqcomp_table_rev0[] = {
{216, 0, 0},
};
-static const uint32 lcnphy_23bitgaincode_table[] = {
+static const u32 lcnphy_23bitgaincode_table[] = {
0x200100,
0x200200,
0x200004,
@@ -545,7 +545,7 @@ static const s8 lcnphy_gain_index_offset_for_rssi[] = {
};
extern const u8 spur_tbl_rev0[];
-extern const uint32 dot11lcnphytbl_rx_gain_info_sz_rev1;
+extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev1;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev1[];
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa;
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250;
@@ -976,7 +976,7 @@ u16
#define FIXED_TXPWR 78
#define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val))
-static uint32 wlc_lcnphy_qdiv_roundup(uint32 divident, uint32 divisor,
+static u32 wlc_lcnphy_qdiv_roundup(u32 divident, u32 divisor,
u8 precision);
static void wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi,
u16 ext_lna, u16 trsw,
@@ -1002,7 +1002,7 @@ static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode);
extern void wlc_lcnphy_tx_pwr_ctrl_init(wlc_phy_t *ppi);
extern void wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng,
u8 rate, struct ether_addr *sa,
- uint32 wait_delay);
+ u32 wait_delay);
static void wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi,
u8 channel);
@@ -1048,9 +1048,9 @@ void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti)
}
static void
-wlc_lcnphy_common_read_table(phy_info_t *pi, uint32 tbl_id,
- const void *tbl_ptr, uint32 tbl_len,
- uint32 tbl_width, uint32 tbl_offset)
+wlc_lcnphy_common_read_table(phy_info_t *pi, u32 tbl_id,
+ const void *tbl_ptr, u32 tbl_len,
+ u32 tbl_width, u32 tbl_offset)
{
phytbl_info_t tab;
tab.tbl_id = tbl_id;
@@ -1062,9 +1062,9 @@ wlc_lcnphy_common_read_table(phy_info_t *pi, uint32 tbl_id,
}
static void
-wlc_lcnphy_common_write_table(phy_info_t *pi, uint32 tbl_id,
- const void *tbl_ptr, uint32 tbl_len,
- uint32 tbl_width, uint32 tbl_offset)
+wlc_lcnphy_common_write_table(phy_info_t *pi, u32 tbl_id,
+ const void *tbl_ptr, u32 tbl_len,
+ u32 tbl_width, u32 tbl_offset)
{
phytbl_info_t tab;
@@ -1076,10 +1076,10 @@ wlc_lcnphy_common_write_table(phy_info_t *pi, uint32 tbl_id,
wlc_lcnphy_write_table(pi, &tab);
}
-static uint32
-wlc_lcnphy_qdiv_roundup(uint32 dividend, uint32 divisor, u8 precision)
+static u32
+wlc_lcnphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
{
- uint32 quotient, remainder, roundup, rbit;
+ u32 quotient, remainder, roundup, rbit;
ASSERT(divisor);
@@ -1140,7 +1140,7 @@ s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi)
return index;
}
-static uint32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, u16 nsamples)
+static u32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, u16 nsamples)
{
lcnphy_iq_est_t iq_est = { 0, 0, 0 };
@@ -1327,7 +1327,7 @@ static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0)
static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi)
{
- uint32 data_buf[64];
+ u32 data_buf[64];
phytbl_info_t tab;
bzero(data_buf, sizeof(data_buf));
@@ -1461,7 +1461,7 @@ static void wlc_lcnphy_pwrctrl_rssiparams(phy_info_t *pi)
static void wlc_lcnphy_tssi_setup(phy_info_t *pi)
{
phytbl_info_t tab;
- uint32 rfseq, ind;
+ u32 rfseq, ind;
tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
tab.tbl_width = 32;
@@ -1615,7 +1615,7 @@ static void wlc_lcnphy_txpower_reset_npt(phy_info_t *pi)
void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
{
phytbl_info_t tab;
- uint32 rate_table[WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM +
+ u32 rate_table[WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM +
WLC_NUM_RATES_MCS_1_STREAM];
uint i, j;
if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
@@ -1626,7 +1626,7 @@ void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
if (i == WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM)
j = TXP_FIRST_MCS_20_SISO;
- rate_table[i] = (uint32) ((int32) (-pi->tx_power_offset[j]));
+ rate_table[i] = (u32) ((int32) (-pi->tx_power_offset[j]));
}
tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
@@ -1645,8 +1645,8 @@ void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
static void wlc_lcnphy_set_tx_pwr_soft_ctrl(phy_info_t *pi, s8 index)
{
- uint32 cck_offset[4] = { 22, 22, 22, 22 };
- uint32 ofdm_offset, reg_offset_cck;
+ u32 cck_offset[4] = { 22, 22, 22, 22 };
+ u32 ofdm_offset, reg_offset_cck;
int i;
u16 index2;
phytbl_info_t tab;
@@ -1733,8 +1733,8 @@ static s8 wlc_lcnphy_tempcompensated_txpwrctrl(phy_info_t *pi)
temp_diff = -temp_diff;
}
- delta_temp = (s8) wlc_lcnphy_qdiv_roundup((uint32) (temp_diff * 192),
- (uint32) (pi_lcn->
+ delta_temp = (s8) wlc_lcnphy_qdiv_roundup((u32) (temp_diff * 192),
+ (u32) (pi_lcn->
lcnphy_tempsense_slope
* 10), 0);
if (neg)
@@ -2155,7 +2155,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain;
u16 auxpga_vmid;
phytbl_info_t tab;
- uint32 val;
+ u32 val;
u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025,
save_reg112;
u16 values_to_save[14];
@@ -2455,7 +2455,7 @@ void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index)
phytbl_info_t tab;
u16 a, b;
u8 bb_mult;
- uint32 bbmultiqcomp, txgain, locoeffs, rfpower;
+ u32 bbmultiqcomp, txgain, locoeffs, rfpower;
lcnphy_txgains_t gains;
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
@@ -2523,9 +2523,9 @@ static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx)
static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi)
{
- uint32 j;
+ u32 j;
phytbl_info_t tab;
- uint32 temp_offset[128];
+ u32 temp_offset[128];
tab.tbl_ptr = temp_offset;
tab.tbl_len = 128;
tab.tbl_id = LCNPHY_TBL_ID_PAPDCOMPDELTATBL;
@@ -2734,10 +2734,10 @@ wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, u16 max_val,
{
u8 phy_bw;
u16 num_samps, t, k;
- uint32 bw;
+ u32 bw;
fixed theta = 0, rot = 0;
cint32 tone_samp;
- uint32 data_buf[64];
+ u32 data_buf[64];
u16 i_samp, q_samp;
phytbl_info_t tab;
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
@@ -2761,7 +2761,7 @@ wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, u16 max_val,
num_samps = bw / ABS(f_kHz);
ASSERT(num_samps <= ARRAYSIZE(data_buf));
k++;
- } while ((num_samps * (uint32) (ABS(f_kHz))) != bw);
+ } while ((num_samps * (u32) (ABS(f_kHz))) != bw);
} else
num_samps = 2;
@@ -2868,7 +2868,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi)
u8 save_bb_mult;
u16 a, b, didq, save_pa_gain = 0;
uint idx, SAVE_txpwrindex = 0xFF;
- uint32 val;
+ u32 val;
u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
phytbl_info_t tab;
u8 ei0, eq0, fi0, fq0;
@@ -2949,7 +2949,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi)
wlc_lcnphy_read_table(pi, &tab);
val = (val & 0xfff00000) |
- ((uint32) (a & 0x3FF) << 10) | (b & 0x3ff);
+ ((u32) (a & 0x3FF) << 10) | (b & 0x3ff);
wlc_lcnphy_write_table(pi, &tab);
val = didq;
@@ -3172,12 +3172,12 @@ wlc_lcnphy_rx_iq_est(phy_info_t *pi,
wait_count++;
}
- iq_est->iq_prod = ((uint32) read_phy_reg(pi, 0x483) << 16) |
- (uint32) read_phy_reg(pi, 0x484);
- iq_est->i_pwr = ((uint32) read_phy_reg(pi, 0x485) << 16) |
- (uint32) read_phy_reg(pi, 0x486);
- iq_est->q_pwr = ((uint32) read_phy_reg(pi, 0x487) << 16) |
- (uint32) read_phy_reg(pi, 0x488);
+ iq_est->iq_prod = ((u32) read_phy_reg(pi, 0x483) << 16) |
+ (u32) read_phy_reg(pi, 0x484);
+ iq_est->i_pwr = ((u32) read_phy_reg(pi, 0x485) << 16) |
+ (u32) read_phy_reg(pi, 0x486);
+ iq_est->q_pwr = ((u32) read_phy_reg(pi, 0x487) << 16) |
+ (u32) read_phy_reg(pi, 0x488);
cleanup:
mod_phy_reg(pi, 0x410, (0x1 << 3), (1) << 3);
@@ -3196,7 +3196,7 @@ static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps)
int32 a, b, temp;
s16 iq_nbits, qq_nbits, arsh, brsh;
int32 iq;
- uint32 ii, qq;
+ u32 ii, qq;
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
a0_new = ((read_phy_reg(pi, 0x645) & (0x3ff << 0)) >> 0);
@@ -3254,7 +3254,7 @@ static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps)
}
b /= temp;
b -= a * a;
- b = (int32) wlc_phy_sqrt_int((uint32) b);
+ b = (int32) wlc_phy_sqrt_int((u32) b);
b -= (1 << 10);
a0_new = (u16) (a & 0x3ff);
b0_new = (u16) (b & 0x3ff);
@@ -3286,7 +3286,7 @@ wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp,
rfoverride3_old, rfoverride3val_old, rfoverride4_old,
rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
int tia_gain;
- uint32 received_power, rx_pwr_threshold;
+ u32 received_power, rx_pwr_threshold;
u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
u16 values_to_save[11];
s16 *ptr;
@@ -3671,7 +3671,7 @@ static void wlc_lcnphy_set_chanspec_tweaks(phy_info_t *pi, chanspec_t chanspec)
void
wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng, u8 rate,
- struct ether_addr *sa, uint32 wait_delay)
+ struct ether_addr *sa, u32 wait_delay)
{
}
@@ -3854,7 +3854,7 @@ static void
wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
s16 *ptr, int mode)
{
- uint32 curval1, curval2, stpptr, curptr, strptr, val;
+ u32 curval1, curval2, stpptr, curptr, strptr, val;
u16 sslpnCalibClkEnCtrl, timer;
u16 old_sslpnCalibClkEnCtrl;
s16 imag, real;
@@ -3887,7 +3887,7 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
write_phy_reg(pi, 0x580, 0x4501);
sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
- write_phy_reg(pi, 0x6da, (uint32) (sslpnCalibClkEnCtrl | 0x2008));
+ write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl | 0x2008));
stpptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr);
curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);
do {
@@ -4039,7 +4039,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
s16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16;
s16 *ptr, phy_c17;
int32 phy_c18, phy_c19;
- uint32 phy_c20, phy_c21;
+ u32 phy_c20, phy_c21;
bool phy_c22, phy_c23, phy_c24, phy_c25;
u16 phy_c26, phy_c27;
u16 phy_c28, phy_c29, phy_c30;
@@ -4244,9 +4244,9 @@ static void
WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
const lcnphy_tx_gain_tbl_entry *
gain_table) {
- uint32 j;
+ u32 j;
phytbl_info_t tab;
- uint32 val;
+ u32 val;
u16 pa_gain;
u16 gm_gain;
@@ -4264,7 +4264,7 @@ WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
for (j = 0; j < 128; j++) {
gm_gain = gain_table[j].gm;
- val = (((uint32) pa_gain << 24) |
+ val = (((u32) pa_gain << 24) |
(gain_table[j].pad << 16) |
(gain_table[j].pga << 8) | gm_gain);
@@ -4280,7 +4280,7 @@ WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
static void wlc_lcnphy_load_rfpower(phy_info_t *pi)
{
phytbl_info_t tab;
- uint32 val, bbmult, rfgain;
+ u32 val, bbmult, rfgain;
u8 index;
u8 scale_factor = 1;
s16 temp, temp1, temp2, qQ, qQ1, qQ2, shift;
@@ -4331,7 +4331,7 @@ static void WLBANDINITFN(wlc_lcnphy_tbl_init) (phy_info_t *pi)
uint idx;
u8 phybw40;
phytbl_info_t tab;
- uint32 val;
+ u32 val;
phybw40 = CHSPEC_IS40(pi->radio_chanspec);
@@ -4481,7 +4481,7 @@ static void wlc_lcnphy_agc_temp_init(phy_info_t *pi)
{
s16 temp;
phytbl_info_t tab;
- uint32 tableBuffer[2];
+ u32 tableBuffer[2];
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
if (NORADIO_ENAB(pi->pubpi))
@@ -4605,7 +4605,7 @@ static void WLBANDINITFN(wlc_lcnphy_baseband_init) (phy_info_t *pi)
static void WLBANDINITFN(wlc_radio_2064_init) (phy_info_t *pi)
{
- uint32 i;
+ u32 i;
lcnphy_radio_regs_t *lcnphyregs = NULL;
lcnphyregs = lcnphy_radio_regs_2064;
@@ -4734,7 +4734,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi)
if (CHSPEC_IS2G(pi->radio_chanspec)) {
u16 cckpo = 0;
- uint32 offset_ofdm, offset_mcs;
+ u32 offset_ofdm, offset_mcs;
pi_lcn->lcnphy_tr_isolation_mid =
(u8) PHY_GETINTVAR(pi, "triso2g");
@@ -4781,7 +4781,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi)
cckpo >>= 4;
}
- offset_ofdm = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo");
+ offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
pi->tx_srom_max_rate_2g[i] = max_pwr_chan -
((offset_ofdm & 0xf) * 2);
@@ -4796,7 +4796,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi)
pi->tx_srom_max_rate_2g[i] = txpwr;
}
- offset_ofdm = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo");
+ offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
pi->tx_srom_max_rate_2g[i] = txpwr -
@@ -4872,7 +4872,7 @@ wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, u8 channel)
u8 pll_pwrup, pll_pwrup_ovr;
fixed qFxtal, qFref, qFvco, qFcal;
u8 d15, d16, f16, e44, e45;
- uint32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div;
+ u32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div;
u16 loop_bw, d30, setCount;
if (NORADIO_ENAB(pi->pubpi))
return;
@@ -5111,11 +5111,11 @@ bool wlc_phy_attach_lcnphy(phy_info_t *pi)
return TRUE;
}
-static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, uint32 gain)
+static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, u32 gain)
{
u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19;
- trsw = (gain & ((uint32) 1 << 28)) ? 0 : 1;
+ trsw = (gain & ((u32) 1 << 28)) ? 0 : 1;
ext_lna = (u16) (gain >> 29) & 0x01;
lna1 = (u16) (gain >> 0) & 0x0f;
lna2 = (u16) (gain >> 4) & 0x0f;
@@ -5141,11 +5141,11 @@ static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, uint32 gain)
wlc_lcnphy_rx_gain_override_enable(pi, TRUE);
}
-static uint32 wlc_lcnphy_get_receive_power(phy_info_t *pi, int32 *gain_index)
+static u32 wlc_lcnphy_get_receive_power(phy_info_t *pi, int32 *gain_index)
{
- uint32 received_power = 0;
+ u32 received_power = 0;
int32 max_index = 0;
- uint32 gain_code = 0;
+ u32 gain_code = 0;
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
max_index = 36;
@@ -5194,8 +5194,8 @@ int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index)
nominal_power_db = read_phy_reg(pi, 0x425) >> 8;
{
- uint32 power = (received_power * 16);
- uint32 msb1, msb2, val1, val2, diff1, diff2;
+ u32 power = (received_power * 16);
+ u32 msb1, msb2, val1, val2, diff1, diff2;
msb1 = ffs(power) - 1;
msb2 = msb1 + 1;
val1 = 1 << msb1;
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h
index 83351d8d4bd5..2b3bbdb71d0a 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h
+++ b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h
@@ -27,7 +27,7 @@ struct phy_info_lcnphy {
bool lcnphy_recal;
u8 lcnphy_rc_cap;
- uint32 lcnphy_mcs20_po;
+ u32 lcnphy_mcs20_po;
u8 lcnphy_tr_isolation_mid;
u8 lcnphy_tr_isolation_low;
@@ -69,17 +69,17 @@ struct phy_info_lcnphy {
s8 lcnphy_tx_power_idx_override;
u16 lcnphy_noise_samples;
- uint32 lcnphy_papdRxGnIdx;
- uint32 lcnphy_papd_rxGnCtrl_init;
+ u32 lcnphy_papdRxGnIdx;
+ u32 lcnphy_papd_rxGnCtrl_init;
- uint32 lcnphy_gain_idx_14_lowword;
- uint32 lcnphy_gain_idx_14_hiword;
- uint32 lcnphy_gain_idx_27_lowword;
- uint32 lcnphy_gain_idx_27_hiword;
+ u32 lcnphy_gain_idx_14_lowword;
+ u32 lcnphy_gain_idx_14_hiword;
+ u32 lcnphy_gain_idx_27_lowword;
+ u32 lcnphy_gain_idx_27_hiword;
s16 lcnphy_ofdmgainidxtableoffset;
s16 lcnphy_dsssgainidxtableoffset;
- uint32 lcnphy_tr_R_gain_val;
- uint32 lcnphy_tr_T_gain_val;
+ u32 lcnphy_tr_R_gain_val;
+ u32 lcnphy_tr_T_gain_val;
s8 lcnphy_input_pwr_offset_db;
u16 lcnphy_Med_Low_Gain_db;
u16 lcnphy_Very_Low_Gain_db;
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_n.c b/drivers/staging/brcm80211/phy/wlc_phy_n.c
index a335db315402..79322056b9ca 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_n.c
+++ b/drivers/staging/brcm80211/phy/wlc_phy_n.c
@@ -13309,7 +13309,7 @@ static const u16 tbl_iqcal_gainparams_nphy[2][NPHY_IQCAL_NUMGAINS][8] = {
}
};
-static const uint32 nphy_tpc_txgain[] = {
+static const u32 nphy_tpc_txgain[] = {
0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
@@ -13363,7 +13363,7 @@ static const u16 nphy_tpc_loscale[] = {
858, 908, 908, 962, 962, 1019, 1019, 256
};
-static uint32 nphy_tpc_txgain_ipa[] = {
+static u32 nphy_tpc_txgain_ipa[] = {
0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
@@ -13398,7 +13398,7 @@ static uint32 nphy_tpc_txgain_ipa[] = {
0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025
};
-static uint32 nphy_tpc_txgain_ipa_rev5[] = {
+static u32 nphy_tpc_txgain_ipa_rev5[] = {
0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
@@ -13433,7 +13433,7 @@ static uint32 nphy_tpc_txgain_ipa_rev5[] = {
0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025
};
-static uint32 nphy_tpc_txgain_ipa_rev6[] = {
+static u32 nphy_tpc_txgain_ipa_rev6[] = {
0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
@@ -13468,7 +13468,7 @@ static uint32 nphy_tpc_txgain_ipa_rev6[] = {
0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025
};
-static uint32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
+static u32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
0x70ff0040, 0x70f7003e, 0x70ef003b, 0x70e70039,
0x70df0037, 0x70d70036, 0x70cf0033, 0x70c70032,
0x70bf0031, 0x70b7002f, 0x70af002e, 0x70a7002d,
@@ -13503,7 +13503,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001
};
-static uint32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
+static u32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
0xf0ff0040, 0xf0f7003e, 0xf0ef003b, 0xf0e70039,
0xf0df0037, 0xf0d70036, 0xf0cf0033, 0xf0c70032,
0xf0bf0031, 0xf0b7002f, 0xf0af002e, 0xf0a7002d,
@@ -13538,7 +13538,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001
};
-static uint32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
+static u32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
@@ -13573,7 +13573,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
};
-static uint32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
+static u32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
@@ -13608,7 +13608,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
};
-static uint32 nphy_tpc_txgain_ipa_5g[] = {
+static u32 nphy_tpc_txgain_ipa_5g[] = {
0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
@@ -13643,7 +13643,7 @@ static uint32 nphy_tpc_txgain_ipa_5g[] = {
0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f
};
-static uint32 nphy_tpc_txgain_ipa_5g_2057[] = {
+static u32 nphy_tpc_txgain_ipa_5g_2057[] = {
0x7f7f0044, 0x7f7f0040, 0x7f7f003c, 0x7f7f0039,
0x7f7f0036, 0x7e7f003c, 0x7e7f0038, 0x7e7f0035,
0x7d7f003c, 0x7d7f0039, 0x7d7f0036, 0x7d7f0033,
@@ -13678,7 +13678,7 @@ static uint32 nphy_tpc_txgain_ipa_5g_2057[] = {
0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001
};
-static uint32 nphy_tpc_txgain_ipa_5g_2057rev7[] = {
+static u32 nphy_tpc_txgain_ipa_5g_2057rev7[] = {
0x6f7f0031, 0x6f7f002e, 0x6f7f002c, 0x6f7f002a,
0x6f7f0027, 0x6e7f002e, 0x6e7f002c, 0x6e7f002a,
0x6d7f0030, 0x6d7f002d, 0x6d7f002a, 0x6d7f0028,
@@ -13775,7 +13775,7 @@ static u8 pga_all_gain_codes_2057[] = {
15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
};
-static uint32 nphy_papd_scaltbl[] = {
+static u32 nphy_papd_scaltbl[] = {
0x0ae2002f, 0x0a3b0032, 0x09a70035, 0x09220038,
0x0887003c, 0x081f003f, 0x07a20043, 0x07340047,
0x06d2004b, 0x067a004f, 0x06170054, 0x05bf0059,
@@ -13794,7 +13794,7 @@ static uint32 nphy_papd_scaltbl[] = {
0x005805d7, 0x0053062f, 0x004e068d, 0x004a06f1
};
-static uint32 nphy_tpc_txgain_rev3[] = {
+static u32 nphy_tpc_txgain_rev3[] = {
0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
@@ -13829,7 +13829,7 @@ static uint32 nphy_tpc_txgain_rev3[] = {
0x1041003c, 0x1041003b, 0x10410039, 0x10410037
};
-static uint32 nphy_tpc_txgain_HiPwrEPA[] = {
+static u32 nphy_tpc_txgain_HiPwrEPA[] = {
0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e,
0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037,
0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e,
@@ -13864,7 +13864,7 @@ static uint32 nphy_tpc_txgain_HiPwrEPA[] = {
0x0041003c, 0x0041003b, 0x00410039, 0x00410037
};
-static uint32 nphy_tpc_txgain_epa_2057rev3[] = {
+static u32 nphy_tpc_txgain_epa_2057rev3[] = {
0x80f90040, 0x80e10040, 0x80e1003c, 0x80c9003d,
0x80b9003c, 0x80a9003d, 0x80a1003c, 0x8099003b,
0x8091003b, 0x8089003a, 0x8081003a, 0x80790039,
@@ -13899,7 +13899,7 @@ static uint32 nphy_tpc_txgain_epa_2057rev3[] = {
0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d
};
-static uint32 nphy_tpc_txgain_epa_2057rev5[] = {
+static u32 nphy_tpc_txgain_epa_2057rev5[] = {
0x10f90040, 0x10e10040, 0x10e1003c, 0x10c9003d,
0x10b9003c, 0x10a9003d, 0x10a1003c, 0x1099003b,
0x1091003b, 0x1089003a, 0x1081003a, 0x10790039,
@@ -13934,7 +13934,7 @@ static uint32 nphy_tpc_txgain_epa_2057rev5[] = {
0x10090001, 0x10090001, 0x10090001, 0x10090001
};
-static uint32 nphy_tpc_5GHz_txgain_rev3[] = {
+static u32 nphy_tpc_5GHz_txgain_rev3[] = {
0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
@@ -13969,7 +13969,7 @@ static uint32 nphy_tpc_5GHz_txgain_rev3[] = {
0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037
};
-static uint32 nphy_tpc_5GHz_txgain_rev4[] = {
+static u32 nphy_tpc_5GHz_txgain_rev4[] = {
0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
@@ -14004,7 +14004,7 @@ static uint32 nphy_tpc_5GHz_txgain_rev4[] = {
0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034
};
-static uint32 nphy_tpc_5GHz_txgain_rev5[] = {
+static u32 nphy_tpc_5GHz_txgain_rev5[] = {
0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
@@ -14039,7 +14039,7 @@ static uint32 nphy_tpc_5GHz_txgain_rev5[] = {
0x0062003b, 0x00620039, 0x00620037, 0x00620035
};
-static uint32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = {
+static u32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = {
0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e,
0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037,
0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e,
@@ -14092,7 +14092,7 @@ static void wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chans,
static void wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi,
u16 reduction_factr);
static void wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *,
- uint32 *buf);
+ u32 *buf);
static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr);
static void wlc_phy_txlpfbw_nphy(phy_info_t *pi);
static void wlc_phy_spurwar_nphy(phy_info_t *pi);
@@ -14133,10 +14133,10 @@ static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi);
static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi);
static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi);
static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1);
-static uint32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi);
+static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi);
-static void wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32,
- uint32 e);
+static void wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32,
+ u32 e);
static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core);
static void wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *,
phy_cal_mode_t, u8);
@@ -14181,7 +14181,7 @@ static u16 wlc_phy_radio205x_rcal(phy_info_t *pi);
static u16 wlc_phy_radio2057_rccal(phy_info_t *pi);
-static u16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz,
+static u16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz,
u16 max_val,
u8 dac_test_mode);
static void wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf,
@@ -14193,7 +14193,7 @@ static void wlc_phy_runsamples_nphy(phy_info_t *pi, u16 n, u16 lps,
bool wlc_phy_bist_check_phy(wlc_phy_t *pih)
{
phy_info_t *pi = (phy_info_t *) pih;
- uint32 phybist0, phybist1, phybist2, phybist3, phybist4;
+ u32 phybist0, phybist1, phybist2, phybist3, phybist4;
if (NREV_GE(pi->pubpi.phy_rev, 16))
return TRUE;
@@ -14243,8 +14243,8 @@ static void WLBANDINITFN(wlc_phy_bphy_init_nphy) (phy_info_t *pi)
}
void
-wlc_phy_table_write_nphy(phy_info_t *pi, uint32 id, uint32 len, uint32 offset,
- uint32 width, const void *data)
+wlc_phy_table_write_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
+ u32 width, const void *data)
{
mimophytbl_info_t tbl;
@@ -14257,8 +14257,8 @@ wlc_phy_table_write_nphy(phy_info_t *pi, uint32 id, uint32 len, uint32 offset,
}
void
-wlc_phy_table_read_nphy(phy_info_t *pi, uint32 id, uint32 len, uint32 offset,
- uint32 width, void *data)
+wlc_phy_table_read_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
+ u32 width, void *data)
{
mimophytbl_info_t tbl;
@@ -14535,7 +14535,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
uint core;
uint origidx, intr_val;
d11regs_t *regs;
- uint32 d11_clk_ctl_st;
+ u32 d11_clk_ctl_st;
core = 0;
@@ -14703,7 +14703,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- uint32 *tx_pwrctrl_tbl = NULL;
+ u32 *tx_pwrctrl_tbl = NULL;
u16 idx;
s16 pga_gn = 0;
s16 pad_gn = 0;
@@ -15330,7 +15330,7 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi)
s16 alpha0, alpha1, alpha2;
s16 beta0, beta1, beta2;
- uint32 leg_data_weights, ht_data_weights, nss1_data_weights,
+ u32 leg_data_weights, ht_data_weights, nss1_data_weights,
stbc_data_weights;
u8 chan_freq_range = 0;
u16 dac_control = 0x0002;
@@ -17629,7 +17629,7 @@ wlc_phy_chan2freq_nphy(phy_info_t *pi, uint channel, int *f,
chan_info_nphy_radio2057_t *chan_info_tbl_p_0 = NULL;
chan_info_nphy_radio205x_t *chan_info_tbl_p_1 = NULL;
chan_info_nphy_radio2057_rev5_t *chan_info_tbl_p_2 = NULL;
- uint32 tbl_len = 0;
+ u32 tbl_len = 0;
int freq = 0;
@@ -18656,10 +18656,10 @@ wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, u16 reduction_factr)
static void
wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *tone_id_buf,
- uint32 *noise_var_buf)
+ u32 *noise_var_buf)
{
int i;
- uint32 offset;
+ u32 offset;
int tone_id;
int tbllen =
CHSPEC_IS40(pi->
@@ -18798,10 +18798,10 @@ static void wlc_phy_spurwar_nphy(phy_info_t *pi)
{
u16 cur_channel = 0;
int nphy_adj_tone_id_buf[] = { 57, 58 };
- uint32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff };
+ u32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff };
bool isAdjustNoiseVar = FALSE;
uint numTonesAdjust = 0;
- uint32 tempval = 0;
+ u32 tempval = 0;
if (NREV_GE(pi->pubpi.phy_rev, 3)) {
if (pi->phyhang_avoid)
@@ -19563,7 +19563,7 @@ void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init)
{
phy_info_t *pi = (phy_info_t *) ppi;
u16 mask = 0xfc00;
- uint32 mc = 0;
+ u32 mc = 0;
if (NREV_GE(pi->pubpi.phy_rev, 7))
return;
@@ -19709,7 +19709,7 @@ static void
wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *events, u8 *dlys,
u8 len)
{
- uint32 t1_offset, t2_offset;
+ u32 t1_offset, t2_offset;
u8 ctr;
u8 end_event =
NREV_GE(pi->pubpi.phy_rev,
@@ -19754,7 +19754,7 @@ static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset)
rx2tx_lpf_rc_lut_offset = offset;
}
wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
- (uint32) rx2tx_lpf_rc_lut_offset, 16,
+ (u32) rx2tx_lpf_rc_lut_offset, 16,
&lpf_bw_ctl_val);
lpf_bw_ctl_val = lpf_bw_ctl_val & 0x7;
@@ -22338,13 +22338,13 @@ static void wlc_phy_restore_rssical_nphy(phy_info_t *pi)
}
static u16
-wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val,
+wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
u8 dac_test_mode)
{
u8 phy_bw, is_phybw40;
u16 num_samps, t, spur;
fixed theta = 0, rot = 0;
- uint32 tbl_len;
+ u32 tbl_len;
cint32 *tone_buf = NULL;
is_phybw40 = CHSPEC_IS40(pi->radio_chanspec);
@@ -22388,7 +22388,7 @@ wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val,
}
int
-wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val,
+wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
u8 iqmode, u8 dac_test_mode, bool modify_bbmult)
{
u16 num_samps;
@@ -22412,9 +22412,9 @@ wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf,
u16 num_samps)
{
u16 t;
- uint32 *data_buf = NULL;
+ u32 *data_buf = NULL;
- data_buf = (uint32 *) MALLOC(pi->sh->osh, sizeof(uint32) * num_samps);
+ data_buf = (u32 *) MALLOC(pi->sh->osh, sizeof(u32) * num_samps);
if (data_buf == NULL) {
return;
}
@@ -22430,7 +22430,7 @@ wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf,
data_buf);
if (data_buf != NULL)
- MFREE(pi->sh->osh, data_buf, sizeof(uint32) * num_samps);
+ MFREE(pi->sh->osh, data_buf, sizeof(u32) * num_samps);
if (pi->phyhang_avoid)
wlc_phy_stay_in_carriersearch_nphy(pi, FALSE);
@@ -22571,7 +22571,7 @@ nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi)
u16 base_idx[2], curr_gain[2];
u8 core_no;
nphy_txgains_t target_gain;
- uint32 *tx_pwrctrl_tbl = NULL;
+ u32 *tx_pwrctrl_tbl = NULL;
if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
if (pi->phyhang_avoid)
@@ -23513,9 +23513,9 @@ wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, u8 num_samps)
}
wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 1,
- (uint32) pwrindex[0], 32, &qdBm_pwrbuf[0]);
+ (u32) pwrindex[0], 32, &qdBm_pwrbuf[0]);
wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 1,
- (uint32) pwrindex[1], 32, &qdBm_pwrbuf[1]);
+ (u32) pwrindex[1], 32, &qdBm_pwrbuf[1]);
}
static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi)
@@ -23640,7 +23640,7 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, bool debug)
int32 qdBm_power[2];
u16 orig_BBConfig;
u16 phy_saveregs[4];
- uint32 freq_test;
+ u32 freq_test;
u16 ampl_test = 250;
uint stepsize;
bool phyhang_avoid_state = FALSE;
@@ -23800,7 +23800,7 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, bool debug)
static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core)
{
int index;
- uint32 bbmult_scale;
+ u32 bbmult_scale;
u16 bbmult;
u16 tblentry;
@@ -24112,7 +24112,7 @@ wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
u16 gain_save[2];
u16 cal_gain[2];
nphy_iqcal_params_t cal_params[2];
- uint32 tbl_len;
+ u32 tbl_len;
void *tbl_ptr;
bool ladder_updated[2];
u8 mphase_cal_lastphase = 0;
@@ -24569,7 +24569,7 @@ static void wlc_phy_calc_rx_iq_comp_nphy(phy_info_t *pi, u8 core_mask)
phy_iq_est_t est[PHY_CORE_MAX];
nphy_iq_comp_t old_comp, new_comp;
int32 iq = 0;
- uint32 ii = 0, qq = 0;
+ u32 ii = 0, qq = 0;
s16 iq_nbits, qq_nbits, brsh, arsh;
int32 a, b, temp;
int bcmerror = BCME_OK;
@@ -24646,7 +24646,7 @@ static void wlc_phy_calc_rx_iq_comp_nphy(phy_info_t *pi, u8 core_mask)
}
b /= temp;
b -= a * a;
- b = (int32) wlc_phy_sqrt_int((uint32) b);
+ b = (int32) wlc_phy_sqrt_int((u32) b);
b -= (1 << 10);
if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
@@ -25315,7 +25315,7 @@ wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core,
phy_iq_est_t est[PHY_CORE_MAX];
u8 tx_core;
nphy_iq_comp_t save_comp, zero_comp;
- uint32 i_pwr, q_pwr, curr_pwr, optim_pwr = 0, prev_pwr = 0, thresh_pwr =
+ u32 i_pwr, q_pwr, curr_pwr, optim_pwr = 0, prev_pwr = 0, thresh_pwr =
10000;
s16 desired_log2_pwr, actual_log2_pwr, delta_pwr;
bool gainctrl_done = FALSE;
@@ -25524,12 +25524,12 @@ wlc_phy_rxcal_gainctrl_nphy(phy_info_t *pi, u8 rx_core, u16 *rxgain,
static u8
wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
{
- uint32 target_bws[2] = { 9500, 21000 };
- uint32 ref_tones[2] = { 3000, 6000 };
- uint32 target_bw, ref_tone;
+ u32 target_bws[2] = { 9500, 21000 };
+ u32 ref_tones[2] = { 3000, 6000 };
+ u32 target_bw, ref_tone;
- uint32 target_pwr_ratios[2] = { 28606, 18468 };
- uint32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0;
+ u32 target_pwr_ratios[2] = { 28606, 18468 };
+ u32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0;
u16 start_rccal_ovr_val = 128;
u16 txlpf_rccal_lpc_ovr_val = 128;
@@ -25552,7 +25552,7 @@ wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
s8 rccal_stepsize;
u16 rccal_val, last_rccal_val = 0, best_rccal_val = 0;
- uint32 ref_iq_vals = 0, target_iq_vals = 0;
+ u32 ref_iq_vals = 0, target_iq_vals = 0;
u16 num_samps, log_num_samps = 10;
phy_iq_est_t est[PHY_CORE_MAX];
@@ -25933,7 +25933,7 @@ wlc_phy_cal_rxiq_nphy_rev2(phy_info_t *pi, nphy_txgains_t target_gain,
u16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride;
u16 orig_RfctrlIntcRx, orig_RfctrlIntcTx;
u16 num_samps;
- uint32 i_pwr, q_pwr, tot_pwr[3];
+ u32 i_pwr, q_pwr, tot_pwr[3];
u8 gain_pass, use_hpf_num;
u16 mask, val1, val2;
u16 core_no;
@@ -26244,9 +26244,9 @@ static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1)
wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1);
}
-static uint32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi)
+static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi)
{
- uint32 *tx_pwrctrl_tbl = NULL;
+ u32 *tx_pwrctrl_tbl = NULL;
if (CHSPEC_IS2G(pi->radio_chanspec)) {
@@ -26718,16 +26718,16 @@ wlc_phy_papd_cal_cleanup_nphy(phy_info_t *pi, nphy_papd_restore_state *state)
}
static void
-wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start,
- uint32 end)
+wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32 start,
+ u32 end)
{
- uint32 *buf, *src, *dst, sz;
+ u32 *buf, *src, *dst, sz;
sz = end - start + 1;
ASSERT(end > start);
ASSERT(end < NPHY_PAPD_EPS_TBL_SIZE);
- buf = MALLOC(pi->sh->osh, 2 * sizeof(uint32) * NPHY_PAPD_EPS_TBL_SIZE);
+ buf = MALLOC(pi->sh->osh, 2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE);
if (NULL == buf) {
return;
}
@@ -26742,7 +26742,7 @@ wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start,
NPHY_PAPD_EPS_TBL_SIZE, 0, 32, src);
do {
- uint32 phy_a1, phy_a2;
+ u32 phy_a1, phy_a2;
int32 phy_a3, phy_a4, phy_a5, phy_a6, phy_a7;
phy_a1 = end - MIN(end, (winsz >> 1));
@@ -26760,7 +26760,7 @@ wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start,
phy_a6 /= phy_a3;
phy_a7 /= phy_a3;
- dst[end] = ((uint32) phy_a7 << 13) | ((uint32) phy_a6 & 0x1fff);
+ dst[end] = ((u32) phy_a7 << 13) | ((u32) phy_a6 & 0x1fff);
} while (end-- != start);
wlc_phy_table_write_nphy(pi,
@@ -26768,7 +26768,7 @@ wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start,
PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0 :
NPHY_TBL_ID_EPSILONTBL1, sz, start, 32, dst);
- MFREE(pi->sh->osh, buf, 2 * sizeof(uint32) * NPHY_PAPD_EPS_TBL_SIZE);
+ MFREE(pi->sh->osh, buf, 2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE);
}
static void
@@ -26779,7 +26779,7 @@ wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *txgains,
u16 phy_a4, phy_a5;
bool phy_a6;
u8 phy_a7, m[2];
- uint32 phy_a8 = 0;
+ u32 phy_a8 = 0;
nphy_txgains_t phy_a9;
if (NREV_LT(pi->pubpi.phy_rev, 3))
@@ -27081,7 +27081,7 @@ static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core)
bool phy_a5 = FALSE;
bool phy_a6 = TRUE;
int32 phy_a7, phy_a8;
- uint32 phy_a9;
+ u32 phy_a9;
int phy_a10;
bool phy_a11 = FALSE;
int phy_a12;
@@ -27531,7 +27531,7 @@ static void wlc_phy_a4(phy_info_t *pi, bool full_cal)
void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi)
{
uint core;
- uint32 txgain;
+ u32 txgain;
u16 rad_gain, dac_gain, bbmult, m1m2;
u8 txpi[2], chan_freq_range;
int32 rfpwr_offset;
@@ -27590,7 +27590,7 @@ void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi)
for (core = 0; core < pi->pubpi.phy_corenum; core++) {
if (NREV_GE(pi->pubpi.phy_rev, 3)) {
if (PHY_IPA(pi)) {
- uint32 *tx_gaintbl =
+ u32 *tx_gaintbl =
wlc_phy_get_ipa_gaintbl_nphy(pi);
txgain = tx_gaintbl[txpi[core]];
} else {
@@ -28005,7 +28005,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
pi->cck2gpo = (u16) PHY_GETINTVAR(pi, "cck2gpo");
- pi->ofdm2gpo = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo");
+ pi->ofdm2gpo = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
pi->mcs2gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs2gpo0");
pi->mcs2gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs2gpo1");
@@ -28043,7 +28043,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
(s8) PHY_GETINTVAR(pi, "itt5ga1");
- pi->ofdm5gpo = (uint32) PHY_GETINTVAR(pi, "ofdm5gpo");
+ pi->ofdm5gpo = (u32) PHY_GETINTVAR(pi, "ofdm5gpo");
pi->mcs5gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs5gpo0");
pi->mcs5gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs5gpo1");
@@ -28079,7 +28079,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
- pi->ofdm5glpo = (uint32) PHY_GETINTVAR(pi, "ofdm5glpo");
+ pi->ofdm5glpo = (u32) PHY_GETINTVAR(pi, "ofdm5glpo");
pi->mcs5glpo[0] =
(u16) PHY_GETINTVAR(pi, "mcs5glpo0");
@@ -28123,7 +28123,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
- pi->ofdm5ghpo = (uint32) PHY_GETINTVAR(pi, "ofdm5ghpo");
+ pi->ofdm5ghpo = (u32) PHY_GETINTVAR(pi, "ofdm5ghpo");
pi->mcs5ghpo[0] =
(u16) PHY_GETINTVAR(pi, "mcs5ghpo0");
@@ -28230,13 +28230,13 @@ void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi)
static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
{
- uint32 idx;
+ u32 idx;
u16 iqloCalbuf[7];
- uint32 iqcomp, locomp, curr_locomp;
+ u32 iqcomp, locomp, curr_locomp;
s8 locomp_i, locomp_q;
s8 curr_locomp_i, curr_locomp_q;
- uint32 tbl_id, tbl_len, tbl_offset;
- uint32 regval[128];
+ u32 tbl_id, tbl_len, tbl_offset;
+ u32 regval[128];
if (pi->phyhang_avoid)
wlc_phy_stay_in_carriersearch_nphy(pi, TRUE);
@@ -28249,9 +28249,9 @@ static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
iqcomp =
(tbl_id ==
- 26) ? (((uint32) (iqloCalbuf[0] & 0x3ff)) << 10) |
+ 26) ? (((u32) (iqloCalbuf[0] & 0x3ff)) << 10) |
(iqloCalbuf[1] & 0x3ff)
- : (((uint32) (iqloCalbuf[2] & 0x3ff)) << 10) |
+ : (((u32) (iqloCalbuf[2] & 0x3ff)) << 10) |
(iqloCalbuf[3] & 0x3ff);
for (idx = 0; idx < tbl_len; idx++) {
@@ -28266,7 +28266,7 @@ static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
locomp =
- (uint32) ((tbl_id == 26) ? iqloCalbuf[5] : iqloCalbuf[6]);
+ (u32) ((tbl_id == 26) ? iqloCalbuf[5] : iqloCalbuf[6]);
locomp_i = (s8) ((locomp >> 8) & 0xff);
locomp_q = (s8) ((locomp) & 0xff);
for (idx = 0; idx < tbl_len; idx++) {
@@ -28281,8 +28281,8 @@ static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
(s8) ((locomp_q * nphy_tpc_loscale[idx] +
128) >> 8);
}
- curr_locomp = (uint32) ((curr_locomp_i & 0xff) << 8);
- curr_locomp |= (uint32) (curr_locomp_q & 0xff);
+ curr_locomp = (u32) ((curr_locomp_i & 0xff) << 8);
+ curr_locomp |= (u32) (curr_locomp_q & 0xff);
regval[idx] = curr_locomp;
}
wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
@@ -28477,14 +28477,14 @@ static void wlc_phy_txpwrctrl_idle_tssi_nphy(phy_info_t *pi)
static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
{
- uint32 idx;
+ u32 idx;
s16 a1[2], b0[2], b1[2];
s8 target_pwr_qtrdbm[2];
int32 num, den, pwr_est;
u8 chan_freq_range;
u8 idle_tssi[2];
- uint32 tbl_id, tbl_len, tbl_offset;
- uint32 regval[64];
+ u32 tbl_id, tbl_len, tbl_offset;
+ u32 regval[64];
u8 core;
if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
@@ -28696,7 +28696,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
target_pwr_qtrdbm[tbl_id - 26] +
1);
}
- regval[idx] = (uint32) pwr_est;
+ regval[idx] = (u32) pwr_est;
}
wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
regval);
@@ -28764,10 +28764,10 @@ void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi)
&& (pi->nphy_force_papd_cal
|| (wlc_phy_txpwr_ison_nphy(pi)
&&
- (((uint32)
+ (((u32)
ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 0) -
pi->nphy_papd_tx_gain_at_last_cal[0]) >= 4)
- || ((uint32)
+ || ((u32)
ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 1) -
pi->nphy_papd_tx_gain_at_last_cal[1]) >= 4))))) {
wlc_phy_a4(pi, TRUE);
@@ -28779,8 +28779,8 @@ void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type)
u16 mask = 0, val = 0, ishw = 0;
u8 ctr;
uint core;
- uint32 tbl_offset;
- uint32 tbl_len;
+ u32 tbl_offset;
+ u32 tbl_len;
u16 regval[84];
if (pi->phyhang_avoid)
@@ -28926,12 +28926,12 @@ wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask, s8 txpwrindex,
u8 core, txpwrctl_tbl;
u16 tx_ind0, iq_ind0, lo_ind0;
u16 m1m2;
- uint32 txgain;
+ u32 txgain;
u16 rad_gain, dac_gain;
u8 bbmult;
- uint32 iqcomp;
+ u32 iqcomp;
u16 iqcomp_a, iqcomp_b;
- uint32 locomp;
+ u32 locomp;
u16 tmpval;
u8 tx_pwr_ctrl_state;
int32 rfpwr_offset;
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c
index 970a00cfe4fe..e3d6dd183791 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c
@@ -19,7 +19,7 @@
#include <wlc_phy_int.h>
#include <wlc_phytbl_lcn.h>
-const uint32 dot11lcn_gain_tbl_rev0[] = {
+const u32 dot11lcn_gain_tbl_rev0[] = {
0x00000000,
0x00000000,
0x00000000,
@@ -118,7 +118,7 @@ const uint32 dot11lcn_gain_tbl_rev0[] = {
0x00000000,
};
-const uint32 dot11lcn_gain_tbl_rev1[] = {
+const u32 dot11lcn_gain_tbl_rev1[] = {
0x00000000,
0x00000000,
0x00000000,
@@ -258,7 +258,7 @@ const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = {
0x0000,
};
-const uint32 dot11lcn_gain_idx_tbl_rev0[] = {
+const u32 dot11lcn_gain_idx_tbl_rev0[] = {
0x00000000,
0x00000000,
0x10000000,
@@ -521,7 +521,7 @@ const u8 dot11lcn_gain_val_tbl_2G[] = {
0x00
};
-const uint32 dot11lcn_gain_idx_tbl_2G[] = {
+const u32 dot11lcn_gain_idx_tbl_2G[] = {
0x00000000,
0x00000000,
0x00000000,
@@ -676,7 +676,7 @@ const uint32 dot11lcn_gain_idx_tbl_2G[] = {
0x00000000
};
-const uint32 dot11lcn_gain_tbl_2G[] = {
+const u32 dot11lcn_gain_tbl_2G[] = {
0x00000000,
0x00000004,
0x00000008,
@@ -775,7 +775,7 @@ const uint32 dot11lcn_gain_tbl_2G[] = {
0x00000000
};
-const uint32 dot11lcn_gain_tbl_extlna_2G[] = {
+const u32 dot11lcn_gain_tbl_extlna_2G[] = {
0x00000000,
0x00000004,
0x00000008,
@@ -986,7 +986,7 @@ const u8 dot11lcn_gain_val_tbl_extlna_2G[] = {
0x00
};
-const uint32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
+const u32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
0x00000000,
0x00000040,
0x00000000,
@@ -1141,7 +1141,7 @@ const uint32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
0x00000000
};
-const uint32 dot11lcn_aux_gain_idx_tbl_5G[] = {
+const u32 dot11lcn_aux_gain_idx_tbl_5G[] = {
0x0000,
0x0000,
0x0000,
@@ -1182,7 +1182,7 @@ const uint32 dot11lcn_aux_gain_idx_tbl_5G[] = {
0x0000
};
-const uint32 dot11lcn_gain_val_tbl_5G[] = {
+const u32 dot11lcn_gain_val_tbl_5G[] = {
0xf7,
0xfd,
0x00,
@@ -1253,7 +1253,7 @@ const uint32 dot11lcn_gain_val_tbl_5G[] = {
0x00
};
-const uint32 dot11lcn_gain_idx_tbl_5G[] = {
+const u32 dot11lcn_gain_idx_tbl_5G[] = {
0x00000000,
0x00000000,
0x00000000,
@@ -1408,7 +1408,7 @@ const uint32 dot11lcn_gain_idx_tbl_5G[] = {
0x00000000
};
-const uint32 dot11lcn_gain_tbl_5G[] = {
+const u32 dot11lcn_gain_tbl_5G[] = {
0x00000000,
0x00000040,
0x00000080,
@@ -1609,19 +1609,19 @@ const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = {
17, 0, 8}
};
-const uint32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
+const u32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
sizeof(dot11lcnphytbl_rx_gain_info_rev0) /
sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]);
-const uint32 dot11lcnphytbl_rx_gain_info_sz_rev1 =
+const u32 dot11lcnphytbl_rx_gain_info_sz_rev1 =
sizeof(dot11lcnphytbl_rx_gain_info_rev1) /
sizeof(dot11lcnphytbl_rx_gain_info_rev1[0]);
-const uint32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
+const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) /
sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]);
-const uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
+const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) /
sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]);
@@ -1759,7 +1759,7 @@ const u16 dot11lcn_noise_scale_tbl_rev0[] = {
0x0000,
};
-const uint32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
+const u32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
0x000141f8,
0x000021f8,
0x000021fb,
@@ -1772,7 +1772,7 @@ const uint32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
0x0000024b,
};
-const uint32 dot11lcn_ps_ctrl_tbl_rev0[] = {
+const u32 dot11lcn_ps_ctrl_tbl_rev0[] = {
0x00100001,
0x00200010,
0x00300001,
@@ -2612,7 +2612,7 @@ const u16 dot11lcn_iq_local_tbl_rev0[] = {
0x0000,
};
-const uint32 dot11lcn_papd_compdelta_tbl_rev0[] = {
+const u32 dot11lcn_papd_compdelta_tbl_rev0[] = {
0x00080000,
0x00080000,
0x00080000,
@@ -2858,7 +2858,7 @@ const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {
sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16
};
-const uint32 dot11lcnphytbl_info_sz_rev0 =
+const u32 dot11lcnphytbl_info_sz_rev0 =
sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]);
const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = {
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h
index 49bb00a78345..5a64a988d107 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h
@@ -17,19 +17,19 @@
typedef phytbl_info_t dot11lcnphytbl_info_t;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[];
-extern const uint32 dot11lcnphytbl_rx_gain_info_sz_rev0;
+extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev0;
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313;
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa;
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[];
-extern const uint32 dot11lcnphytbl_info_sz_rev0;
+extern const u32 dot11lcnphytbl_info_sz_rev0;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[];
-extern const uint32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
+extern const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[];
-extern const uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
+extern const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[];
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_n.c b/drivers/staging/brcm80211/phy/wlc_phytbl_n.c
index 303b4acc2def..bbc4cfae73e3 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_n.c
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_n.c
@@ -19,7 +19,7 @@
#include <wlc_phy_int.h>
#include <wlc_phytbl_n.h>
-const uint32 frame_struct_rev0[] = {
+const u32 frame_struct_rev0[] = {
0x08004a04,
0x00100000,
0x01000a05,
@@ -889,7 +889,7 @@ const u8 frame_lut_rev0[] = {
0x2a,
};
-const uint32 tmap_tbl_rev0[] = {
+const u32 tmap_tbl_rev0[] = {
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
@@ -1340,7 +1340,7 @@ const uint32 tmap_tbl_rev0[] = {
0x00000000,
};
-const uint32 tdtrn_tbl_rev0[] = {
+const u32 tdtrn_tbl_rev0[] = {
0x061c061c,
0x0050ee68,
0xf592fe36,
@@ -2047,7 +2047,7 @@ const uint32 tdtrn_tbl_rev0[] = {
0x00f006be,
};
-const uint32 intlv_tbl_rev0[] = {
+const u32 intlv_tbl_rev0[] = {
0x00802070,
0x0671188d,
0x0a60192c,
@@ -2148,7 +2148,7 @@ const u16 pilot_tbl_rev0[] = {
0xffff,
};
-const uint32 pltlut_tbl_rev0[] = {
+const u32 pltlut_tbl_rev0[] = {
0x76540123,
0x62407351,
0x76543201,
@@ -2157,7 +2157,7 @@ const uint32 pltlut_tbl_rev0[] = {
0x76430521,
};
-const uint32 tdi_tbl20_ant0_rev0[] = {
+const u32 tdi_tbl20_ant0_rev0[] = {
0x00091226,
0x000a1429,
0x000b56ad,
@@ -2215,7 +2215,7 @@ const uint32 tdi_tbl20_ant0_rev0[] = {
0x00000000,
};
-const uint32 tdi_tbl20_ant1_rev0[] = {
+const u32 tdi_tbl20_ant1_rev0[] = {
0x00014b26,
0x00028d29,
0x000393ad,
@@ -2273,7 +2273,7 @@ const uint32 tdi_tbl20_ant1_rev0[] = {
0x00000000,
};
-const uint32 tdi_tbl40_ant0_rev0[] = {
+const u32 tdi_tbl40_ant0_rev0[] = {
0x0011a346,
0x00136ccf,
0x0014f5d9,
@@ -2386,7 +2386,7 @@ const uint32 tdi_tbl40_ant0_rev0[] = {
0x00000000,
};
-const uint32 tdi_tbl40_ant1_rev0[] = {
+const u32 tdi_tbl40_ant1_rev0[] = {
0x001edb36,
0x000129ca,
0x0002b353,
@@ -2508,7 +2508,7 @@ const u16 bdi_tbl_rev0[] = {
0x04d2,
};
-const uint32 chanest_tbl_rev0[] = {
+const u32 chanest_tbl_rev0[] = {
0x44444444,
0x44444444,
0x44444444,
@@ -2738,7 +2738,7 @@ const u8 mcs_tbl_rev0[] = {
0x00,
};
-const uint32 noise_var_tbl0_rev0[] = {
+const u32 noise_var_tbl0_rev0[] = {
0x020c020c,
0x0000014d,
0x020c020c,
@@ -2997,7 +2997,7 @@ const uint32 noise_var_tbl0_rev0[] = {
0x0000014d,
};
-const uint32 noise_var_tbl1_rev0[] = {
+const u32 noise_var_tbl1_rev0[] = {
0x020c020c,
0x0000014d,
0x020c020c,
@@ -3652,7 +3652,7 @@ const u8 adj_pwr_lut_core1_rev0[] = {
0x00,
};
-const uint32 gainctrl_lut_core0_rev0[] = {
+const u32 gainctrl_lut_core0_rev0[] = {
0x03cc2b44,
0x03cc2b42,
0x03cc2b40,
@@ -3783,7 +3783,7 @@ const uint32 gainctrl_lut_core0_rev0[] = {
0x00002b00,
};
-const uint32 gainctrl_lut_core1_rev0[] = {
+const u32 gainctrl_lut_core1_rev0[] = {
0x03cc2b44,
0x03cc2b42,
0x03cc2b40,
@@ -3914,7 +3914,7 @@ const uint32 gainctrl_lut_core1_rev0[] = {
0x00002b00,
};
-const uint32 iq_lut_core0_rev0[] = {
+const u32 iq_lut_core0_rev0[] = {
0x0000007f,
0x0000007f,
0x0000007f,
@@ -4045,7 +4045,7 @@ const uint32 iq_lut_core0_rev0[] = {
0x0000007f,
};
-const uint32 iq_lut_core1_rev0[] = {
+const u32 iq_lut_core1_rev0[] = {
0x0000007f,
0x0000007f,
0x0000007f,
@@ -4536,9 +4536,9 @@ const mimophytbl_info_t mimophytbl_info_rev0[] = {
,
};
-const uint32 mimophytbl_info_sz_rev0 =
+const u32 mimophytbl_info_sz_rev0 =
sizeof(mimophytbl_info_rev0) / sizeof(mimophytbl_info_rev0[0]);
-const uint32 mimophytbl_info_sz_rev0_volatile =
+const u32 mimophytbl_info_sz_rev0_volatile =
sizeof(mimophytbl_info_rev0_volatile) /
sizeof(mimophytbl_info_rev0_volatile[0]);
@@ -4682,7 +4682,7 @@ const u16 ant_swctrl_tbl_rev3_3[] = {
0x3cc
};
-const uint32 frame_struct_rev3[] = {
+const u32 frame_struct_rev3[] = {
0x08004a04,
0x00100000,
0x01000a05,
@@ -5608,7 +5608,7 @@ const u16 pilot_tbl_rev3[] = {
0xffff,
};
-const uint32 tmap_tbl_rev3[] = {
+const u32 tmap_tbl_rev3[] = {
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
@@ -6059,7 +6059,7 @@ const uint32 tmap_tbl_rev3[] = {
0x00000000,
};
-const uint32 intlv_tbl_rev3[] = {
+const u32 intlv_tbl_rev3[] = {
0x00802070,
0x0671188d,
0x0a60192c,
@@ -6069,7 +6069,7 @@ const uint32 intlv_tbl_rev3[] = {
0x00000070,
};
-const uint32 tdtrn_tbl_rev3[] = {
+const u32 tdtrn_tbl_rev3[] = {
0x061c061c,
0x0050ee68,
0xf592fe36,
@@ -6776,7 +6776,7 @@ const uint32 tdtrn_tbl_rev3[] = {
0x00f006be,
};
-const uint32 noise_var_tbl_rev3[] = {
+const u32 noise_var_tbl_rev3[] = {
0x02110211,
0x0000014d,
0x02110211,
@@ -7166,7 +7166,7 @@ const u16 mcs_tbl_rev3[] = {
0x0007,
};
-const uint32 tdi_tbl20_ant0_rev3[] = {
+const u32 tdi_tbl20_ant0_rev3[] = {
0x00091226,
0x000a1429,
0x000b56ad,
@@ -7224,7 +7224,7 @@ const uint32 tdi_tbl20_ant0_rev3[] = {
0x00000000,
};
-const uint32 tdi_tbl20_ant1_rev3[] = {
+const u32 tdi_tbl20_ant1_rev3[] = {
0x00014b26,
0x00028d29,
0x000393ad,
@@ -7282,7 +7282,7 @@ const uint32 tdi_tbl20_ant1_rev3[] = {
0x00000000,
};
-const uint32 tdi_tbl40_ant0_rev3[] = {
+const u32 tdi_tbl40_ant0_rev3[] = {
0x0011a346,
0x00136ccf,
0x0014f5d9,
@@ -7395,7 +7395,7 @@ const uint32 tdi_tbl40_ant0_rev3[] = {
0x00000000,
};
-const uint32 tdi_tbl40_ant1_rev3[] = {
+const u32 tdi_tbl40_ant1_rev3[] = {
0x001edb36,
0x000129ca,
0x0002b353,
@@ -7508,7 +7508,7 @@ const uint32 tdi_tbl40_ant1_rev3[] = {
0x00000000,
};
-const uint32 pltlut_tbl_rev3[] = {
+const u32 pltlut_tbl_rev3[] = {
0x76540213,
0x62407351,
0x76543210,
@@ -7517,7 +7517,7 @@ const uint32 pltlut_tbl_rev3[] = {
0x76430521,
};
-const uint32 chanest_tbl_rev3[] = {
+const u32 chanest_tbl_rev3[] = {
0x44444444,
0x44444444,
0x44444444,
@@ -8047,7 +8047,7 @@ const u8 adj_pwr_lut_core1_rev3[] = {
0x00,
};
-const uint32 gainctrl_lut_core0_rev3[] = {
+const u32 gainctrl_lut_core0_rev3[] = {
0x5bf70044,
0x5bf70042,
0x5bf70040,
@@ -8178,7 +8178,7 @@ const uint32 gainctrl_lut_core0_rev3[] = {
0x5b07001c,
};
-const uint32 gainctrl_lut_core1_rev3[] = {
+const u32 gainctrl_lut_core1_rev3[] = {
0x5bf70044,
0x5bf70042,
0x5bf70040,
@@ -8309,7 +8309,7 @@ const uint32 gainctrl_lut_core1_rev3[] = {
0x5b07001c,
};
-const uint32 iq_lut_core0_rev3[] = {
+const u32 iq_lut_core0_rev3[] = {
0x00000000,
0x00000000,
0x00000000,
@@ -8440,7 +8440,7 @@ const uint32 iq_lut_core0_rev3[] = {
0x00000000,
};
-const uint32 iq_lut_core1_rev3[] = {
+const u32 iq_lut_core1_rev3[] = {
0x00000000,
0x00000000,
0x00000000,
@@ -9095,7 +9095,7 @@ const u16 papd_comp_rfpwr_tbl_core1_rev3[] = {
0x01d6,
};
-const uint32 papd_comp_epsilon_tbl_core0_rev3[] = {
+const u32 papd_comp_epsilon_tbl_core0_rev3[] = {
0x00000000,
0x00001fa0,
0x00019f78,
@@ -9162,7 +9162,7 @@ const uint32 papd_comp_epsilon_tbl_core0_rev3[] = {
0x03e38ffe,
};
-const uint32 papd_cal_scalars_tbl_core0_rev3[] = {
+const u32 papd_cal_scalars_tbl_core0_rev3[] = {
0x05af005a,
0x0571005e,
0x05040066,
@@ -9229,7 +9229,7 @@ const uint32 papd_cal_scalars_tbl_core0_rev3[] = {
0x002606a4,
};
-const uint32 papd_comp_epsilon_tbl_core1_rev3[] = {
+const u32 papd_comp_epsilon_tbl_core1_rev3[] = {
0x00000000,
0x00001fa0,
0x00019f78,
@@ -9296,7 +9296,7 @@ const uint32 papd_comp_epsilon_tbl_core1_rev3[] = {
0x03e38ffe,
};
-const uint32 papd_cal_scalars_tbl_core1_rev3[] = {
+const u32 papd_cal_scalars_tbl_core1_rev3[] = {
0x05af005a,
0x0571005e,
0x05040066,
@@ -9476,22 +9476,22 @@ const mimophytbl_info_t mimophytbl_info_rev3[] = {
16}
};
-const uint32 mimophytbl_info_sz_rev3 =
+const u32 mimophytbl_info_sz_rev3 =
sizeof(mimophytbl_info_rev3) / sizeof(mimophytbl_info_rev3[0]);
-const uint32 mimophytbl_info_sz_rev3_volatile =
+const u32 mimophytbl_info_sz_rev3_volatile =
sizeof(mimophytbl_info_rev3_volatile) /
sizeof(mimophytbl_info_rev3_volatile[0]);
-const uint32 mimophytbl_info_sz_rev3_volatile1 =
+const u32 mimophytbl_info_sz_rev3_volatile1 =
sizeof(mimophytbl_info_rev3_volatile1) /
sizeof(mimophytbl_info_rev3_volatile1[0]);
-const uint32 mimophytbl_info_sz_rev3_volatile2 =
+const u32 mimophytbl_info_sz_rev3_volatile2 =
sizeof(mimophytbl_info_rev3_volatile2) /
sizeof(mimophytbl_info_rev3_volatile2[0]);
-const uint32 mimophytbl_info_sz_rev3_volatile3 =
+const u32 mimophytbl_info_sz_rev3_volatile3 =
sizeof(mimophytbl_info_rev3_volatile3) /
sizeof(mimophytbl_info_rev3_volatile3[0]);
-const uint32 tmap_tbl_rev7[] = {
+const u32 tmap_tbl_rev7[] = {
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
@@ -9942,7 +9942,7 @@ const uint32 tmap_tbl_rev7[] = {
0x00000000,
};
-const uint32 noise_var_tbl_rev7[] = {
+const u32 noise_var_tbl_rev7[] = {
0x020c020c,
0x0000014d,
0x020c020c,
@@ -10201,7 +10201,7 @@ const uint32 noise_var_tbl_rev7[] = {
0x0000014d,
};
-const uint32 papd_comp_epsilon_tbl_core0_rev7[] = {
+const u32 papd_comp_epsilon_tbl_core0_rev7[] = {
0x00000000,
0x00000000,
0x00016023,
@@ -10268,7 +10268,7 @@ const uint32 papd_comp_epsilon_tbl_core0_rev7[] = {
0x0156cfff,
};
-const uint32 papd_cal_scalars_tbl_core0_rev7[] = {
+const u32 papd_cal_scalars_tbl_core0_rev7[] = {
0x0b5e002d,
0x0ae2002f,
0x0a3b0032,
@@ -10335,7 +10335,7 @@ const uint32 papd_cal_scalars_tbl_core0_rev7[] = {
0x004e068c,
};
-const uint32 papd_comp_epsilon_tbl_core1_rev7[] = {
+const u32 papd_comp_epsilon_tbl_core1_rev7[] = {
0x00000000,
0x00000000,
0x00016023,
@@ -10402,7 +10402,7 @@ const uint32 papd_comp_epsilon_tbl_core1_rev7[] = {
0x0156cfff,
};
-const uint32 papd_cal_scalars_tbl_core1_rev7[] = {
+const u32 papd_cal_scalars_tbl_core1_rev7[] = {
0x0b5e002d,
0x0ae2002f,
0x0a3b0032,
@@ -10580,7 +10580,7 @@ const mimophytbl_info_t mimophytbl_info_rev7[] = {
,
};
-const uint32 mimophytbl_info_sz_rev7 =
+const u32 mimophytbl_info_sz_rev7 =
sizeof(mimophytbl_info_rev7) / sizeof(mimophytbl_info_rev7[0]);
const mimophytbl_info_t mimophytbl_info_rev16[] = {
@@ -10627,5 +10627,5 @@ const mimophytbl_info_t mimophytbl_info_rev16[] = {
,
};
-const uint32 mimophytbl_info_sz_rev16 =
+const u32 mimophytbl_info_sz_rev16 =
sizeof(mimophytbl_info_rev16) / sizeof(mimophytbl_info_rev16[0]);
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_n.h b/drivers/staging/brcm80211/phy/wlc_phytbl_n.h
index 03c34d62c8e3..396122f5e50b 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_n.h
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_n.h
@@ -20,20 +20,20 @@ typedef phytbl_info_t mimophytbl_info_t;
extern const mimophytbl_info_t mimophytbl_info_rev0[],
mimophytbl_info_rev0_volatile[];
-extern const uint32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile;
+extern const u32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile;
extern const mimophytbl_info_t mimophytbl_info_rev3[],
mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[],
mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[];
-extern const uint32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile,
+extern const u32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile,
mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2,
mimophytbl_info_sz_rev3_volatile3;
-extern const uint32 noise_var_tbl_rev3[];
+extern const u32 noise_var_tbl_rev3[];
extern const mimophytbl_info_t mimophytbl_info_rev7[];
-extern const uint32 mimophytbl_info_sz_rev7;
-extern const uint32 noise_var_tbl_rev7[];
+extern const u32 mimophytbl_info_sz_rev7;
+extern const u32 noise_var_tbl_rev7[];
extern const mimophytbl_info_t mimophytbl_info_rev16[];
-extern const uint32 mimophytbl_info_sz_rev16;
+extern const u32 mimophytbl_info_sz_rev16;
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-19 00:12:03 +0000