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author | Simon Guinot <sguinot@lacie.com> | 2010-09-17 23:33:51 +0200 |
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committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-10-28 21:04:15 -0700 |
commit | 1aa14af44cc76d3e38ed4a0b321cab7323a59452 (patch) | |
tree | 8b940e9a0ecee0ff679150e1ff7ac61fa893e892 /drivers/net/enc28j60_hw.h | |
parent | 0243e39b20b13072a9e16e615316859c4c6c7600 (diff) |
dmaengine: fix interrupt clearing for mv_xor
commit cc60f8878eab892c03d06b10f389232b9b66bd83 upstream.
When using simultaneously the two DMA channels on a same engine, some
transfers are never completed. For example, an endless lock can occur
while writing heavily on a RAID5 array (with async-tx offload support
enabled).
Note that this issue can also be reproduced by using the DMA test
client.
On a same engine, the interrupt cause register is shared between two
DMA channels. This patch make sure that the cause bit is only cleared
for the requested channel.
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Tested-by: Luc Saillard <luc@saillard.org>
Acked-by: saeed bishara <saeed.bishara@gmail.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/net/enc28j60_hw.h')
0 files changed, 0 insertions, 0 deletions