diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2013-02-01 22:32:38 +0530 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2013-02-22 05:49:18 -0800 |
| commit | 42800cab851a693013f29b54f2a0f75d7a9683a8 (patch) | |
| tree | cc78d04c59fcf5ffd3e9abd1ab7e9852df63111e /drivers/mmc | |
| parent | 2c6b09135f87293170a09270f77f413e07e7cf67 (diff) | |
mmc: tegra: Enable HS200 mode support
Set MMC_CAP2_HS200 to enable HS200 mode support.
Increase sdmmc4 base clock frequency of T114 chip to 208MHz.
Bug 1225343
Change-Id: Ica171c8fe093f0c0ab35b4c46c2dcebaecf25134
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/196484
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 511fa1b38a6d..0f89f333ec0e 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -106,12 +106,14 @@ static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci); #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC) static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci); +static unsigned int tegra11_sdhost_max_clk[4] = { + 208000000, 104000000, 208000000, 208000000 }; #endif static unsigned int tegra_sdhost_min_freq; static unsigned int tegra_sdhost_std_freq; -#ifndef CONFIG_ARCH_TEGRA_2x_SOC +#ifdef CONFIG_ARCH_TEGRA_3x_SOC static unsigned int tegra3_sdhost_max_clk[4] = { 208000000, 104000000, 208000000, 104000000 }; #endif @@ -418,8 +420,8 @@ static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci) /* Set the base clock frequency */ vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL); vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT); - vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) << - SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT; + vendor_ctrl |= (tegra11_sdhost_max_clk[tegra_host->instance] / 1000000) + << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT; vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE; vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE; @@ -2062,7 +2064,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) #ifdef CONFIG_MMC_BKOPS host->mmc->caps2 |= MMC_CAP2_BKOPS; #endif - tegra_sdhost_min_freq = TEGRA_SDHOST_MIN_FREQ; #if defined(CONFIG_ARCH_TEGRA_2x_SOC) tegra_host->hw_ops = &tegra_2x_sdhci_ops; @@ -2073,6 +2074,7 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) #else tegra_host->hw_ops = &tegra_11x_sdhci_ops; tegra_sdhost_std_freq = TEGRA3_SDHOST_STD_FREQ; + host->mmc->caps2 |= MMC_CAP2_HS200; #endif if (plat->nominal_vcore_uV) |