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authorSteve Wise <swise@opengridcomputing.com>2010-09-13 11:23:57 -0500
committerRoland Dreier <rolandd@cisco.com>2010-09-28 10:46:35 -0700
commitc6d7b26791a2aefdf97f2af1e93161ed05acd631 (patch)
tree61b9b3af001fe5983aa84034d20e44eb43c039a8 /drivers/infiniband/hw/cxgb4/user.h
parentaadc4df3087a33ca7fc37f91a024e7b7efdafa75 (diff)
RDMA/cxgb4: Support on-chip SQs
T4 support on-chip SQs to reduce latency. This patch adds support for this in iw_cxgb4: - Manage ocqp memory like other adapter mem resources. - Allocate user mode SQs from ocqp mem if available. - Map ocqp mem to user process using write combining. - Map PCIE_MA_SYNC reg to user process. Bump uverbs ABI. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb4/user.h')
-rw-r--r--drivers/infiniband/hw/cxgb4/user.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/cxgb4/user.h b/drivers/infiniband/hw/cxgb4/user.h
index ed6414abde02..e6669d54770e 100644
--- a/drivers/infiniband/hw/cxgb4/user.h
+++ b/drivers/infiniband/hw/cxgb4/user.h
@@ -50,7 +50,13 @@ struct c4iw_create_cq_resp {
__u32 qid_mask;
};
+
+enum {
+ C4IW_QPF_ONCHIP = (1<<0)
+};
+
struct c4iw_create_qp_resp {
+ __u64 ma_sync_key;
__u64 sq_key;
__u64 rq_key;
__u64 sq_db_gts_key;
@@ -62,5 +68,6 @@ struct c4iw_create_qp_resp {
__u32 sq_size;
__u32 rq_size;
__u32 qid_mask;
+ __u32 flags;
};
#endif