diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-06-05 16:17:25 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-09 12:02:49 +0200 |
| commit | d6922295e2c29a4a5e8b38f24249887728373e62 (patch) | |
| tree | afd59322ba56f289b84032d88956743e3d722736 /drivers/gpu/drm/tegra | |
| parent | a4263fed284282665c24ca1f3335bddde3a76d57 (diff) | |
drm/tegra: sor - Do not program interlaced mode registers
Interlaced mode is currently not supported on the SOR, so don't program
any associated registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 4e354ee4b203..c06af3db3026 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -849,9 +849,6 @@ static int tegra_output_sor_enable(struct tegra_output *output) value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); - /* XXX interlaced mode */ - tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0)); - /* CSTM (LVDS, link A/B, upper) */ value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | SOR_CSTM_UPPER; |